src/arch/sparc/regfile.hh

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Gabe Black
  29  *          Ali Saidi
  30  */
  31
  32 #ifndef __ARCH_SPARC_REGFILE_HH__
  33 #define __ARCH_SPARC_REGFILE_HH__
  34
  35 #include "arch/sparc/exceptions.hh"
  36 #include "arch/sparc/faults.hh"
  37 #include "base/trace.hh"
  38 #include "sim/byteswap.hh"
  39 #include "cpu/cpuevent.hh"
  40 #include "sim/host.hh"
  41
  42 class Checkpoint;
  43
  44 namespace SparcISA
  45 {
  46
  47     typedef uint8_t  RegIndex;
  48
  49     // MAXTL - maximum trap level
  50     const int MaxPTL = 2;
  51     const int MaxTL  = 6;
  52     const int MaxGL  = 3;
  53     const int MaxPGL = 2;
  54
  55     // NWINDOWS - number of register windows, can be 3 to 32
  56     const int NWindows = 32;
  57
  58     const int AsrStart = 0;
  59     const int PrStart = 32;
  60     const int HprStart = 64;
  61     const int MiscStart = 96;
  62
  63     const uint64_t Bit64 = (1ULL << 63);
  64     class IntRegFile
  65     {
  66       protected:
  67         static const int FrameOffsetBits = 3;
  68         static const int FrameNumBits = 2;
  69
  70         static const int RegsPerFrame = 1 << FrameOffsetBits;
  71         static const int FrameNumMask =
  72                 (FrameNumBits == sizeof(int)) ?
  73                 (unsigned int)(-1) :
  74                 (1 << FrameNumBits) - 1;
  75         static const int FrameOffsetMask =
  76                 (FrameOffsetBits == sizeof(int)) ?
  77                 (unsigned int)(-1) :
  78                 (1 << FrameOffsetBits) - 1;
  79
  80         IntReg regGlobals[MaxGL][RegsPerFrame];
  81         IntReg regSegments[2 * NWindows][RegsPerFrame];
  82
  83         enum regFrame {Globals, Outputs, Locals, Inputs, NumFrames};
  84
  85         IntReg * regView[NumFrames];
  86
  87         static const int RegGlobalOffset = 0;
  88         static const int FrameOffset = MaxGL * RegsPerFrame;
  89         int offset[NumFrames];
  90
  91       public:
  92
  93         int flattenIndex(int reg)
  94         {
  95             int flatIndex = offset[reg >> FrameOffsetBits]
  96                 | (reg & FrameOffsetMask);
  97             DPRINTF(Sparc, "Flattened index %d into %d.\n", reg, flatIndex);
  98             return flatIndex;
  99         }
 100
 101         void clear()
 102         {
 103             int x;
 104             for (x = 0; x < MaxGL; x++)
 105                 memset(regGlobals[x], 0, sizeof(regGlobals[x]));
 106             for(int x = 0; x < 2 * NWindows; x++)
 107                 bzero(regSegments[x], sizeof(regSegments[x]));
 108         }
 109
 110         IntRegFile()
 111         {
 112             offset[Globals] = 0;
 113             regView[Globals] = regGlobals[0];
 114             setCWP(0);
 115             clear();
 116         }
 117
 118         IntReg readReg(int intReg)
 119         {
 120             IntReg val =
 121                 regView[intReg >> FrameOffsetBits][intReg & FrameOffsetMask];
 122             DPRINTF(Sparc, "Read register %d = 0x%x\n", intReg, val);
 123             return val;
 124         }
 125
 126         Fault setReg(int intReg, const IntReg &val)
 127         {
 128             if(intReg)
 129                 DPRINTF(Sparc, "Wrote register %d = 0x%x\n", intReg, val);
 130             regView[intReg >> FrameOffsetBits][intReg & FrameOffsetMask] = val;
 131             return NoFault;
 132         }
 133
 134         //This doesn't effect the actual CWP register.
 135         //It's purpose is to adjust the view of the register file
 136         //to what it would be if CWP = cwp.
 137         void setCWP(int cwp)
 138         {
 139             int index = ((NWindows - cwp) % NWindows) * 2;
 140             offset[Outputs] = FrameOffset + (index * RegsPerFrame);
 141             offset[Locals] = FrameOffset + ((index+1) * RegsPerFrame);
 142             offset[Inputs] = FrameOffset +
 143                 (((index+2) % (NWindows * 2)) * RegsPerFrame);
 144             regView[Outputs] = regSegments[index];
 145             regView[Locals] = regSegments[index+1];
 146             regView[Inputs] = regSegments[(index+2) % (NWindows * 2)];
 147
 148             DPRINTF(Sparc, "Changed the CWP value to %d\n", cwp);
 149         }
 150
 151         void setGlobals(int gl)
 152         {
 153
 154             DPRINTF(Sparc, "Now using %d globals", gl);
 155
 156             regView[Globals] = regGlobals[gl];
 157             offset[Globals] = RegGlobalOffset + gl * RegsPerFrame;
 158         }
 159
 160         void serialize(std::ostream &os);
 161
 162         void unserialize(Checkpoint *cp, const std::string &section);
 163     };
 164
 165     typedef float float32_t;
 166     typedef double float64_t;
 167     //FIXME long double refers to a 10 byte float, rather than a
 168     //16 byte float as required. This data type may have to be emulated.
 169     typedef double float128_t;
 170
 171     class FloatRegFile
 172     {
 173       public:
 174         static const int SingleWidth = 32;
 175         static const int DoubleWidth = 64;
 176         static const int QuadWidth = 128;
 177
 178       protected:
 179
 180         //Since the floating point registers overlap each other,
 181         //A generic storage space is used. The float to be returned is
 182         //pulled from the appropriate section of this region.
 183         char regSpace[(SingleWidth / 8) * NumFloatRegs];
 184
 185       public:
 186
 187         void clear()
 188         {
 189             bzero(regSpace, sizeof(regSpace));
 190         }
 191
 192         FloatReg readReg(int floatReg, int width)
 193         {
 194             //In each of these cases, we have to copy the value into a temporary
 195             //variable. This is because we may otherwise try to access an
 196             //unaligned portion of memory.
 197             switch(width)
 198             {
 199               case SingleWidth:
 200                 float32_t result32;
 201                 memcpy(&result32, regSpace + 4 * floatReg, sizeof(result32));
 202                 return htog(result32);
 203               case DoubleWidth:
 204                 float64_t result64;
 205                 memcpy(&result64, regSpace + 4 * floatReg, sizeof(result64));
 206                 return htog(result64);
 207               case QuadWidth:
 208                 float128_t result128;
 209                 memcpy(&result128, regSpace + 4 * floatReg, sizeof(result128));
 210                 return htog(result128);
 211               default:
 212                 panic("Attempted to read a %d bit floating point register!", width);
 213             }
 214         }
 215
 216         FloatRegBits readRegBits(int floatReg, int width)
 217         {
 218             //In each of these cases, we have to copy the value into a temporary
 219             //variable. This is because we may otherwise try to access an
 220             //unaligned portion of memory.
 221             switch(width)
 222             {
 223               case SingleWidth:
 224                 uint32_t result32;
 225                 memcpy(&result32, regSpace + 4 * floatReg, sizeof(result32));
 226                 return htog(result32);
 227               case DoubleWidth:
 228                 uint64_t result64;
 229                 memcpy(&result64, regSpace + 4 * floatReg, sizeof(result64));
 230                 return htog(result64);
 231               case QuadWidth:
 232                 uint64_t result128;
 233                 memcpy(&result128, regSpace + 4 * floatReg, sizeof(result128));
 234                 return htog(result128);
 235               default:
 236                 panic("Attempted to read a %d bit floating point register!", width);
 237             }
 238         }
 239
 240         Fault setReg(int floatReg, const FloatReg &val, int width)
 241         {
 242             //In each of these cases, we have to copy the value into a temporary
 243             //variable. This is because we may otherwise try to access an
 244             //unaligned portion of memory.
 245
 246             uint32_t result32;
 247             uint64_t result64;
 248             DPRINTF(Sparc, "Setting floating point register %d\n", floatReg);
 249             switch(width)
 250             {
 251               case SingleWidth:
 252                 result32 = gtoh((uint32_t)val);
 253                 memcpy(regSpace + 4 * floatReg, &result32, sizeof(result32));
 254                 break;
 255               case DoubleWidth:
 256                 result64 = gtoh((uint64_t)val);
 257                 memcpy(regSpace + 4 * floatReg, &result64, sizeof(result64));
 258                 break;
 259               case QuadWidth:
 260                 panic("Quad width FP not implemented.");
 261                 break;
 262               default:
 263                 panic("Attempted to read a %d bit floating point register!", width);
 264             }
 265             return NoFault;
 266         }
 267
 268         Fault setRegBits(int floatReg, const FloatRegBits &val, int width)
 269         {
 270             //In each of these cases, we have to copy the value into a temporary
 271             //variable. This is because we may otherwise try to access an
 272             //unaligned portion of memory.
 273             uint32_t result32;
 274             uint64_t result64;
 275             switch(width)
 276             {
 277               case SingleWidth:
 278                 result32 = gtoh((uint32_t)val);
 279                 memcpy(regSpace + 4 * floatReg, &result32, sizeof(result32));
 280                 break;
 281               case DoubleWidth:
 282                 result64 = gtoh((uint64_t)val);
 283                 memcpy(regSpace + 4 * floatReg, &result64, sizeof(result64));
 284                 break;
 285               case QuadWidth:
 286                 panic("Quad width FP not implemented.");
 287                 break;
 288               default:
 289                 panic("Attempted to read a %d bit floating point register!", width);
 290             }
 291             return NoFault;
 292         }
 293
 294         void serialize(std::ostream &os);
 295
 296         void unserialize(Checkpoint *cp, const std::string &section);
 297     };
 298
 299     enum MiscRegIndex
 300     {
 301         /** Ancillary State Registers */
 302         MISCREG_Y  = AsrStart + 0,
 303         MISCREG_CCR = AsrStart + 2,
 304         MISCREG_ASI = AsrStart + 3,
 305         MISCREG_TICK = AsrStart + 4,
 306         MISCREG_PC = AsrStart + 5,
 307         MISCREG_FPRS = AsrStart + 6,
 308         MISCREG_PCR = AsrStart + 16,
 309         MISCREG_PIC = AsrStart + 17,
 310         MISCREG_GSR = AsrStart + 19,
 311         MISCREG_SOFTINT_SET = AsrStart + 20,
 312         MISCREG_SOFTINT_CLR = AsrStart + 21,
 313         MISCREG_SOFTINT = AsrStart + 22,
 314         MISCREG_TICK_CMPR = AsrStart + 23,
 315         MISCREG_STICK = AsrStart + 24,
 316         MISCREG_STICK_CMPR = AsrStart + 25,
 317
 318         /** Privilged Registers */
 319         MISCREG_TPC = PrStart + 0,
 320         MISCREG_TNPC = PrStart + 1,
 321         MISCREG_TSTATE = PrStart + 2,
 322         MISCREG_TT = PrStart + 3,
 323         MISCREG_PRIVTICK = PrStart + 4,
 324         MISCREG_TBA = PrStart + 5,
 325         MISCREG_PSTATE = PrStart + 6,
 326         MISCREG_TL = PrStart + 7,
 327         MISCREG_PIL = PrStart + 8,
 328         MISCREG_CWP = PrStart + 9,
 329         MISCREG_CANSAVE = PrStart + 10,
 330         MISCREG_CANRESTORE = PrStart + 11,
 331         MISCREG_CLEANWIN = PrStart + 12,
 332         MISCREG_OTHERWIN = PrStart + 13,
 333         MISCREG_WSTATE = PrStart + 14,
 334         MISCREG_GL = PrStart + 16,
 335
 336         /** Hyper privileged registers */
 337         MISCREG_HPSTATE = HprStart + 0,
 338         MISCREG_HTSTATE = HprStart + 1,
 339         MISCREG_HINTP = HprStart + 3,
 340         MISCREG_HTBA = HprStart + 5,
 341         MISCREG_HVER = HprStart + 6,
 342         MISCREG_STRAND_STS_REG = HprStart + 16,
 343         MISCREG_HSTICK_CMPR = HprStart + 31,
 344
 345         /** Floating Point Status Register */
 346         MISCREG_FSR = MiscStart + 0
 347
 348     };
 349
 350     // The control registers, broken out into fields
 351     class MiscRegFile
 352     {
 353       private:
 354
 355         /* ASR Registers */
 356         union {
 357             uint64_t y;         // Y (used in obsolete multiplication)
 358             struct {
 359                 uint64_t value:32;      // The actual value stored in y
 360                 uint64_t :32;   // reserved bits
 361             } yFields;
 362         };
 363         union {
 364             uint8_t     ccr;            // Condition Code Register
 365             struct {
 366                 union {
 367                     uint8_t icc:4;      // 32-bit condition codes
 368                     struct {
 369                         uint8_t c:1;    // Carry
 370                         uint8_t v:1;    // Overflow
 371                         uint8_t z:1;    // Zero
 372                         uint8_t n:1;    // Negative
 373                     } iccFields;
 374                 };
 375                 union {
 376                     uint8_t xcc:4;      // 64-bit condition codes
 377                     struct {
 378                         uint8_t c:1;    // Carry
 379                         uint8_t v:1;    // Overflow
 380                         uint8_t z:1;    // Zero
 381                         uint8_t n:1;    // Negative
 382                     } xccFields;
 383                 };
 384             } ccrFields;
 385         };
 386         uint8_t asi;            // Address Space Identifier
 387         union {
 388             uint64_t tick;              // Hardware clock-tick counter
 389             struct {
 390                 int64_t counter:63;     // Clock-tick count
 391                 uint64_t npt:1;         // Non-priveleged trap
 392             } tickFields;
 393         };
 394         union {
 395             uint8_t             fprs;   // Floating-Point Register State
 396             struct {
 397                 uint8_t dl:1;           // Dirty lower
 398                 uint8_t du:1;           // Dirty upper
 399                 uint8_t fef:1;          // FPRS enable floating-Point
 400             } fprsFields;
 401         };
 402         union {
 403             uint64_t softint;
 404             struct {
 405                 uint64_t tm:1;
 406                 uint64_t int_level:14;
 407                 uint64_t sm:1;
 408             } softintFields;
 409         };
 410         union {
 411             uint64_t tick_cmpr;         // Hardware tick compare registers
 412             struct {
 413                 uint64_t tick_cmpr:63;  // Clock-tick count
 414                 uint64_t int_dis:1;             // Non-priveleged trap
 415             } tick_cmprFields;
 416         };
 417         union {
 418             uint64_t stick;             // Hardware clock-tick counter
 419             struct {
 420                 int64_t :63;    // Not used, storage in SparcSystem
 421                 uint64_t npt:1;         // Non-priveleged trap
 422             } stickFields;
 423         };
 424         union {
 425             uint64_t stick_cmpr;                // Hardware tick compare registers
 426             struct {
 427                 uint64_t tick_cmpr:63;  // Clock-tick count
 428                 uint64_t int_dis:1;             // Non-priveleged trap
 429             } stick_cmprFields;
 430         };
 431
 432
 433         /* Privileged Registers */
 434         uint64_t tpc[MaxTL];    // Trap Program Counter (value from
 435                                 // previous trap level)
 436         uint64_t tnpc[MaxTL];   // Trap Next Program Counter (value from
 437                                 // previous trap level)
 438         union {
 439             uint64_t tstate[MaxTL];     // Trap State
 440             struct {
 441                 //Values are from previous trap level
 442                 uint64_t cwp:5;         // Current Window Pointer
 443                 uint64_t :3;    // Reserved bits
 444                 uint64_t pstate:13;     // Process State
 445                 uint64_t :3;    // Reserved bits
 446                 uint64_t asi:8;         // Address Space Identifier
 447                 uint64_t ccr:8;         // Condition Code Register
 448                 uint64_t gl:8;          // Global level
 449             } tstateFields[MaxTL];
 450         };
 451         uint16_t tt[MaxTL];     // Trap Type (Type of trap which occured
 452                                 // on the previous level)
 453         uint64_t tba;           // Trap Base Address
 454
 455         union {
 456             uint16_t pstate;            // Process State Register
 457             struct {
 458                 uint16_t :1;            // reserved
 459                 uint16_t ie:1;          // Interrupt enable
 460                 uint16_t priv:1;        // Privelege mode
 461                 uint16_t am:1;          // Address mask
 462                 uint16_t pef:1;         // PSTATE enable floating-point
 463                 uint16_t :1;            // reserved2
 464                 uint16_t mm:2;          // Memory Model
 465                 uint16_t tle:1;         // Trap little-endian
 466                 uint16_t cle:1;         // Current little-endian
 467             } pstateFields;
 468         };
 469         uint8_t tl;             // Trap Level
 470         uint8_t pil;            // Process Interrupt Register
 471         uint8_t cwp;            // Current Window Pointer
 472         uint8_t cansave;        // Savable windows
 473         uint8_t canrestore;     // Restorable windows
 474         uint8_t cleanwin;       // Clean windows
 475         uint8_t otherwin;       // Other windows
 476         union {
 477             uint8_t wstate;             // Window State
 478             struct {
 479                 uint8_t normal:3;       // Bits TT<4:2> are set to on a normal
 480                                         // register window trap
 481                 uint8_t other:3;        // Bits TT<4:2> are set to on an "otherwin"
 482                                         // register window trap
 483             } wstateFields;
 484         };
 485         uint8_t gl;             // Global level register
 486
 487
 488         /** Hyperprivileged Registers */
 489         union {
 490             uint64_t hpstate; // Hyperprivileged State Register
 491             struct {
 492                 uint8_t tlz: 1;
 493                 uint8_t :1;
 494                 uint8_t hpriv:1;
 495                 uint8_t :2;
 496                 uint8_t red:1;
 497                 uint8_t :4;
 498                 uint8_t ibe:1;
 499                 uint8_t id:1;
 500             } hpstateFields;
 501         };
 502
 503         uint64_t htstate[MaxTL]; // Hyperprivileged Trap State Register
 504         uint64_t hintp;
 505         uint64_t htba; // Hyperprivileged Trap Base Address register
 506         union {
 507             uint64_t hstick_cmpr;               // Hardware tick compare registers
 508             struct {
 509                 uint64_t tick_cmpr:63;  // Clock-tick count
 510                 uint64_t int_dis:1;             // Non-priveleged trap
 511             } hstick_cmprFields;
 512         };
 513
 514         uint64_t strandStatusReg; // Per strand status register
 515
 516
 517         /** Floating point misc registers. */
 518         union {
 519             uint64_t    fsr;    // Floating-Point State Register
 520             struct {
 521                 union {
 522                     uint64_t cexc:5;    // Current excpetion
 523                     struct {
 524                         uint64_t nxc:1;         // Inexact
 525                         uint64_t dzc:1;         // Divide by zero
 526                         uint64_t ufc:1;         // Underflow
 527                         uint64_t ofc:1;         // Overflow
 528                         uint64_t nvc:1;         // Invalid operand
 529                     } cexcFields;
 530                 };
 531                 union {
 532                     uint64_t aexc:5;            // Accrued exception
 533                     struct {
 534                         uint64_t nxc:1;         // Inexact
 535                         uint64_t dzc:1;         // Divide by zero
 536                         uint64_t ufc:1;         // Underflow
 537                         uint64_t ofc:1;         // Overflow
 538                         uint64_t nvc:1;         // Invalid operand
 539                     } aexcFields;
 540                 };
 541                 uint64_t fcc0:2;                // Floating-Point condtion codes
 542                 uint64_t :1;            // Reserved bits
 543                 uint64_t qne:1;                 // Deferred trap queue not empty
 544                                                 // with no queue, it should read 0
 545                 uint64_t ftt:3;                 // Floating-Point trap type
 546                 uint64_t ver:3;                 // Version (of the FPU)
 547                 uint64_t :2;            // Reserved bits
 548                 uint64_t ns:1;                  // Nonstandard floating point
 549                 union {
 550                     uint64_t tem:5;                     // Trap Enable Mask
 551                     struct {
 552                         uint64_t nxm:1;         // Inexact
 553                         uint64_t dzm:1;         // Divide by zero
 554                         uint64_t ufm:1;         // Underflow
 555                         uint64_t ofm:1;         // Overflow
 556                         uint64_t nvm:1;         // Invalid operand
 557                     } temFields;
 558                 };
 559                 uint64_t :2;            // Reserved bits
 560                 uint64_t rd:2;                  // Rounding direction
 561                 uint64_t fcc1:2;                // Floating-Point condition codes
 562                 uint64_t fcc2:2;                // Floating-Point condition codes
 563                 uint64_t fcc3:2;                // Floating-Point condition codes
 564                 uint64_t :26;           // Reserved bits
 565             } fsrFields;
 566         };
 567
 568         // These need to check the int_dis field and if 0 then
 569         // set appropriate bit in softint and checkinterrutps on the cpu
 570 #if FULL_SYSTEM
 571         /** Process a tick compare event and generate an interrupt on the cpu if
 572          * appropriate. */
 573         void processTickCompare(ThreadContext *tc);
 574         void processSTickCompare(ThreadContext *tc);
 575         void processHSTickCompare(ThreadContext *tc);
 576
 577         typedef CpuEventWrapper<MiscRegFile,
 578                 &MiscRegFile::processTickCompare> TickCompareEvent;
 579         TickCompareEvent *tickCompare;
 580
 581         typedef CpuEventWrapper<MiscRegFile,
 582                 &MiscRegFile::processSTickCompare> STickCompareEvent;
 583         STickCompareEvent *sTickCompare;
 584
 585         typedef CpuEventWrapper<MiscRegFile,
 586                 &MiscRegFile::processHSTickCompare> HSTickCompareEvent;
 587         HSTickCompareEvent *hSTickCompare;
 588
 589         /** Fullsystem only register version of ReadRegWithEffect() */
 590         MiscReg readFSRegWithEffect(int miscReg, Fault &fault, ThreadContext *tc);
 591         /** Fullsystem only register version of SetRegWithEffect() */
 592         Fault setFSRegWithEffect(int miscReg, const MiscReg &val,
 593                 ThreadContext * tc);
 594 #endif
 595       public:
 596
 597         void reset()
 598         {
 599             pstateFields.pef = 0; //No FPU
 600             //pstateFields.pef = 1; //FPU
 601 #if FULL_SYSTEM
 602             //For SPARC, when a system is first started, there is a power
 603             //on reset Trap which sets the processor into the following state.
 604             //Bits that aren't set aren't defined on startup.
 605             tl = MaxTL;
 606             gl = MaxGL;
 607
 608             tickFields.counter = 0; //The TICK register is unreadable bya
 609             tickFields.npt = 1; //The TICK register is unreadable by by !priv
 610
 611             softint = 0; // Clear all the soft interrupt bits
 612             tick_cmprFields.int_dis = 1; // disable timer compare interrupts
 613             tick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
 614             stickFields.npt = 1; //The TICK register is unreadable by by !priv
 615             stick_cmprFields.int_dis = 1; // disable timer compare interrupts
 616             stick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
 617
 618
 619             tt[tl] = power_on_reset;
 620             pstate = 0; // fields 0 but pef
 621             pstateFields.pef = 1;
 622
 623             hpstate = 0;
 624             hpstateFields.red = 1;
 625             hpstateFields.hpriv = 1;
 626             hpstateFields.tlz = 0; // this is a guess
 627             hintp = 0; // no interrupts pending
 628             hstick_cmprFields.int_dis = 1; // disable timer compare interrupts
 629             hstick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
 630 #else
 631 /*          //This sets up the initial state of the processor for usermode processes
 632             pstateFields.priv = 0; //Process runs in user mode
 633             pstateFields.ie = 1; //Interrupts are enabled
 634             fsrFields.rd = 0; //Round to nearest
 635             fsrFields.tem = 0; //Floating point traps not enabled
 636             fsrFields.ns = 0; //Non standard mode off
 637             fsrFields.qne = 0; //Floating point queue is empty
 638             fsrFields.aexc = 0; //No accrued exceptions
 639             fsrFields.cexc = 0; //No current exceptions
 640
 641             //Register window management registers
 642             otherwin = 0; //No windows contain info from other programs
 643             canrestore = 0; //There are no windows to pop
 644             cansave = MaxTL - 2; //All windows are available to save into
 645             cleanwin = MaxTL;*/
 646 #endif
 647         }
 648
 649         MiscRegFile()
 650         {
 651             reset();
 652         }
 653
 654         /** read a value out of an either an SE or FS IPR. No checking is done
 655          * about SE vs. FS as this is mostly used to copy the regfile. Thus more
 656          * register are copied that are necessary for FS. However this prevents
 657          * a bunch of ifdefs and is rarely called so is not performance
 658          * criticial. */
 659         MiscReg readReg(int miscReg);
 660
 661         /** Read a value from an IPR. Only the SE iprs are here and the rest
 662          * are are readFSRegWithEffect (which is called by readRegWithEffect()).
 663          * Checking is done for permission based on state bits in the miscreg
 664          * file. */
 665         MiscReg readRegWithEffect(int miscReg, Fault &fault, ThreadContext *tc);
 666
 667         /** write a value into an either an SE or FS IPR. No checking is done
 668          * about SE vs. FS as this is mostly used to copy the regfile. Thus more
 669          * register are copied that are necessary for FS. However this prevents
 670          * a bunch of ifdefs and is rarely called so is not performance
 671          * criticial.*/
 672         Fault setReg(int miscReg, const MiscReg &val);
 673
 674         /** Write a value into an IPR. Only the SE iprs are here and the rest
 675          * are are setFSRegWithEffect (which is called by setRegWithEffect()).
 676          * Checking is done for permission based on state bits in the miscreg
 677          * file. */
 678         Fault setRegWithEffect(int miscReg,
 679                 const MiscReg &val, ThreadContext * tc);
 680
 681         void serialize(std::ostream & os);
 682
 683         void unserialize(Checkpoint * cp, const std::string & section);
 684
 685         void copyMiscRegs(ThreadContext * tc);
 686
 687       protected:
 688
 689         bool isHyperPriv() { return hpstateFields.hpriv; }
 690         bool isPriv() { return hpstateFields.hpriv || pstateFields.priv; }
 691         bool isNonPriv() { return !isPriv(); }
 692     };
 693
 694     typedef union
 695     {
 696         IntReg  intreg;
 697         FloatReg   fpreg;
 698         MiscReg ctrlreg;
 699     } AnyReg;
 700
 701     class RegFile
 702     {
 703       protected:
 704         Addr pc;                // Program Counter
 705         Addr npc;               // Next Program Counter
 706         Addr nnpc;
 707
 708       public:
 709         Addr readPC()
 710         {
 711             return pc;
 712         }
 713
 714         void setPC(Addr val)
 715         {
 716             pc = val;
 717         }
 718
 719         Addr readNextPC()
 720         {
 721             return npc;
 722         }
 723
 724         void setNextPC(Addr val)
 725         {
 726             npc = val;
 727         }
 728
 729         Addr readNextNPC()
 730         {
 731             return nnpc;
 732         }
 733
 734         void setNextNPC(Addr val)
 735         {
 736             nnpc = val;
 737         }
 738
 739       protected:
 740         IntRegFile intRegFile;          // integer register file
 741         FloatRegFile floatRegFile;      // floating point register file
 742         MiscRegFile miscRegFile;        // control register file
 743
 744       public:
 745
 746         void clear()
 747         {
 748             intRegFile.clear();
 749             floatRegFile.clear();
 750         }
 751
 752         int FlattenIntIndex(int reg)
 753         {
 754             return intRegFile.flattenIndex(reg);
 755         }
 756
 757         MiscReg readMiscReg(int miscReg)
 758         {
 759             return miscRegFile.readReg(miscReg);
 760         }
 761
 762         MiscReg readMiscRegWithEffect(int miscReg,
 763                 Fault &fault, ThreadContext *tc)
 764         {
 765             return miscRegFile.readRegWithEffect(miscReg, fault, tc);
 766         }
 767
 768         Fault setMiscReg(int miscReg, const MiscReg &val)
 769         {
 770             return miscRegFile.setReg(miscReg, val);
 771         }
 772
 773         Fault setMiscRegWithEffect(int miscReg, const MiscReg &val,
 774                 ThreadContext * tc)
 775         {
 776             return miscRegFile.setRegWithEffect(miscReg, val, tc);
 777         }
 778
 779         FloatReg readFloatReg(int floatReg, int width)
 780         {
 781             return floatRegFile.readReg(floatReg, width);
 782         }
 783
 784         FloatReg readFloatReg(int floatReg)
 785         {
 786             //Use the "natural" width of a single float
 787             return floatRegFile.readReg(floatReg, FloatRegFile::SingleWidth);
 788         }
 789
 790         FloatRegBits readFloatRegBits(int floatReg, int width)
 791         {
 792             return floatRegFile.readRegBits(floatReg, width);
 793         }
 794
 795         FloatRegBits readFloatRegBits(int floatReg)
 796         {
 797             //Use the "natural" width of a single float
 798             return floatRegFile.readRegBits(floatReg,
 799                     FloatRegFile::SingleWidth);
 800         }
 801
 802         Fault setFloatReg(int floatReg, const FloatReg &val, int width)
 803         {
 804             return floatRegFile.setReg(floatReg, val, width);
 805         }
 806
 807         Fault setFloatReg(int floatReg, const FloatReg &val)
 808         {
 809             //Use the "natural" width of a single float
 810             return setFloatReg(floatReg, val, FloatRegFile::SingleWidth);
 811         }
 812
 813         Fault setFloatRegBits(int floatReg, const FloatRegBits &val, int width)
 814         {
 815             return floatRegFile.setRegBits(floatReg, val, width);
 816         }
 817
 818         Fault setFloatRegBits(int floatReg, const FloatRegBits &val)
 819         {
 820             //Use the "natural" width of a single float
 821             return floatRegFile.setRegBits(floatReg, val,
 822                     FloatRegFile::SingleWidth);
 823         }
 824
 825         IntReg readIntReg(int intReg)
 826         {
 827             return intRegFile.readReg(intReg);
 828         }
 829
 830         Fault setIntReg(int intReg, const IntReg &val)
 831         {
 832             return intRegFile.setReg(intReg, val);
 833         }
 834
 835         void serialize(std::ostream &os);
 836         void unserialize(Checkpoint *cp, const std::string &section);
 837
 838       public:
 839
 840         enum ContextParam
 841         {
 842             CONTEXT_CWP,
 843             CONTEXT_GLOBALS
 844         };
 845         typedef int ContextVal;
 846
 847         void changeContext(ContextParam param, ContextVal val)
 848         {
 849             switch(param)
 850             {
 851               case CONTEXT_CWP:
 852                 intRegFile.setCWP(val);
 853                 break;
 854               case CONTEXT_GLOBALS:
 855                 intRegFile.setGlobals(val);
 856                 break;
 857               default:
 858                 panic("Tried to set illegal context parameter in the SPARC regfile.\n");
 859             }
 860         }
 861     };
 862
 863     void copyRegs(ThreadContext *src, ThreadContext *dest);
 864
 865     void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
 866
 867     int InterruptLevel(uint64_t softint);
 868
 869 } // namespace SparcISA
 870
 871 #endif