src/arch/sparc/regfile.hh

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Gabe Black
  29  *          Ali Saidi
  30  */
  31
  32 #ifndef __ARCH_SPARC_REGFILE_HH__
  33 #define __ARCH_SPARC_REGFILE_HH__
  34
  35 #include "arch/sparc/floatregfile.hh"
  36 #include "arch/sparc/intregfile.hh"
  37 #include "arch/sparc/isa_traits.hh"
  38 #include "arch/sparc/miscregfile.hh"
  39 #include "arch/sparc/types.hh"
  40 #include "sim/host.hh"
  41
  42 #include <string>
  43
  44 class Checkpoint;
  45
  46 namespace SparcISA
  47 {
  48     class RegFile
  49     {
  50       protected:
  51         Addr pc;                // Program Counter
  52         Addr npc;               // Next Program Counter
  53         Addr nnpc;
  54
  55       public:
  56         Addr readPC();
  57         void setPC(Addr val);
  58
  59         Addr readNextPC();
  60         void setNextPC(Addr val);
  61
  62         Addr readNextNPC();
  63         void setNextNPC(Addr val);
  64
  65       protected:
  66         IntRegFile intRegFile;          // integer register file
  67         FloatRegFile floatRegFile;      // floating point register file
  68         MiscRegFile miscRegFile;        // control register file
  69
  70       public:
  71
  72         void clear();
  73
  74         int FlattenIntIndex(int reg);
  75
  76         MiscReg readMiscRegNoEffect(int miscReg);
  77
  78         MiscReg readMiscReg(int miscReg, ThreadContext *tc);
  79
  80         void setMiscRegNoEffect(int miscReg, const MiscReg &val);
  81
  82         void setMiscReg(int miscReg, const MiscReg &val,
  83                 ThreadContext * tc);
  84
  85         int instAsid()
  86         {
  87             return miscRegFile.getInstAsid();
  88         }
  89
  90         int dataAsid()
  91         {
  92             return miscRegFile.getDataAsid();
  93         }
  94
  95         FloatReg readFloatReg(int floatReg, int width);
  96
  97         FloatReg readFloatReg(int floatReg);
  98
  99         FloatRegBits readFloatRegBits(int floatReg, int width);
 100
 101         FloatRegBits readFloatRegBits(int floatReg);
 102
 103         void setFloatReg(int floatReg, const FloatReg &val, int width);
 104
 105         void setFloatReg(int floatReg, const FloatReg &val);
 106
 107         void setFloatRegBits(int floatReg, const FloatRegBits &val, int width);
 108
 109         void setFloatRegBits(int floatReg, const FloatRegBits &val);
 110
 111         IntReg readIntReg(int intReg);
 112
 113         void setIntReg(int intReg, const IntReg &val);
 114
 115         void serialize(std::ostream &os);
 116         void unserialize(Checkpoint *cp, const std::string &section);
 117
 118       public:
 119
 120         void changeContext(RegContextParam param, RegContextVal val);
 121     };
 122
 123     int flattenIntIndex(ThreadContext * tc, int reg);
 124
 125     int flattenFloatIndex(ThreadContext * tc, int reg)
 126     {
 127         return reg;
 128     }
 129
 130     void copyRegs(ThreadContext *src, ThreadContext *dest);
 131
 132     void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
 133
 134 } // namespace SparcISA
 135
 136 #endif