2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
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12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 #include "arch/sparc/asi.hh"
34 #include "arch/sparc/registers.hh"
35 #include "arch/sparc/tlb.hh"
36 #include "base/bitfield.hh"
37 #include "base/trace.hh"
38 #include "cpu/thread_context.hh"
39 #include "cpu/base.hh"
40 #include "mem/packet_access.hh"
41 #include "mem/request.hh"
42 #include "sim/system.hh"
44 /* @todo remove some of the magic constants. -- ali
48 TLB::TLB(const Params
*p
)
49 : BaseTLB(p
), size(p
->size
), usedEntries(0), lastReplaced(0),
52 // To make this work you'll have to change the hypervisor and OS
54 fatal("SPARC T1 TLB registers don't support more than 64 TLB entries");
56 tlb
= new TlbEntry
[size
];
57 std::memset(tlb
, 0, sizeof(TlbEntry
) * size
);
59 for (int x
= 0; x
< size
; x
++)
60 freeList
.push_back(&tlb
[x
]);
79 for (i
= lookupTable
.begin(); i
!= lookupTable
.end(); i
++) {
80 TlbEntry
*t
= i
->second
;
81 if (!t
->pte
.locked()) {
90 TLB::insert(Addr va
, int partition_id
, int context_id
, bool real
,
91 const PageTableEntry
& PTE
, int entry
)
94 TlbEntry
*new_entry
= NULL
;
99 va
&= ~(PTE
.size()-1);
101 tr.size = PTE.size() - 1;
102 tr.contextId = context_id;
103 tr.partitionId = partition_id;
108 "TLB: Inserting Entry; va=%#x pa=%#x pid=%d cid=%d r=%d entryid=%d\n",
109 va
, PTE
.paddr(), partition_id
, context_id
, (int)real
, entry
);
111 // Demap any entry that conflicts
112 for (x
= 0; x
< size
; x
++) {
113 if (tlb
[x
].range
.real
== real
&&
114 tlb
[x
].range
.partitionId
== partition_id
&&
115 tlb
[x
].range
.va
< va
+ PTE
.size() - 1 &&
116 tlb
[x
].range
.va
+ tlb
[x
].range
.size
>= va
&&
117 (real
|| tlb
[x
].range
.contextId
== context_id
))
120 freeList
.push_front(&tlb
[x
]);
121 DPRINTF(TLB
, "TLB: Conflicting entry %#X , deleting it\n", x
);
123 tlb
[x
].valid
= false;
128 lookupTable
.erase(tlb
[x
].range
);
134 i = lookupTable.find(tr);
135 if (i != lookupTable.end()) {
136 i->second->valid = false;
137 if (i->second->used) {
138 i->second->used = false;
141 freeList.push_front(i->second);
142 DPRINTF(TLB, "TLB: Found conflicting entry %#X , deleting it\n",
144 lookupTable.erase(i);
149 assert(entry
< size
&& entry
>= 0);
150 new_entry
= &tlb
[entry
];
152 if (!freeList
.empty()) {
153 new_entry
= freeList
.front();
160 if (x
== lastReplaced
)
161 goto insertAllLocked
;
162 } while (tlb
[x
].pte
.locked());
167 for (x = 0; x < size; x++) {
168 if (!tlb[x].valid || !tlb[x].used) {
176 // Update the last ently if their all locked
178 new_entry
= &tlb
[size
-1];
181 freeList
.remove(new_entry
);
182 if (new_entry
->valid
&& new_entry
->used
)
184 if (new_entry
->valid
)
185 lookupTable
.erase(new_entry
->range
);
189 new_entry
->range
.va
= va
;
190 new_entry
->range
.size
= PTE
.size() - 1;
191 new_entry
->range
.partitionId
= partition_id
;
192 new_entry
->range
.contextId
= context_id
;
193 new_entry
->range
.real
= real
;
194 new_entry
->pte
= PTE
;
195 new_entry
->used
= true;;
196 new_entry
->valid
= true;
199 i
= lookupTable
.insert(new_entry
->range
, new_entry
);
200 assert(i
!= lookupTable
.end());
202 // If all entries have their used bit set, clear it on them all,
203 // but the one we just inserted
204 if (usedEntries
== size
) {
206 new_entry
->used
= true;
213 TLB::lookup(Addr va
, int partition_id
, bool real
, int context_id
,
220 DPRINTF(TLB
, "TLB: Looking up entry va=%#x pid=%d cid=%d r=%d\n",
221 va
, partition_id
, context_id
, real
);
222 // Assemble full address structure
225 tr
.contextId
= context_id
;
226 tr
.partitionId
= partition_id
;
229 // Try to find the entry
230 i
= lookupTable
.find(tr
);
231 if (i
== lookupTable
.end()) {
232 DPRINTF(TLB
, "TLB: No valid entry found\n");
236 // Mark the entries used bit and clear other used bits in needed
238 DPRINTF(TLB
, "TLB: Valid entry found pa: %#x size: %#x\n", t
->pte
.paddr(),
241 // Update the used bits only if this is a real access (not a fake
242 // one from virttophys()
243 if (!t
->used
&& update_used
) {
246 if (usedEntries
== size
) {
260 for (int x
= 0; x
< size
; x
++) {
262 DPRINTFN("%4d: %#2x:%#2x %c %#4x %#8x %#8x %#16x\n",
263 x
, tlb
[x
].range
.partitionId
, tlb
[x
].range
.contextId
,
264 tlb
[x
].range
.real
? 'R' : ' ', tlb
[x
].range
.size
,
265 tlb
[x
].range
.va
, tlb
[x
].pte
.paddr(), tlb
[x
].pte());
271 TLB::demapPage(Addr va
, int partition_id
, bool real
, int context_id
)
276 DPRINTF(IPR
, "TLB: Demapping Page va=%#x pid=%#d cid=%d r=%d\n",
277 va
, partition_id
, context_id
, real
);
281 // Assemble full address structure
284 tr
.contextId
= context_id
;
285 tr
.partitionId
= partition_id
;
288 // Demap any entry that conflicts
289 i
= lookupTable
.find(tr
);
290 if (i
!= lookupTable
.end()) {
291 DPRINTF(IPR
, "TLB: Demapped page\n");
292 i
->second
->valid
= false;
293 if (i
->second
->used
) {
294 i
->second
->used
= false;
297 freeList
.push_front(i
->second
);
298 lookupTable
.erase(i
);
303 TLB::demapContext(int partition_id
, int context_id
)
305 DPRINTF(IPR
, "TLB: Demapping Context pid=%#d cid=%d\n",
306 partition_id
, context_id
);
308 for (int x
= 0; x
< size
; x
++) {
309 if (tlb
[x
].range
.contextId
== context_id
&&
310 tlb
[x
].range
.partitionId
== partition_id
) {
311 if (tlb
[x
].valid
== true) {
312 freeList
.push_front(&tlb
[x
]);
314 tlb
[x
].valid
= false;
319 lookupTable
.erase(tlb
[x
].range
);
325 TLB::demapAll(int partition_id
)
327 DPRINTF(TLB
, "TLB: Demapping All pid=%#d\n", partition_id
);
329 for (int x
= 0; x
< size
; x
++) {
330 if (tlb
[x
].valid
&& !tlb
[x
].pte
.locked() &&
331 tlb
[x
].range
.partitionId
== partition_id
) {
332 freeList
.push_front(&tlb
[x
]);
333 tlb
[x
].valid
= false;
338 lookupTable
.erase(tlb
[x
].range
);
349 for (int x
= 0; x
< size
; x
++) {
350 if (tlb
[x
].valid
== true)
351 freeList
.push_back(&tlb
[x
]);
352 tlb
[x
].valid
= false;
359 TLB::TteRead(int entry
)
362 panic("entry: %d\n", entry
);
364 assert(entry
< size
);
365 if (tlb
[entry
].valid
)
366 return tlb
[entry
].pte();
368 return (uint64_t)-1ll;
372 TLB::TagRead(int entry
)
374 assert(entry
< size
);
376 if (!tlb
[entry
].valid
)
377 return (uint64_t)-1ll;
379 tag
= tlb
[entry
].range
.contextId
;
380 tag
|= tlb
[entry
].range
.va
;
381 tag
|= (uint64_t)tlb
[entry
].range
.partitionId
<< 61;
382 tag
|= tlb
[entry
].range
.real
? ULL(1) << 60 : 0;
383 tag
|= (uint64_t)~tlb
[entry
].pte
._size() << 56;
388 TLB::validVirtualAddress(Addr va
, bool am
)
392 if (va
>= StartVAddrHole
&& va
<= EndVAddrHole
)
398 TLB::writeSfsr(bool write
, ContextType ct
, bool se
, FaultTypes ft
, int asi
)
415 TLB::writeTagAccess(Addr va
, int context
)
417 DPRINTF(TLB
, "TLB: Writing Tag Access: va: %#X ctx: %#X value: %#X\n",
418 va
, context
, mbits(va
, 63,13) | mbits(context
,12,0));
420 tag_access
= mbits(va
, 63,13) | mbits(context
,12,0);
424 TLB::writeSfsr(Addr a
, bool write
, ContextType ct
,
425 bool se
, FaultTypes ft
, int asi
)
427 DPRINTF(TLB
, "TLB: Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n",
428 a
, (int)write
, ct
, ft
, asi
);
429 TLB::writeSfsr(write
, ct
, se
, ft
, asi
);
434 TLB::translateInst(RequestPtr req
, ThreadContext
*tc
)
436 uint64_t tlbdata
= tc
->readMiscRegNoEffect(MISCREG_TLB_DATA
);
438 Addr vaddr
= req
->getVaddr();
441 assert(req
->getAsi() == ASI_IMPLICIT
);
443 DPRINTF(TLB
, "TLB: ITB Request to translate va=%#x size=%d\n",
444 vaddr
, req
->getSize());
446 // Be fast if we can!
447 if (cacheValid
&& cacheState
== tlbdata
) {
449 if (cacheEntry
[0]->range
.va
< vaddr
+ sizeof(MachInst
) &&
450 cacheEntry
[0]->range
.va
+ cacheEntry
[0]->range
.size
>= vaddr
) {
451 req
->setPaddr(cacheEntry
[0]->pte
.translate(vaddr
));
455 req
->setPaddr(vaddr
& PAddrImplMask
);
460 bool hpriv
= bits(tlbdata
,0,0);
461 bool red
= bits(tlbdata
,1,1);
462 bool priv
= bits(tlbdata
,2,2);
463 bool addr_mask
= bits(tlbdata
,3,3);
464 bool lsu_im
= bits(tlbdata
,4,4);
466 int part_id
= bits(tlbdata
,15,8);
467 int tl
= bits(tlbdata
,18,16);
468 int pri_context
= bits(tlbdata
,47,32);
474 DPRINTF(TLB
, "TLB: priv:%d hpriv:%d red:%d lsuim:%d part_id: %#X\n",
475 priv
, hpriv
, red
, lsu_im
, part_id
);
484 context
= pri_context
;
487 if ( hpriv
|| red
) {
489 cacheState
= tlbdata
;
490 cacheEntry
[0] = NULL
;
491 req
->setPaddr(vaddr
& PAddrImplMask
);
495 // If the access is unaligned trap
497 writeSfsr(false, ct
, false, OtherFault
, asi
);
498 return new MemAddressNotAligned
;
502 vaddr
= vaddr
& VAddrAMask
;
504 if (!validVirtualAddress(vaddr
, addr_mask
)) {
505 writeSfsr(false, ct
, false, VaOutOfRange
, asi
);
506 return new InstructionAccessException
;
510 e
= lookup(vaddr
, part_id
, true);
514 e
= lookup(vaddr
, part_id
, false, context
);
517 if (e
== NULL
|| !e
->valid
) {
518 writeTagAccess(vaddr
, context
);
520 return new InstructionRealTranslationMiss
;
523 return new FastInstructionAccessMMUMiss
;
525 return new FastInstructionAccessMMUMiss(req
->getVaddr());
529 // were not priviledged accesing priv page
530 if (!priv
&& e
->pte
.priv()) {
531 writeTagAccess(vaddr
, context
);
532 writeSfsr(false, ct
, false, PrivViolation
, asi
);
533 return new InstructionAccessException
;
536 // cache translation date for next translation
538 cacheState
= tlbdata
;
541 req
->setPaddr(e
->pte
.translate(vaddr
));
542 DPRINTF(TLB
, "TLB: %#X -> %#X\n", vaddr
, req
->getPaddr());
547 TLB::translateData(RequestPtr req
, ThreadContext
*tc
, bool write
)
550 * @todo this could really use some profiling and fixing to make
553 uint64_t tlbdata
= tc
->readMiscRegNoEffect(MISCREG_TLB_DATA
);
554 Addr vaddr
= req
->getVaddr();
555 Addr size
= req
->getSize();
557 asi
= (ASI
)req
->getAsi();
558 bool implicit
= false;
559 bool hpriv
= bits(tlbdata
,0,0);
560 bool unaligned
= vaddr
& (size
- 1);
562 DPRINTF(TLB
, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n",
565 if (lookupTable
.size() != 64 - freeList
.size())
566 panic("Lookup table size: %d tlb size: %d\n", lookupTable
.size(),
568 if (asi
== ASI_IMPLICIT
)
571 // Only use the fast path here if there doesn't need to be an unaligned
574 if (hpriv
&& implicit
) {
575 req
->setPaddr(vaddr
& PAddrImplMask
);
579 // Be fast if we can!
580 if (cacheValid
&& cacheState
== tlbdata
) {
585 TlbEntry
*ce
= cacheEntry
[0];
586 Addr ce_va
= ce
->range
.va
;
587 if (cacheAsi
[0] == asi
&&
588 ce_va
< vaddr
+ size
&& ce_va
+ ce
->range
.size
> vaddr
&&
589 (!write
|| ce
->pte
.writable())) {
590 req
->setPaddr(ce
->pte
.translate(vaddr
));
591 if (ce
->pte
.sideffect() || (ce
->pte
.paddr() >> 39) & 1)
592 req
->setFlags(Request::UNCACHEABLE
);
593 DPRINTF(TLB
, "TLB: %#X -> %#X\n", vaddr
, req
->getPaddr());
596 } // if cache entry valid
598 TlbEntry
*ce
= cacheEntry
[1];
599 Addr ce_va
= ce
->range
.va
;
600 if (cacheAsi
[1] == asi
&&
601 ce_va
< vaddr
+ size
&& ce_va
+ ce
->range
.size
> vaddr
&&
602 (!write
|| ce
->pte
.writable())) {
603 req
->setPaddr(ce
->pte
.translate(vaddr
));
604 if (ce
->pte
.sideffect() || (ce
->pte
.paddr() >> 39) & 1)
605 req
->setFlags(Request::UNCACHEABLE
);
606 DPRINTF(TLB
, "TLB: %#X -> %#X\n", vaddr
, req
->getPaddr());
609 } // if cache entry valid
613 bool red
= bits(tlbdata
,1,1);
614 bool priv
= bits(tlbdata
,2,2);
615 bool addr_mask
= bits(tlbdata
,3,3);
616 bool lsu_dm
= bits(tlbdata
,5,5);
618 int part_id
= bits(tlbdata
,15,8);
619 int tl
= bits(tlbdata
,18,16);
620 int pri_context
= bits(tlbdata
,47,32);
621 int sec_context
= bits(tlbdata
,63,48);
624 ContextType ct
= Primary
;
629 DPRINTF(TLB
, "TLB: priv:%d hpriv:%d red:%d lsudm:%d part_id: %#X\n",
630 priv
, hpriv
, red
, lsu_dm
, part_id
);
640 context
= pri_context
;
643 // We need to check for priv level/asi priv
644 if (!priv
&& !hpriv
&& !AsiIsUnPriv(asi
)) {
645 // It appears that context should be Nucleus in these cases?
646 writeSfsr(vaddr
, write
, Nucleus
, false, IllegalAsi
, asi
);
647 return new PrivilegedAction
;
650 if (!hpriv
&& AsiIsHPriv(asi
)) {
651 writeSfsr(vaddr
, write
, Nucleus
, false, IllegalAsi
, asi
);
652 return new DataAccessException
;
655 if (AsiIsPrimary(asi
)) {
656 context
= pri_context
;
658 } else if (AsiIsSecondary(asi
)) {
659 context
= sec_context
;
661 } else if (AsiIsNucleus(asi
)) {
666 context
= pri_context
;
670 if (!implicit
&& asi
!= ASI_P
&& asi
!= ASI_S
) {
671 if (AsiIsLittle(asi
))
672 panic("Little Endian ASIs not supported\n");
674 //XXX It's unclear from looking at the documentation how a no fault
675 //load differs from a regular one, other than what happens concerning
676 //nfo and e bits in the TTE
677 // if (AsiIsNoFault(asi))
678 // panic("No Fault ASIs not supported\n");
680 if (AsiIsPartialStore(asi
))
681 panic("Partial Store ASIs not supported\n");
684 panic("Cmt ASI registers not implmented\n");
686 if (AsiIsInterrupt(asi
))
687 goto handleIntRegAccess
;
689 goto handleMmuRegAccess
;
690 if (AsiIsScratchPad(asi
))
691 goto handleScratchRegAccess
;
693 goto handleQueueRegAccess
;
694 if (AsiIsSparcError(asi
))
695 goto handleSparcErrorRegAccess
;
697 if (!AsiIsReal(asi
) && !AsiIsNucleus(asi
) && !AsiIsAsIfUser(asi
) &&
698 !AsiIsTwin(asi
) && !AsiIsBlock(asi
) && !AsiIsNoFault(asi
))
699 panic("Accessing ASI %#X. Should we?\n", asi
);
702 // If the asi is unaligned trap
704 writeSfsr(vaddr
, false, ct
, false, OtherFault
, asi
);
705 return new MemAddressNotAligned
;
709 vaddr
= vaddr
& VAddrAMask
;
711 if (!validVirtualAddress(vaddr
, addr_mask
)) {
712 writeSfsr(vaddr
, false, ct
, true, VaOutOfRange
, asi
);
713 return new DataAccessException
;
716 if ((!lsu_dm
&& !hpriv
&& !red
) || AsiIsReal(asi
)) {
721 if (hpriv
&& (implicit
|| (!AsiIsAsIfUser(asi
) && !AsiIsReal(asi
)))) {
722 req
->setPaddr(vaddr
& PAddrImplMask
);
726 e
= lookup(vaddr
, part_id
, real
, context
);
728 if (e
== NULL
|| !e
->valid
) {
729 writeTagAccess(vaddr
, context
);
730 DPRINTF(TLB
, "TLB: DTB Failed to find matching TLB entry\n");
732 return new DataRealTranslationMiss
;
735 return new FastDataAccessMMUMiss
;
737 return new FastDataAccessMMUMiss(req
->getVaddr());
742 if (!priv
&& e
->pte
.priv()) {
743 writeTagAccess(vaddr
, context
);
744 writeSfsr(vaddr
, write
, ct
, e
->pte
.sideffect(), PrivViolation
, asi
);
745 return new DataAccessException
;
748 if (write
&& !e
->pte
.writable()) {
749 writeTagAccess(vaddr
, context
);
750 writeSfsr(vaddr
, write
, ct
, e
->pte
.sideffect(), OtherFault
, asi
);
751 return new FastDataAccessProtection
;
754 if (e
->pte
.nofault() && !AsiIsNoFault(asi
)) {
755 writeTagAccess(vaddr
, context
);
756 writeSfsr(vaddr
, write
, ct
, e
->pte
.sideffect(), LoadFromNfo
, asi
);
757 return new DataAccessException
;
760 if (e
->pte
.sideffect() && AsiIsNoFault(asi
)) {
761 writeTagAccess(vaddr
, context
);
762 writeSfsr(vaddr
, write
, ct
, e
->pte
.sideffect(), SideEffect
, asi
);
763 return new DataAccessException
;
766 if (e
->pte
.sideffect() || (e
->pte
.paddr() >> 39) & 1)
767 req
->setFlags(Request::UNCACHEABLE
);
769 // cache translation date for next translation
770 cacheState
= tlbdata
;
772 cacheEntry
[1] = NULL
;
773 cacheEntry
[0] = NULL
;
776 if (cacheEntry
[0] != e
&& cacheEntry
[1] != e
) {
777 cacheEntry
[1] = cacheEntry
[0];
779 cacheAsi
[1] = cacheAsi
[0];
782 cacheAsi
[0] = (ASI
)0;
785 req
->setPaddr(e
->pte
.translate(vaddr
));
786 DPRINTF(TLB
, "TLB: %#X -> %#X\n", vaddr
, req
->getPaddr());
789 /** Normal flow ends here. */
792 writeSfsr(vaddr
, write
, Primary
, true, IllegalAsi
, asi
);
794 return new DataAccessException
;
796 return new PrivilegedAction
;
799 if ((asi
== ASI_SWVR_UDB_INTR_W
&& !write
) ||
800 (asi
== ASI_SWVR_UDB_INTR_R
&& write
)) {
801 writeSfsr(vaddr
, write
, Primary
, true, IllegalAsi
, asi
);
802 return new DataAccessException
;
808 handleScratchRegAccess
:
809 if (vaddr
> 0x38 || (vaddr
>= 0x20 && vaddr
< 0x30 && !hpriv
)) {
810 writeSfsr(vaddr
, write
, Primary
, true, IllegalAsi
, asi
);
811 return new DataAccessException
;
815 handleQueueRegAccess
:
816 if (!priv
&& !hpriv
) {
817 writeSfsr(vaddr
, write
, Primary
, true, IllegalAsi
, asi
);
818 return new PrivilegedAction
;
820 if ((!hpriv
&& vaddr
& 0xF) || vaddr
> 0x3f8 || vaddr
< 0x3c0) {
821 writeSfsr(vaddr
, write
, Primary
, true, IllegalAsi
, asi
);
822 return new DataAccessException
;
826 handleSparcErrorRegAccess
:
828 writeSfsr(vaddr
, write
, Primary
, true, IllegalAsi
, asi
);
830 return new DataAccessException
;
832 return new PrivilegedAction
;
839 DPRINTF(TLB
, "TLB: DTB Translating MM IPR access\n");
840 req
->setFlags(Request::MMAPED_IPR
);
841 req
->setPaddr(req
->getVaddr());
846 TLB::translateAtomic(RequestPtr req
, ThreadContext
*tc
, Mode mode
)
849 return translateInst(req
, tc
);
851 return translateData(req
, tc
, mode
== Write
);
855 TLB::translateTiming(RequestPtr req
, ThreadContext
*tc
,
856 Translation
*translation
, Mode mode
)
859 translation
->finish(translateAtomic(req
, tc
, mode
), req
, tc
, mode
);
865 TLB::doMmuRegRead(ThreadContext
*tc
, Packet
*pkt
)
867 Addr va
= pkt
->getAddr();
868 ASI asi
= (ASI
)pkt
->req
->getAsi();
871 DPRINTF(IPR
, "Memory Mapped IPR Read: asi=%#X a=%#x\n",
872 (uint32_t)pkt
->req
->getAsi(), pkt
->getAddr());
874 TLB
*itb
= tc
->getITBPtr();
877 case ASI_LSU_CONTROL_REG
:
879 pkt
->set(tc
->readMiscReg(MISCREG_MMU_LSU_CTRL
));
884 pkt
->set(tc
->readMiscReg(MISCREG_MMU_P_CONTEXT
));
887 pkt
->set(tc
->readMiscReg(MISCREG_MMU_S_CONTEXT
));
894 pkt
->set(tc
->readMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD
+
897 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0
:
899 pkt
->set(c0_tsb_ps0
);
901 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1
:
903 pkt
->set(c0_tsb_ps1
);
905 case ASI_DMMU_CTXT_ZERO_CONFIG
:
909 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0
:
911 pkt
->set(itb
->c0_tsb_ps0
);
913 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1
:
915 pkt
->set(itb
->c0_tsb_ps1
);
917 case ASI_IMMU_CTXT_ZERO_CONFIG
:
919 pkt
->set(itb
->c0_config
);
921 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0
:
923 pkt
->set(cx_tsb_ps0
);
925 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1
:
927 pkt
->set(cx_tsb_ps1
);
929 case ASI_DMMU_CTXT_NONZERO_CONFIG
:
933 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0
:
935 pkt
->set(itb
->cx_tsb_ps0
);
937 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1
:
939 pkt
->set(itb
->cx_tsb_ps1
);
941 case ASI_IMMU_CTXT_NONZERO_CONFIG
:
943 pkt
->set(itb
->cx_config
);
945 case ASI_SPARC_ERROR_STATUS_REG
:
946 pkt
->set((uint64_t)0);
948 case ASI_HYP_SCRATCHPAD
:
950 pkt
->set(tc
->readMiscReg(MISCREG_SCRATCHPAD_R0
+ (va
>> 3)));
955 temp
= itb
->tag_access
;
956 pkt
->set(bits(temp
,63,22) | bits(temp
,12,0) << 48);
962 pkt
->set(itb
->tag_access
);
972 pkt
->set(bits(temp
,63,22) | bits(temp
,12,0) << 48);
981 pkt
->set(tag_access
);
984 pkt
->set(tc
->readMiscReg(MISCREG_MMU_PART_ID
));
990 case ASI_DMMU_TSB_PS0_PTR_REG
:
991 pkt
->set(MakeTsbPtr(Ps0
,
998 case ASI_DMMU_TSB_PS1_PTR_REG
:
999 pkt
->set(MakeTsbPtr(Ps1
,
1006 case ASI_IMMU_TSB_PS0_PTR_REG
:
1007 pkt
->set(MakeTsbPtr(Ps0
,
1014 case ASI_IMMU_TSB_PS1_PTR_REG
:
1015 pkt
->set(MakeTsbPtr(Ps1
,
1022 case ASI_SWVR_INTR_RECEIVE
:
1024 SparcISA::Interrupts
* interrupts
=
1025 dynamic_cast<SparcISA::Interrupts
*>(
1026 tc
->getCpuPtr()->getInterruptController());
1027 pkt
->set(interrupts
->get_vec(IT_INT_VEC
));
1030 case ASI_SWVR_UDB_INTR_R
:
1032 SparcISA::Interrupts
* interrupts
=
1033 dynamic_cast<SparcISA::Interrupts
*>(
1034 tc
->getCpuPtr()->getInterruptController());
1035 temp
= findMsbSet(interrupts
->get_vec(IT_INT_VEC
));
1036 tc
->getCpuPtr()->clearInterrupt(IT_INT_VEC
, temp
);
1042 panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n",
1045 pkt
->makeAtomicResponse();
1046 return tc
->getCpuPtr()->ticks(1);
1050 TLB::doMmuRegWrite(ThreadContext
*tc
, Packet
*pkt
)
1052 uint64_t data
= gtoh(pkt
->get
<uint64_t>());
1053 Addr va
= pkt
->getAddr();
1054 ASI asi
= (ASI
)pkt
->req
->getAsi();
1060 int entry_insert
= -1;
1067 DPRINTF(IPR
, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n",
1068 (uint32_t)asi
, va
, data
);
1070 TLB
*itb
= tc
->getITBPtr();
1073 case ASI_LSU_CONTROL_REG
:
1075 tc
->setMiscReg(MISCREG_MMU_LSU_CTRL
, data
);
1080 tc
->setMiscReg(MISCREG_MMU_P_CONTEXT
, data
);
1083 tc
->setMiscReg(MISCREG_MMU_S_CONTEXT
, data
);
1086 goto doMmuWriteError
;
1090 assert(mbits(data
,13,6) == data
);
1091 tc
->setMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD
+
1092 (va
>> 4) - 0x3c, data
);
1094 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0
:
1098 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1
:
1102 case ASI_DMMU_CTXT_ZERO_CONFIG
:
1106 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0
:
1108 itb
->c0_tsb_ps0
= data
;
1110 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1
:
1112 itb
->c0_tsb_ps1
= data
;
1114 case ASI_IMMU_CTXT_ZERO_CONFIG
:
1116 itb
->c0_config
= data
;
1118 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0
:
1122 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1
:
1126 case ASI_DMMU_CTXT_NONZERO_CONFIG
:
1130 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0
:
1132 itb
->cx_tsb_ps0
= data
;
1134 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1
:
1136 itb
->cx_tsb_ps1
= data
;
1138 case ASI_IMMU_CTXT_NONZERO_CONFIG
:
1140 itb
->cx_config
= data
;
1142 case ASI_SPARC_ERROR_EN_REG
:
1143 case ASI_SPARC_ERROR_STATUS_REG
:
1144 inform("Ignoring write to SPARC ERROR regsiter\n");
1146 case ASI_HYP_SCRATCHPAD
:
1147 case ASI_SCRATCHPAD
:
1148 tc
->setMiscReg(MISCREG_SCRATCHPAD_R0
+ (va
>> 3), data
);
1156 sext
<59>(bits(data
, 59,0));
1157 itb
->tag_access
= data
;
1160 goto doMmuWriteError
;
1163 case ASI_ITLB_DATA_ACCESS_REG
:
1164 entry_insert
= bits(va
, 8,3);
1165 case ASI_ITLB_DATA_IN_REG
:
1166 assert(entry_insert
!= -1 || mbits(va
,10,9) == va
);
1167 ta_insert
= itb
->tag_access
;
1168 va_insert
= mbits(ta_insert
, 63,13);
1169 ct_insert
= mbits(ta_insert
, 12,0);
1170 part_insert
= tc
->readMiscReg(MISCREG_MMU_PART_ID
);
1171 real_insert
= bits(va
, 9,9);
1172 pte
.populate(data
, bits(va
,10,10) ? PageTableEntry::sun4v
:
1173 PageTableEntry::sun4u
);
1174 tc
->getITBPtr()->insert(va_insert
, part_insert
, ct_insert
, real_insert
,
1177 case ASI_DTLB_DATA_ACCESS_REG
:
1178 entry_insert
= bits(va
, 8,3);
1179 case ASI_DTLB_DATA_IN_REG
:
1180 assert(entry_insert
!= -1 || mbits(va
,10,9) == va
);
1181 ta_insert
= tag_access
;
1182 va_insert
= mbits(ta_insert
, 63,13);
1183 ct_insert
= mbits(ta_insert
, 12,0);
1184 part_insert
= tc
->readMiscReg(MISCREG_MMU_PART_ID
);
1185 real_insert
= bits(va
, 9,9);
1186 pte
.populate(data
, bits(va
,10,10) ? PageTableEntry::sun4v
:
1187 PageTableEntry::sun4u
);
1188 insert(va_insert
, part_insert
, ct_insert
, real_insert
, pte
,
1191 case ASI_IMMU_DEMAP
:
1194 part_id
= tc
->readMiscReg(MISCREG_MMU_PART_ID
);
1195 switch (bits(va
,5,4)) {
1197 ctx_id
= tc
->readMiscReg(MISCREG_MMU_P_CONTEXT
);
1209 switch(bits(va
,7,6)) {
1210 case 0: // demap page
1212 tc
->getITBPtr()->demapPage(mbits(va
,63,13), part_id
,
1213 bits(va
,9,9), ctx_id
);
1215 case 1: //demap context
1217 tc
->getITBPtr()->demapContext(part_id
, ctx_id
);
1220 tc
->getITBPtr()->demapAll(part_id
);
1223 panic("Invalid type for IMMU demap\n");
1232 sext
<59>(bits(data
, 59,0));
1236 tc
->setMiscReg(MISCREG_MMU_PART_ID
, data
);
1239 goto doMmuWriteError
;
1242 case ASI_DMMU_DEMAP
:
1245 part_id
= tc
->readMiscReg(MISCREG_MMU_PART_ID
);
1246 switch (bits(va
,5,4)) {
1248 ctx_id
= tc
->readMiscReg(MISCREG_MMU_P_CONTEXT
);
1251 ctx_id
= tc
->readMiscReg(MISCREG_MMU_S_CONTEXT
);
1260 switch(bits(va
,7,6)) {
1261 case 0: // demap page
1263 demapPage(mbits(va
,63,13), part_id
, bits(va
,9,9), ctx_id
);
1265 case 1: //demap context
1267 demapContext(part_id
, ctx_id
);
1273 panic("Invalid type for IMMU demap\n");
1276 case ASI_SWVR_INTR_RECEIVE
:
1279 // clear all the interrupts that aren't set in the write
1280 SparcISA::Interrupts
* interrupts
=
1281 dynamic_cast<SparcISA::Interrupts
*>(
1282 tc
->getCpuPtr()->getInterruptController());
1283 while (interrupts
->get_vec(IT_INT_VEC
) & data
) {
1284 msb
= findMsbSet(interrupts
->get_vec(IT_INT_VEC
) & data
);
1285 tc
->getCpuPtr()->clearInterrupt(IT_INT_VEC
, msb
);
1289 case ASI_SWVR_UDB_INTR_W
:
1290 tc
->getSystemPtr()->threadContexts
[bits(data
,12,8)]->getCpuPtr()->
1291 postInterrupt(bits(data
, 5, 0), 0);
1295 panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n",
1296 (uint32_t)pkt
->req
->getAsi(), pkt
->getAddr(), data
);
1298 pkt
->makeAtomicResponse();
1299 return tc
->getCpuPtr()->ticks(1);
1305 TLB::GetTsbPtr(ThreadContext
*tc
, Addr addr
, int ctx
, Addr
*ptrs
)
1307 uint64_t tag_access
= mbits(addr
,63,13) | mbits(ctx
,12,0);
1308 TLB
* itb
= tc
->getITBPtr();
1309 ptrs
[0] = MakeTsbPtr(Ps0
, tag_access
,
1314 ptrs
[1] = MakeTsbPtr(Ps1
, tag_access
,
1319 ptrs
[2] = MakeTsbPtr(Ps0
, tag_access
,
1324 ptrs
[3] = MakeTsbPtr(Ps1
, tag_access
,
1332 TLB::MakeTsbPtr(TsbPageSize ps
, uint64_t tag_access
, uint64_t c0_tsb
,
1333 uint64_t c0_config
, uint64_t cX_tsb
, uint64_t cX_config
)
1338 if (bits(tag_access
, 12,0) == 0) {
1346 uint64_t ptr
= mbits(tsb
,63,13);
1347 bool split
= bits(tsb
,12,12);
1348 int tsb_size
= bits(tsb
,3,0);
1349 int page_size
= (ps
== Ps0
) ? bits(config
, 2,0) : bits(config
,10,8);
1351 if (ps
== Ps1
&& split
)
1352 ptr
|= ULL(1) << (13 + tsb_size
);
1353 ptr
|= (tag_access
>> (9 + page_size
* 3)) & mask(12+tsb_size
, 4);
1359 TLB::serialize(std::ostream
&os
)
1361 SERIALIZE_SCALAR(size
);
1362 SERIALIZE_SCALAR(usedEntries
);
1363 SERIALIZE_SCALAR(lastReplaced
);
1365 // convert the pointer based free list into an index based one
1366 int *free_list
= (int*)malloc(sizeof(int) * size
);
1368 std::list
<TlbEntry
*>::iterator i
;
1369 i
= freeList
.begin();
1370 while (i
!= freeList
.end()) {
1371 free_list
[cntr
++] = ((size_t)*i
- (size_t)tlb
)/ sizeof(TlbEntry
);
1374 SERIALIZE_SCALAR(cntr
);
1375 SERIALIZE_ARRAY(free_list
, cntr
);
1377 SERIALIZE_SCALAR(c0_tsb_ps0
);
1378 SERIALIZE_SCALAR(c0_tsb_ps1
);
1379 SERIALIZE_SCALAR(c0_config
);
1380 SERIALIZE_SCALAR(cx_tsb_ps0
);
1381 SERIALIZE_SCALAR(cx_tsb_ps1
);
1382 SERIALIZE_SCALAR(cx_config
);
1383 SERIALIZE_SCALAR(sfsr
);
1384 SERIALIZE_SCALAR(tag_access
);
1386 for (int x
= 0; x
< size
; x
++) {
1387 nameOut(os
, csprintf("%s.PTE%d", name(), x
));
1388 tlb
[x
].serialize(os
);
1390 SERIALIZE_SCALAR(sfar
);
1394 TLB::unserialize(Checkpoint
*cp
, const std::string
§ion
)
1398 paramIn(cp
, section
, "size", oldSize
);
1399 if (oldSize
!= size
)
1400 panic("Don't support unserializing different sized TLBs\n");
1401 UNSERIALIZE_SCALAR(usedEntries
);
1402 UNSERIALIZE_SCALAR(lastReplaced
);
1405 UNSERIALIZE_SCALAR(cntr
);
1407 int *free_list
= (int*)malloc(sizeof(int) * cntr
);
1409 UNSERIALIZE_ARRAY(free_list
, cntr
);
1410 for (int x
= 0; x
< cntr
; x
++)
1411 freeList
.push_back(&tlb
[free_list
[x
]]);
1413 UNSERIALIZE_SCALAR(c0_tsb_ps0
);
1414 UNSERIALIZE_SCALAR(c0_tsb_ps1
);
1415 UNSERIALIZE_SCALAR(c0_config
);
1416 UNSERIALIZE_SCALAR(cx_tsb_ps0
);
1417 UNSERIALIZE_SCALAR(cx_tsb_ps1
);
1418 UNSERIALIZE_SCALAR(cx_config
);
1419 UNSERIALIZE_SCALAR(sfsr
);
1420 UNSERIALIZE_SCALAR(tag_access
);
1422 lookupTable
.clear();
1423 for (int x
= 0; x
< size
; x
++) {
1424 tlb
[x
].unserialize(cp
, csprintf("%s.PTE%d", section
, x
));
1426 lookupTable
.insert(tlb
[x
].range
, &tlb
[x
]);
1429 UNSERIALIZE_SCALAR(sfar
);
1432 /* end namespace SparcISA */ }
1435 SparcTLBParams::create()
1437 return new SparcISA::TLB(this);