2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
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6 * modification, are permitted provided that the following conditions are
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13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 #include "arch/sparc/tlb.hh"
35 #include "arch/sparc/asi.hh"
36 #include "arch/sparc/faults.hh"
37 #include "arch/sparc/interrupts.hh"
38 #include "arch/sparc/registers.hh"
39 #include "base/bitfield.hh"
40 #include "base/compiler.hh"
41 #include "base/trace.hh"
42 #include "cpu/base.hh"
43 #include "cpu/thread_context.hh"
44 #include "debug/IPR.hh"
45 #include "debug/TLB.hh"
46 #include "mem/packet_access.hh"
47 #include "mem/request.hh"
48 #include "sim/full_system.hh"
49 #include "sim/system.hh"
51 /* @todo remove some of the magic constants. -- ali
55 TLB::TLB(const Params
*p
)
56 : BaseTLB(p
), size(p
->size
), usedEntries(0), lastReplaced(0),
57 cacheState(0), cacheValid(false)
59 // To make this work you'll have to change the hypervisor and OS
61 fatal("SPARC T1 TLB registers don't support more than 64 TLB entries");
63 tlb
= new TlbEntry
[size
];
64 std::memset(tlb
, 0, sizeof(TlbEntry
) * size
);
66 for (int x
= 0; x
< size
; x
++)
67 freeList
.push_back(&tlb
[x
]);
86 for (i
= lookupTable
.begin(); i
!= lookupTable
.end(); i
++) {
87 TlbEntry
*t
= i
->second
;
88 if (!t
->pte
.locked()) {
97 TLB::insert(Addr va
, int partition_id
, int context_id
, bool real
,
98 const PageTableEntry
& PTE
, int entry
)
101 TlbEntry
*new_entry
= NULL
;
106 va
&= ~(PTE
.size()-1);
108 tr.size = PTE.size() - 1;
109 tr.contextId = context_id;
110 tr.partitionId = partition_id;
115 "TLB: Inserting Entry; va=%#x pa=%#x pid=%d cid=%d r=%d entryid=%d\n",
116 va
, PTE
.paddr(), partition_id
, context_id
, (int)real
, entry
);
118 // Demap any entry that conflicts
119 for (x
= 0; x
< size
; x
++) {
120 if (tlb
[x
].range
.real
== real
&&
121 tlb
[x
].range
.partitionId
== partition_id
&&
122 tlb
[x
].range
.va
< va
+ PTE
.size() - 1 &&
123 tlb
[x
].range
.va
+ tlb
[x
].range
.size
>= va
&&
124 (real
|| tlb
[x
].range
.contextId
== context_id
))
127 freeList
.push_front(&tlb
[x
]);
128 DPRINTF(TLB
, "TLB: Conflicting entry %#X , deleting it\n", x
);
130 tlb
[x
].valid
= false;
135 lookupTable
.erase(tlb
[x
].range
);
141 assert(entry
< size
&& entry
>= 0);
142 new_entry
= &tlb
[entry
];
144 if (!freeList
.empty()) {
145 new_entry
= freeList
.front();
152 if (x
== lastReplaced
)
153 goto insertAllLocked
;
154 } while (tlb
[x
].pte
.locked());
161 // Update the last ently if their all locked
163 new_entry
= &tlb
[size
-1];
166 freeList
.remove(new_entry
);
167 if (new_entry
->valid
&& new_entry
->used
)
169 if (new_entry
->valid
)
170 lookupTable
.erase(new_entry
->range
);
174 new_entry
->range
.va
= va
;
175 new_entry
->range
.size
= PTE
.size() - 1;
176 new_entry
->range
.partitionId
= partition_id
;
177 new_entry
->range
.contextId
= context_id
;
178 new_entry
->range
.real
= real
;
179 new_entry
->pte
= PTE
;
180 new_entry
->used
= true;;
181 new_entry
->valid
= true;
184 i
= lookupTable
.insert(new_entry
->range
, new_entry
);
185 assert(i
!= lookupTable
.end());
187 // If all entries have their used bit set, clear it on them all,
188 // but the one we just inserted
189 if (usedEntries
== size
) {
191 new_entry
->used
= true;
198 TLB::lookup(Addr va
, int partition_id
, bool real
, int context_id
,
205 DPRINTF(TLB
, "TLB: Looking up entry va=%#x pid=%d cid=%d r=%d\n",
206 va
, partition_id
, context_id
, real
);
207 // Assemble full address structure
210 tr
.contextId
= context_id
;
211 tr
.partitionId
= partition_id
;
214 // Try to find the entry
215 i
= lookupTable
.find(tr
);
216 if (i
== lookupTable
.end()) {
217 DPRINTF(TLB
, "TLB: No valid entry found\n");
221 // Mark the entries used bit and clear other used bits in needed
223 DPRINTF(TLB
, "TLB: Valid entry found pa: %#x size: %#x\n", t
->pte
.paddr(),
226 // Update the used bits only if this is a real access (not a fake
227 // one from virttophys()
228 if (!t
->used
&& update_used
) {
231 if (usedEntries
== size
) {
245 for (int x
= 0; x
< size
; x
++) {
247 DPRINTFN("%4d: %#2x:%#2x %c %#4x %#8x %#8x %#16x\n",
248 x
, tlb
[x
].range
.partitionId
, tlb
[x
].range
.contextId
,
249 tlb
[x
].range
.real
? 'R' : ' ', tlb
[x
].range
.size
,
250 tlb
[x
].range
.va
, tlb
[x
].pte
.paddr(), tlb
[x
].pte());
256 TLB::demapPage(Addr va
, int partition_id
, bool real
, int context_id
)
261 DPRINTF(IPR
, "TLB: Demapping Page va=%#x pid=%#d cid=%d r=%d\n",
262 va
, partition_id
, context_id
, real
);
266 // Assemble full address structure
269 tr
.contextId
= context_id
;
270 tr
.partitionId
= partition_id
;
273 // Demap any entry that conflicts
274 i
= lookupTable
.find(tr
);
275 if (i
!= lookupTable
.end()) {
276 DPRINTF(IPR
, "TLB: Demapped page\n");
277 i
->second
->valid
= false;
278 if (i
->second
->used
) {
279 i
->second
->used
= false;
282 freeList
.push_front(i
->second
);
283 lookupTable
.erase(i
);
288 TLB::demapContext(int partition_id
, int context_id
)
290 DPRINTF(IPR
, "TLB: Demapping Context pid=%#d cid=%d\n",
291 partition_id
, context_id
);
293 for (int x
= 0; x
< size
; x
++) {
294 if (tlb
[x
].range
.contextId
== context_id
&&
295 tlb
[x
].range
.partitionId
== partition_id
) {
297 freeList
.push_front(&tlb
[x
]);
299 tlb
[x
].valid
= false;
304 lookupTable
.erase(tlb
[x
].range
);
310 TLB::demapAll(int partition_id
)
312 DPRINTF(TLB
, "TLB: Demapping All pid=%#d\n", partition_id
);
314 for (int x
= 0; x
< size
; x
++) {
315 if (tlb
[x
].valid
&& !tlb
[x
].pte
.locked() &&
316 tlb
[x
].range
.partitionId
== partition_id
) {
317 freeList
.push_front(&tlb
[x
]);
318 tlb
[x
].valid
= false;
323 lookupTable
.erase(tlb
[x
].range
);
334 for (int x
= 0; x
< size
; x
++) {
336 freeList
.push_back(&tlb
[x
]);
337 tlb
[x
].valid
= false;
344 TLB::TteRead(int entry
)
347 panic("entry: %d\n", entry
);
349 assert(entry
< size
);
350 if (tlb
[entry
].valid
)
351 return tlb
[entry
].pte();
353 return (uint64_t)-1ll;
357 TLB::TagRead(int entry
)
359 assert(entry
< size
);
361 if (!tlb
[entry
].valid
)
362 return (uint64_t)-1ll;
364 tag
= tlb
[entry
].range
.contextId
;
365 tag
|= tlb
[entry
].range
.va
;
366 tag
|= (uint64_t)tlb
[entry
].range
.partitionId
<< 61;
367 tag
|= tlb
[entry
].range
.real
? ULL(1) << 60 : 0;
368 tag
|= (uint64_t)~tlb
[entry
].pte
._size() << 56;
373 TLB::validVirtualAddress(Addr va
, bool am
)
377 if (va
>= StartVAddrHole
&& va
<= EndVAddrHole
)
383 TLB::writeSfsr(bool write
, ContextType ct
, bool se
, FaultTypes ft
, int asi
)
400 TLB::writeTagAccess(Addr va
, int context
)
402 DPRINTF(TLB
, "TLB: Writing Tag Access: va: %#X ctx: %#X value: %#X\n",
403 va
, context
, mbits(va
, 63,13) | mbits(context
,12,0));
405 tag_access
= mbits(va
, 63,13) | mbits(context
,12,0);
409 TLB::writeSfsr(Addr a
, bool write
, ContextType ct
,
410 bool se
, FaultTypes ft
, int asi
)
412 DPRINTF(TLB
, "TLB: Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n",
413 a
, (int)write
, ct
, ft
, asi
);
414 TLB::writeSfsr(write
, ct
, se
, ft
, asi
);
419 TLB::translateInst(const RequestPtr
&req
, ThreadContext
*tc
)
421 uint64_t tlbdata
= tc
->readMiscRegNoEffect(MISCREG_TLB_DATA
);
423 Addr vaddr
= req
->getVaddr();
426 assert(req
->getArchFlags() == ASI_IMPLICIT
);
428 DPRINTF(TLB
, "TLB: ITB Request to translate va=%#x size=%d\n",
429 vaddr
, req
->getSize());
431 // Be fast if we can!
432 if (cacheValid
&& cacheState
== tlbdata
) {
434 if (cacheEntry
[0]->range
.va
< vaddr
+ sizeof(MachInst
) &&
435 cacheEntry
[0]->range
.va
+ cacheEntry
[0]->range
.size
>= vaddr
) {
436 req
->setPaddr(cacheEntry
[0]->pte
.translate(vaddr
));
440 req
->setPaddr(vaddr
& PAddrImplMask
);
445 bool hpriv
= bits(tlbdata
,0,0);
446 bool red
= bits(tlbdata
,1,1);
447 bool priv
= bits(tlbdata
,2,2);
448 bool addr_mask
= bits(tlbdata
,3,3);
449 bool lsu_im
= bits(tlbdata
,4,4);
451 int part_id
= bits(tlbdata
,15,8);
452 int tl
= bits(tlbdata
,18,16);
453 int pri_context
= bits(tlbdata
,47,32);
459 DPRINTF(TLB
, "TLB: priv:%d hpriv:%d red:%d lsuim:%d part_id: %#X\n",
460 priv
, hpriv
, red
, lsu_im
, part_id
);
469 context
= pri_context
;
472 if ( hpriv
|| red
) {
474 cacheState
= tlbdata
;
475 cacheEntry
[0] = NULL
;
476 req
->setPaddr(vaddr
& PAddrImplMask
);
480 // If the access is unaligned trap
482 writeSfsr(false, ct
, false, OtherFault
, asi
);
483 return std::make_shared
<MemAddressNotAligned
>();
487 vaddr
= vaddr
& VAddrAMask
;
489 if (!validVirtualAddress(vaddr
, addr_mask
)) {
490 writeSfsr(false, ct
, false, VaOutOfRange
, asi
);
491 return std::make_shared
<InstructionAccessException
>();
495 e
= lookup(vaddr
, part_id
, true);
499 e
= lookup(vaddr
, part_id
, false, context
);
502 if (e
== NULL
|| !e
->valid
) {
503 writeTagAccess(vaddr
, context
);
505 return std::make_shared
<InstructionRealTranslationMiss
>();
508 return std::make_shared
<FastInstructionAccessMMUMiss
>();
510 return std::make_shared
<FastInstructionAccessMMUMiss
>(
515 // were not priviledged accesing priv page
516 if (!priv
&& e
->pte
.priv()) {
517 writeTagAccess(vaddr
, context
);
518 writeSfsr(false, ct
, false, PrivViolation
, asi
);
519 return std::make_shared
<InstructionAccessException
>();
522 // cache translation date for next translation
524 cacheState
= tlbdata
;
527 req
->setPaddr(e
->pte
.translate(vaddr
));
528 DPRINTF(TLB
, "TLB: %#X -> %#X\n", vaddr
, req
->getPaddr());
533 TLB::translateData(const RequestPtr
&req
, ThreadContext
*tc
, bool write
)
536 * @todo this could really use some profiling and fixing to make
539 uint64_t tlbdata
= tc
->readMiscRegNoEffect(MISCREG_TLB_DATA
);
540 Addr vaddr
= req
->getVaddr();
541 Addr size
= req
->getSize();
543 asi
= (ASI
)req
->getArchFlags();
544 bool implicit
= false;
545 bool hpriv
= bits(tlbdata
,0,0);
546 bool unaligned
= vaddr
& (size
- 1);
548 DPRINTF(TLB
, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n",
551 if (lookupTable
.size() != 64 - freeList
.size())
552 panic("Lookup table size: %d tlb size: %d\n", lookupTable
.size(),
554 if (asi
== ASI_IMPLICIT
)
557 // Only use the fast path here if there doesn't need to be an unaligned
560 if (hpriv
&& implicit
) {
561 req
->setPaddr(vaddr
& PAddrImplMask
);
565 // Be fast if we can!
566 if (cacheValid
&& cacheState
== tlbdata
) {
571 TlbEntry
*ce
= cacheEntry
[0];
572 Addr ce_va
= ce
->range
.va
;
573 if (cacheAsi
[0] == asi
&&
574 ce_va
< vaddr
+ size
&& ce_va
+ ce
->range
.size
> vaddr
&&
575 (!write
|| ce
->pte
.writable())) {
576 req
->setPaddr(ce
->pte
.translate(vaddr
));
577 if (ce
->pte
.sideffect() || (ce
->pte
.paddr() >> 39) & 1) {
579 Request::UNCACHEABLE
| Request::STRICT_ORDER
);
581 DPRINTF(TLB
, "TLB: %#X -> %#X\n", vaddr
, req
->getPaddr());
584 } // if cache entry valid
586 TlbEntry
*ce
= cacheEntry
[1];
587 Addr ce_va
= ce
->range
.va
;
588 if (cacheAsi
[1] == asi
&&
589 ce_va
< vaddr
+ size
&& ce_va
+ ce
->range
.size
> vaddr
&&
590 (!write
|| ce
->pte
.writable())) {
591 req
->setPaddr(ce
->pte
.translate(vaddr
));
592 if (ce
->pte
.sideffect() || (ce
->pte
.paddr() >> 39) & 1) {
594 Request::UNCACHEABLE
| Request::STRICT_ORDER
);
596 DPRINTF(TLB
, "TLB: %#X -> %#X\n", vaddr
, req
->getPaddr());
599 } // if cache entry valid
603 bool red
= bits(tlbdata
,1,1);
604 bool priv
= bits(tlbdata
,2,2);
605 bool addr_mask
= bits(tlbdata
,3,3);
606 bool lsu_dm
= bits(tlbdata
,5,5);
608 int part_id
= bits(tlbdata
,15,8);
609 int tl
= bits(tlbdata
,18,16);
610 int pri_context
= bits(tlbdata
,47,32);
611 int sec_context
= bits(tlbdata
,63,48);
614 ContextType ct
= Primary
;
619 DPRINTF(TLB
, "TLB: priv:%d hpriv:%d red:%d lsudm:%d part_id: %#X\n",
620 priv
, hpriv
, red
, lsu_dm
, part_id
);
630 context
= pri_context
;
633 // We need to check for priv level/asi priv
634 if (!priv
&& !hpriv
&& !asiIsUnPriv(asi
)) {
635 // It appears that context should be Nucleus in these cases?
636 writeSfsr(vaddr
, write
, Nucleus
, false, IllegalAsi
, asi
);
637 return std::make_shared
<PrivilegedAction
>();
640 if (!hpriv
&& asiIsHPriv(asi
)) {
641 writeSfsr(vaddr
, write
, Nucleus
, false, IllegalAsi
, asi
);
642 return std::make_shared
<DataAccessException
>();
645 if (asiIsPrimary(asi
)) {
646 context
= pri_context
;
648 } else if (asiIsSecondary(asi
)) {
649 context
= sec_context
;
651 } else if (asiIsNucleus(asi
)) {
656 context
= pri_context
;
660 if (!implicit
&& asi
!= ASI_P
&& asi
!= ASI_S
) {
661 if (asiIsLittle(asi
))
662 panic("Little Endian ASIs not supported\n");
664 //XXX It's unclear from looking at the documentation how a no fault
665 // load differs from a regular one, other than what happens concerning
666 // nfo and e bits in the TTE
667 // if (asiIsNoFault(asi))
668 // panic("No Fault ASIs not supported\n");
670 if (asiIsPartialStore(asi
))
671 panic("Partial Store ASIs not supported\n");
674 panic("Cmt ASI registers not implmented\n");
676 if (asiIsInterrupt(asi
))
677 goto handleIntRegAccess
;
679 goto handleMmuRegAccess
;
680 if (asiIsScratchPad(asi
))
681 goto handleScratchRegAccess
;
683 goto handleQueueRegAccess
;
684 if (asiIsSparcError(asi
))
685 goto handleSparcErrorRegAccess
;
687 if (!asiIsReal(asi
) && !asiIsNucleus(asi
) && !asiIsAsIfUser(asi
) &&
688 !asiIsTwin(asi
) && !asiIsBlock(asi
) && !asiIsNoFault(asi
))
689 panic("Accessing ASI %#X. Should we?\n", asi
);
692 // If the asi is unaligned trap
694 writeSfsr(vaddr
, false, ct
, false, OtherFault
, asi
);
695 return std::make_shared
<MemAddressNotAligned
>();
699 vaddr
= vaddr
& VAddrAMask
;
701 if (!validVirtualAddress(vaddr
, addr_mask
)) {
702 writeSfsr(vaddr
, false, ct
, true, VaOutOfRange
, asi
);
703 return std::make_shared
<DataAccessException
>();
706 if ((!lsu_dm
&& !hpriv
&& !red
) || asiIsReal(asi
)) {
711 if (hpriv
&& (implicit
|| (!asiIsAsIfUser(asi
) && !asiIsReal(asi
)))) {
712 req
->setPaddr(vaddr
& PAddrImplMask
);
716 e
= lookup(vaddr
, part_id
, real
, context
);
718 if (e
== NULL
|| !e
->valid
) {
719 writeTagAccess(vaddr
, context
);
720 DPRINTF(TLB
, "TLB: DTB Failed to find matching TLB entry\n");
722 return std::make_shared
<DataRealTranslationMiss
>();
725 return std::make_shared
<FastDataAccessMMUMiss
>();
727 return std::make_shared
<FastDataAccessMMUMiss
>(
733 if (!priv
&& e
->pte
.priv()) {
734 writeTagAccess(vaddr
, context
);
735 writeSfsr(vaddr
, write
, ct
, e
->pte
.sideffect(), PrivViolation
, asi
);
736 return std::make_shared
<DataAccessException
>();
739 if (write
&& !e
->pte
.writable()) {
740 writeTagAccess(vaddr
, context
);
741 writeSfsr(vaddr
, write
, ct
, e
->pte
.sideffect(), OtherFault
, asi
);
742 return std::make_shared
<FastDataAccessProtection
>();
745 if (e
->pte
.nofault() && !asiIsNoFault(asi
)) {
746 writeTagAccess(vaddr
, context
);
747 writeSfsr(vaddr
, write
, ct
, e
->pte
.sideffect(), LoadFromNfo
, asi
);
748 return std::make_shared
<DataAccessException
>();
751 if (e
->pte
.sideffect() && asiIsNoFault(asi
)) {
752 writeTagAccess(vaddr
, context
);
753 writeSfsr(vaddr
, write
, ct
, e
->pte
.sideffect(), SideEffect
, asi
);
754 return std::make_shared
<DataAccessException
>();
757 if (e
->pte
.sideffect() || (e
->pte
.paddr() >> 39) & 1)
758 req
->setFlags(Request::UNCACHEABLE
| Request::STRICT_ORDER
);
760 // cache translation date for next translation
761 cacheState
= tlbdata
;
763 cacheEntry
[1] = NULL
;
764 cacheEntry
[0] = NULL
;
767 if (cacheEntry
[0] != e
&& cacheEntry
[1] != e
) {
768 cacheEntry
[1] = cacheEntry
[0];
770 cacheAsi
[1] = cacheAsi
[0];
773 cacheAsi
[0] = (ASI
)0;
776 req
->setPaddr(e
->pte
.translate(vaddr
));
777 DPRINTF(TLB
, "TLB: %#X -> %#X\n", vaddr
, req
->getPaddr());
780 /** Normal flow ends here. */
783 writeSfsr(vaddr
, write
, Primary
, true, IllegalAsi
, asi
);
785 return std::make_shared
<DataAccessException
>();
787 return std::make_shared
<PrivilegedAction
>();
790 if ((asi
== ASI_SWVR_UDB_INTR_W
&& !write
) ||
791 (asi
== ASI_SWVR_UDB_INTR_R
&& write
)) {
792 writeSfsr(vaddr
, write
, Primary
, true, IllegalAsi
, asi
);
793 return std::make_shared
<DataAccessException
>();
799 handleScratchRegAccess
:
800 if (vaddr
> 0x38 || (vaddr
>= 0x20 && vaddr
< 0x30 && !hpriv
)) {
801 writeSfsr(vaddr
, write
, Primary
, true, IllegalAsi
, asi
);
802 return std::make_shared
<DataAccessException
>();
806 handleQueueRegAccess
:
807 if (!priv
&& !hpriv
) {
808 writeSfsr(vaddr
, write
, Primary
, true, IllegalAsi
, asi
);
809 return std::make_shared
<PrivilegedAction
>();
811 if ((!hpriv
&& vaddr
& 0xF) || vaddr
> 0x3f8 || vaddr
< 0x3c0) {
812 writeSfsr(vaddr
, write
, Primary
, true, IllegalAsi
, asi
);
813 return std::make_shared
<DataAccessException
>();
817 handleSparcErrorRegAccess
:
819 writeSfsr(vaddr
, write
, Primary
, true, IllegalAsi
, asi
);
821 return std::make_shared
<DataAccessException
>();
823 return std::make_shared
<PrivilegedAction
>();
830 DPRINTF(TLB
, "TLB: DTB Translating MM IPR access\n");
831 req
->setFlags(Request::MMAPPED_IPR
);
832 req
->setPaddr(req
->getVaddr());
837 TLB::translateAtomic(const RequestPtr
&req
, ThreadContext
*tc
, Mode mode
)
840 return translateInst(req
, tc
);
842 return translateData(req
, tc
, mode
== Write
);
846 TLB::translateTiming(const RequestPtr
&req
, ThreadContext
*tc
,
847 Translation
*translation
, Mode mode
)
850 translation
->finish(translateAtomic(req
, tc
, mode
), req
, tc
, mode
);
854 TLB::finalizePhysical(const RequestPtr
&req
,
855 ThreadContext
*tc
, Mode mode
) const
861 TLB::doMmuRegRead(ThreadContext
*tc
, Packet
*pkt
)
863 Addr va
= pkt
->getAddr();
864 ASI asi
= (ASI
)pkt
->req
->getArchFlags();
867 DPRINTF(IPR
, "Memory Mapped IPR Read: asi=%#X a=%#x\n",
868 (uint32_t)pkt
->req
->getArchFlags(), pkt
->getAddr());
870 TLB
*itb
= dynamic_cast<TLB
*>(tc
->getITBPtr());
873 case ASI_LSU_CONTROL_REG
:
875 pkt
->setBE(tc
->readMiscReg(MISCREG_MMU_LSU_CTRL
));
880 pkt
->setBE(tc
->readMiscReg(MISCREG_MMU_P_CONTEXT
));
883 pkt
->setBE(tc
->readMiscReg(MISCREG_MMU_S_CONTEXT
));
890 pkt
->setBE(tc
->readMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD
+
893 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0
:
895 pkt
->setBE(c0_tsb_ps0
);
897 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1
:
899 pkt
->setBE(c0_tsb_ps1
);
901 case ASI_DMMU_CTXT_ZERO_CONFIG
:
903 pkt
->setBE(c0_config
);
905 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0
:
907 pkt
->setBE(itb
->c0_tsb_ps0
);
909 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1
:
911 pkt
->setBE(itb
->c0_tsb_ps1
);
913 case ASI_IMMU_CTXT_ZERO_CONFIG
:
915 pkt
->setBE(itb
->c0_config
);
917 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0
:
919 pkt
->setBE(cx_tsb_ps0
);
921 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1
:
923 pkt
->setBE(cx_tsb_ps1
);
925 case ASI_DMMU_CTXT_NONZERO_CONFIG
:
927 pkt
->setBE(cx_config
);
929 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0
:
931 pkt
->setBE(itb
->cx_tsb_ps0
);
933 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1
:
935 pkt
->setBE(itb
->cx_tsb_ps1
);
937 case ASI_IMMU_CTXT_NONZERO_CONFIG
:
939 pkt
->setBE(itb
->cx_config
);
941 case ASI_SPARC_ERROR_STATUS_REG
:
942 pkt
->setBE((uint64_t)0);
944 case ASI_HYP_SCRATCHPAD
:
946 pkt
->setBE(tc
->readMiscReg(MISCREG_SCRATCHPAD_R0
+ (va
>> 3)));
951 temp
= itb
->tag_access
;
952 pkt
->setBE(bits(temp
,63,22) | bits(temp
,12,0) << 48);
955 pkt
->setBE(itb
->sfsr
);
958 pkt
->setBE(itb
->tag_access
);
968 pkt
->setBE(bits(temp
,63,22) | bits(temp
,12,0) << 48);
977 pkt
->setBE(tag_access
);
980 pkt
->setBE(tc
->readMiscReg(MISCREG_MMU_PART_ID
));
986 case ASI_DMMU_TSB_PS0_PTR_REG
:
987 pkt
->setBE(MakeTsbPtr(Ps0
,
994 case ASI_DMMU_TSB_PS1_PTR_REG
:
995 pkt
->setBE(MakeTsbPtr(Ps1
,
1002 case ASI_IMMU_TSB_PS0_PTR_REG
:
1003 pkt
->setBE(MakeTsbPtr(Ps0
,
1010 case ASI_IMMU_TSB_PS1_PTR_REG
:
1011 pkt
->setBE(MakeTsbPtr(Ps1
,
1018 case ASI_SWVR_INTR_RECEIVE
:
1020 SparcISA::Interrupts
* interrupts
=
1021 dynamic_cast<SparcISA::Interrupts
*>(
1022 tc
->getCpuPtr()->getInterruptController(0));
1023 pkt
->setBE(interrupts
->get_vec(IT_INT_VEC
));
1026 case ASI_SWVR_UDB_INTR_R
:
1028 SparcISA::Interrupts
* interrupts
=
1029 dynamic_cast<SparcISA::Interrupts
*>(
1030 tc
->getCpuPtr()->getInterruptController(0));
1031 temp
= findMsbSet(interrupts
->get_vec(IT_INT_VEC
));
1032 tc
->getCpuPtr()->clearInterrupt(0, IT_INT_VEC
, temp
);
1038 panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n",
1041 pkt
->makeAtomicResponse();
1046 TLB::doMmuRegWrite(ThreadContext
*tc
, Packet
*pkt
)
1048 uint64_t data
= pkt
->getBE
<uint64_t>();
1049 Addr va
= pkt
->getAddr();
1050 ASI asi
= (ASI
)pkt
->req
->getArchFlags();
1056 int entry_insert
= -1;
1063 DPRINTF(IPR
, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n",
1064 (uint32_t)asi
, va
, data
);
1066 TLB
*itb
= dynamic_cast<TLB
*>(tc
->getITBPtr());
1069 case ASI_LSU_CONTROL_REG
:
1071 tc
->setMiscReg(MISCREG_MMU_LSU_CTRL
, data
);
1076 tc
->setMiscReg(MISCREG_MMU_P_CONTEXT
, data
);
1079 tc
->setMiscReg(MISCREG_MMU_S_CONTEXT
, data
);
1082 goto doMmuWriteError
;
1086 assert(mbits(data
,13,6) == data
);
1087 tc
->setMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD
+
1088 (va
>> 4) - 0x3c, data
);
1090 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0
:
1094 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1
:
1098 case ASI_DMMU_CTXT_ZERO_CONFIG
:
1102 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0
:
1104 itb
->c0_tsb_ps0
= data
;
1106 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1
:
1108 itb
->c0_tsb_ps1
= data
;
1110 case ASI_IMMU_CTXT_ZERO_CONFIG
:
1112 itb
->c0_config
= data
;
1114 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0
:
1118 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1
:
1122 case ASI_DMMU_CTXT_NONZERO_CONFIG
:
1126 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0
:
1128 itb
->cx_tsb_ps0
= data
;
1130 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1
:
1132 itb
->cx_tsb_ps1
= data
;
1134 case ASI_IMMU_CTXT_NONZERO_CONFIG
:
1136 itb
->cx_config
= data
;
1138 case ASI_SPARC_ERROR_EN_REG
:
1139 case ASI_SPARC_ERROR_STATUS_REG
:
1140 inform("Ignoring write to SPARC ERROR regsiter\n");
1142 case ASI_HYP_SCRATCHPAD
:
1143 case ASI_SCRATCHPAD
:
1144 tc
->setMiscReg(MISCREG_SCRATCHPAD_R0
+ (va
>> 3), data
);
1152 sext
<59>(bits(data
, 59,0));
1153 itb
->tag_access
= data
;
1156 goto doMmuWriteError
;
1159 case ASI_ITLB_DATA_ACCESS_REG
:
1160 entry_insert
= bits(va
, 8,3);
1162 case ASI_ITLB_DATA_IN_REG
:
1163 assert(entry_insert
!= -1 || mbits(va
,10,9) == va
);
1164 ta_insert
= itb
->tag_access
;
1165 va_insert
= mbits(ta_insert
, 63,13);
1166 ct_insert
= mbits(ta_insert
, 12,0);
1167 part_insert
= tc
->readMiscReg(MISCREG_MMU_PART_ID
);
1168 real_insert
= bits(va
, 9,9);
1169 pte
.populate(data
, bits(va
,10,10) ? PageTableEntry::sun4v
:
1170 PageTableEntry::sun4u
);
1171 itb
->insert(va_insert
, part_insert
, ct_insert
, real_insert
,
1174 case ASI_DTLB_DATA_ACCESS_REG
:
1175 entry_insert
= bits(va
, 8,3);
1177 case ASI_DTLB_DATA_IN_REG
:
1178 assert(entry_insert
!= -1 || mbits(va
,10,9) == va
);
1179 ta_insert
= tag_access
;
1180 va_insert
= mbits(ta_insert
, 63,13);
1181 ct_insert
= mbits(ta_insert
, 12,0);
1182 part_insert
= tc
->readMiscReg(MISCREG_MMU_PART_ID
);
1183 real_insert
= bits(va
, 9,9);
1184 pte
.populate(data
, bits(va
,10,10) ? PageTableEntry::sun4v
:
1185 PageTableEntry::sun4u
);
1186 insert(va_insert
, part_insert
, ct_insert
, real_insert
, pte
,
1189 case ASI_IMMU_DEMAP
:
1192 part_id
= tc
->readMiscReg(MISCREG_MMU_PART_ID
);
1193 switch (bits(va
,5,4)) {
1195 ctx_id
= tc
->readMiscReg(MISCREG_MMU_P_CONTEXT
);
1207 switch (bits(va
,7,6)) {
1208 case 0: // demap page
1210 itb
->demapPage(mbits(va
,63,13), part_id
, bits(va
,9,9), ctx_id
);
1212 case 1: // demap context
1214 itb
->demapContext(part_id
, ctx_id
);
1217 itb
->demapAll(part_id
);
1220 panic("Invalid type for IMMU demap\n");
1229 sext
<59>(bits(data
, 59,0));
1233 tc
->setMiscReg(MISCREG_MMU_PART_ID
, data
);
1236 goto doMmuWriteError
;
1239 case ASI_DMMU_DEMAP
:
1242 part_id
= tc
->readMiscReg(MISCREG_MMU_PART_ID
);
1243 switch (bits(va
,5,4)) {
1245 ctx_id
= tc
->readMiscReg(MISCREG_MMU_P_CONTEXT
);
1248 ctx_id
= tc
->readMiscReg(MISCREG_MMU_S_CONTEXT
);
1257 switch (bits(va
,7,6)) {
1258 case 0: // demap page
1260 demapPage(mbits(va
,63,13), part_id
, bits(va
,9,9), ctx_id
);
1262 case 1: // demap context
1264 demapContext(part_id
, ctx_id
);
1270 panic("Invalid type for IMMU demap\n");
1273 case ASI_SWVR_INTR_RECEIVE
:
1276 // clear all the interrupts that aren't set in the write
1277 SparcISA::Interrupts
* interrupts
=
1278 dynamic_cast<SparcISA::Interrupts
*>(
1279 tc
->getCpuPtr()->getInterruptController(0));
1280 while (interrupts
->get_vec(IT_INT_VEC
) & data
) {
1281 msb
= findMsbSet(interrupts
->get_vec(IT_INT_VEC
) & data
);
1282 tc
->getCpuPtr()->clearInterrupt(0, IT_INT_VEC
, msb
);
1286 case ASI_SWVR_UDB_INTR_W
:
1287 tc
->getSystemPtr()->threadContexts
[bits(data
,12,8)]->getCpuPtr()->
1288 postInterrupt(0, bits(data
, 5, 0), 0);
1292 panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n",
1293 (uint32_t)pkt
->req
->getArchFlags(), pkt
->getAddr(), data
);
1295 pkt
->makeAtomicResponse();
1300 TLB::GetTsbPtr(ThreadContext
*tc
, Addr addr
, int ctx
, Addr
*ptrs
)
1302 uint64_t tag_access
= mbits(addr
,63,13) | mbits(ctx
,12,0);
1303 TLB
*itb
= dynamic_cast<TLB
*>(tc
->getITBPtr());
1304 ptrs
[0] = MakeTsbPtr(Ps0
, tag_access
,
1309 ptrs
[1] = MakeTsbPtr(Ps1
, tag_access
,
1314 ptrs
[2] = MakeTsbPtr(Ps0
, tag_access
,
1319 ptrs
[3] = MakeTsbPtr(Ps1
, tag_access
,
1327 TLB::MakeTsbPtr(TsbPageSize ps
, uint64_t tag_access
, uint64_t c0_tsb
,
1328 uint64_t c0_config
, uint64_t cX_tsb
, uint64_t cX_config
)
1333 if (bits(tag_access
, 12,0) == 0) {
1341 uint64_t ptr
= mbits(tsb
,63,13);
1342 bool split
= bits(tsb
,12,12);
1343 int tsb_size
= bits(tsb
,3,0);
1344 int page_size
= (ps
== Ps0
) ? bits(config
, 2,0) : bits(config
,10,8);
1346 if (ps
== Ps1
&& split
)
1347 ptr
|= ULL(1) << (13 + tsb_size
);
1348 ptr
|= (tag_access
>> (9 + page_size
* 3)) & mask(12+tsb_size
, 4);
1354 TLB::serialize(CheckpointOut
&cp
) const
1356 SERIALIZE_SCALAR(size
);
1357 SERIALIZE_SCALAR(usedEntries
);
1358 SERIALIZE_SCALAR(lastReplaced
);
1360 // convert the pointer based free list into an index based one
1361 std::vector
<int> free_list
;
1362 for (const TlbEntry
*entry
: freeList
)
1363 free_list
.push_back(entry
- tlb
);
1365 SERIALIZE_CONTAINER(free_list
);
1367 SERIALIZE_SCALAR(c0_tsb_ps0
);
1368 SERIALIZE_SCALAR(c0_tsb_ps1
);
1369 SERIALIZE_SCALAR(c0_config
);
1370 SERIALIZE_SCALAR(cx_tsb_ps0
);
1371 SERIALIZE_SCALAR(cx_tsb_ps1
);
1372 SERIALIZE_SCALAR(cx_config
);
1373 SERIALIZE_SCALAR(sfsr
);
1374 SERIALIZE_SCALAR(tag_access
);
1375 SERIALIZE_SCALAR(sfar
);
1377 for (int x
= 0; x
< size
; x
++) {
1378 ScopedCheckpointSection
sec(cp
, csprintf("PTE%d", x
));
1379 tlb
[x
].serialize(cp
);
1384 TLB::unserialize(CheckpointIn
&cp
)
1388 paramIn(cp
, "size", oldSize
);
1389 if (oldSize
!= size
)
1390 panic("Don't support unserializing different sized TLBs\n");
1391 UNSERIALIZE_SCALAR(usedEntries
);
1392 UNSERIALIZE_SCALAR(lastReplaced
);
1394 std::vector
<int> free_list
;
1395 UNSERIALIZE_CONTAINER(free_list
);
1397 for (int idx
: free_list
)
1398 freeList
.push_back(&tlb
[idx
]);
1400 UNSERIALIZE_SCALAR(c0_tsb_ps0
);
1401 UNSERIALIZE_SCALAR(c0_tsb_ps1
);
1402 UNSERIALIZE_SCALAR(c0_config
);
1403 UNSERIALIZE_SCALAR(cx_tsb_ps0
);
1404 UNSERIALIZE_SCALAR(cx_tsb_ps1
);
1405 UNSERIALIZE_SCALAR(cx_config
);
1406 UNSERIALIZE_SCALAR(sfsr
);
1407 UNSERIALIZE_SCALAR(tag_access
);
1409 lookupTable
.clear();
1410 for (int x
= 0; x
< size
; x
++) {
1411 ScopedCheckpointSection
sec(cp
, csprintf("PTE%d", x
));
1412 tlb
[x
].unserialize(cp
);
1414 lookupTable
.insert(tlb
[x
].range
, &tlb
[x
]);
1417 UNSERIALIZE_SCALAR(sfar
);
1420 } // namespace SparcISA
1423 SparcTLBParams::create()
1425 return new SparcISA::TLB(this);