src/arch/sparc/tlb.cc

   1 /*
   2  * Copyright (c) 2001-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Ali Saidi
  29  */
  30
  31 #include <cstring>
  32
  33 #include "arch/sparc/asi.hh"
  34 #include "arch/sparc/faults.hh"
  35 #include "arch/sparc/registers.hh"
  36 #include "arch/sparc/tlb.hh"
  37 #include "base/bitfield.hh"
  38 #include "base/trace.hh"
  39 #include "cpu/base.hh"
  40 #include "cpu/thread_context.hh"
  41 #include "debug/IPR.hh"
  42 #include "debug/TLB.hh"
  43 #include "mem/packet_access.hh"
  44 #include "mem/request.hh"
  45 #include "sim/full_system.hh"
  46 #include "sim/system.hh"
  47
  48 /* @todo remove some of the magic constants.  -- ali
  49  * */
  50 namespace SparcISA {
  51
  52 TLB::TLB(const Params *p)
  53     : BaseTLB(p), size(p->size), usedEntries(0), lastReplaced(0),
  54       cacheState(0), cacheValid(false)
  55 {
  56     // To make this work you'll have to change the hypervisor and OS
  57     if (size > 64)
  58         fatal("SPARC T1 TLB registers don't support more than 64 TLB entries");
  59
  60     tlb = new TlbEntry[size];
  61     std::memset(tlb, 0, sizeof(TlbEntry) * size);
  62
  63     for (int x = 0; x < size; x++)
  64         freeList.push_back(&tlb[x]);
  65
  66     c0_tsb_ps0 = 0;
  67     c0_tsb_ps1 = 0;
  68     c0_config = 0;
  69     cx_tsb_ps0 = 0;
  70     cx_tsb_ps1 = 0;
  71     cx_config = 0;
  72     sfsr = 0;
  73     tag_access = 0;
  74     sfar = 0;
  75     cacheEntry[0] = NULL;
  76     cacheEntry[1] = NULL;
  77 }
  78
  79 void
  80 TLB::clearUsedBits()
  81 {
  82     MapIter i;
  83     for (i = lookupTable.begin(); i != lookupTable.end(); i++) {
  84         TlbEntry *t = i->second;
  85         if (!t->pte.locked()) {
  86             t->used = false;
  87             usedEntries--;
  88         }
  89     }
  90 }
  91
  92
  93 void
  94 TLB::insert(Addr va, int partition_id, int context_id, bool real,
  95         const PageTableEntry& PTE, int entry)
  96 {
  97     MapIter i;
  98     TlbEntry *new_entry = NULL;
  99 //    TlbRange tr;
 100     int x;
 101
 102     cacheValid = false;
 103     va &= ~(PTE.size()-1);
 104  /*   tr.va = va;
 105     tr.size = PTE.size() - 1;
 106     tr.contextId = context_id;
 107     tr.partitionId = partition_id;
 108     tr.real = real;
 109 */
 110
 111     DPRINTF(TLB,
 112         "TLB: Inserting Entry; va=%#x pa=%#x pid=%d cid=%d r=%d entryid=%d\n",
 113         va, PTE.paddr(), partition_id, context_id, (int)real, entry);
 114
 115     // Demap any entry that conflicts
 116     for (x = 0; x < size; x++) {
 117         if (tlb[x].range.real == real &&
 118             tlb[x].range.partitionId == partition_id &&
 119             tlb[x].range.va < va + PTE.size() - 1 &&
 120             tlb[x].range.va + tlb[x].range.size >= va &&
 121             (real || tlb[x].range.contextId == context_id ))
 122         {
 123             if (tlb[x].valid) {
 124                 freeList.push_front(&tlb[x]);
 125                 DPRINTF(TLB, "TLB: Conflicting entry %#X , deleting it\n", x);
 126
 127                 tlb[x].valid = false;
 128                 if (tlb[x].used) {
 129                     tlb[x].used = false;
 130                     usedEntries--;
 131                 }
 132                 lookupTable.erase(tlb[x].range);
 133             }
 134         }
 135     }
 136
 137     if (entry != -1) {
 138         assert(entry < size && entry >= 0);
 139         new_entry = &tlb[entry];
 140     } else {
 141         if (!freeList.empty()) {
 142             new_entry = freeList.front();
 143         } else {
 144             x = lastReplaced;
 145             do {
 146                 ++x;
 147                 if (x == size)
 148                     x = 0;
 149                 if (x == lastReplaced)
 150                     goto insertAllLocked;
 151             } while (tlb[x].pte.locked());
 152             lastReplaced = x;
 153             new_entry = &tlb[x];
 154         }
 155     }
 156
 157 insertAllLocked:
 158     // Update the last ently if their all locked
 159     if (!new_entry) {
 160         new_entry = &tlb[size-1];
 161     }
 162
 163     freeList.remove(new_entry);
 164     if (new_entry->valid && new_entry->used)
 165         usedEntries--;
 166     if (new_entry->valid)
 167         lookupTable.erase(new_entry->range);
 168
 169
 170     assert(PTE.valid());
 171     new_entry->range.va = va;
 172     new_entry->range.size = PTE.size() - 1;
 173     new_entry->range.partitionId = partition_id;
 174     new_entry->range.contextId = context_id;
 175     new_entry->range.real = real;
 176     new_entry->pte = PTE;
 177     new_entry->used = true;;
 178     new_entry->valid = true;
 179     usedEntries++;
 180
 181     i = lookupTable.insert(new_entry->range, new_entry);
 182     assert(i != lookupTable.end());
 183
 184     // If all entries have their used bit set, clear it on them all,
 185     // but the one we just inserted
 186     if (usedEntries == size) {
 187         clearUsedBits();
 188         new_entry->used = true;
 189         usedEntries++;
 190     }
 191 }
 192
 193
 194 TlbEntry*
 195 TLB::lookup(Addr va, int partition_id, bool real, int context_id,
 196             bool update_used)
 197 {
 198     MapIter i;
 199     TlbRange tr;
 200     TlbEntry *t;
 201
 202     DPRINTF(TLB, "TLB: Looking up entry va=%#x pid=%d cid=%d r=%d\n",
 203             va, partition_id, context_id, real);
 204     // Assemble full address structure
 205     tr.va = va;
 206     tr.size = 1;
 207     tr.contextId = context_id;
 208     tr.partitionId = partition_id;
 209     tr.real = real;
 210
 211     // Try to find the entry
 212     i = lookupTable.find(tr);
 213     if (i == lookupTable.end()) {
 214         DPRINTF(TLB, "TLB: No valid entry found\n");
 215         return NULL;
 216     }
 217
 218     // Mark the entries used bit and clear other used bits in needed
 219     t = i->second;
 220     DPRINTF(TLB, "TLB: Valid entry found pa: %#x size: %#x\n", t->pte.paddr(),
 221             t->pte.size());
 222
 223     // Update the used bits only if this is a real access (not a fake
 224     // one from virttophys()
 225     if (!t->used && update_used) {
 226         t->used = true;
 227         usedEntries++;
 228         if (usedEntries == size) {
 229             clearUsedBits();
 230             t->used = true;
 231             usedEntries++;
 232         }
 233     }
 234
 235     return t;
 236 }
 237
 238 void
 239 TLB::dumpAll()
 240 {
 241     MapIter i;
 242     for (int x = 0; x < size; x++) {
 243         if (tlb[x].valid) {
 244            DPRINTFN("%4d:  %#2x:%#2x %c %#4x %#8x %#8x %#16x\n",
 245                    x, tlb[x].range.partitionId, tlb[x].range.contextId,
 246                    tlb[x].range.real ? 'R' : ' ', tlb[x].range.size,
 247                    tlb[x].range.va, tlb[x].pte.paddr(), tlb[x].pte());
 248         }
 249     }
 250 }
 251
 252 void
 253 TLB::demapPage(Addr va, int partition_id, bool real, int context_id)
 254 {
 255     TlbRange tr;
 256     MapIter i;
 257
 258     DPRINTF(IPR, "TLB: Demapping Page va=%#x pid=%#d cid=%d r=%d\n",
 259             va, partition_id, context_id, real);
 260
 261     cacheValid = false;
 262
 263     // Assemble full address structure
 264     tr.va = va;
 265     tr.size = 1;
 266     tr.contextId = context_id;
 267     tr.partitionId = partition_id;
 268     tr.real = real;
 269
 270     // Demap any entry that conflicts
 271     i = lookupTable.find(tr);
 272     if (i != lookupTable.end()) {
 273         DPRINTF(IPR, "TLB: Demapped page\n");
 274         i->second->valid = false;
 275         if (i->second->used) {
 276             i->second->used = false;
 277             usedEntries--;
 278         }
 279         freeList.push_front(i->second);
 280         lookupTable.erase(i);
 281     }
 282 }
 283
 284 void
 285 TLB::demapContext(int partition_id, int context_id)
 286 {
 287     DPRINTF(IPR, "TLB: Demapping Context pid=%#d cid=%d\n",
 288             partition_id, context_id);
 289     cacheValid = false;
 290     for (int x = 0; x < size; x++) {
 291         if (tlb[x].range.contextId == context_id &&
 292             tlb[x].range.partitionId == partition_id) {
 293             if (tlb[x].valid) {
 294                 freeList.push_front(&tlb[x]);
 295             }
 296             tlb[x].valid = false;
 297             if (tlb[x].used) {
 298                 tlb[x].used = false;
 299                 usedEntries--;
 300             }
 301             lookupTable.erase(tlb[x].range);
 302         }
 303     }
 304 }
 305
 306 void
 307 TLB::demapAll(int partition_id)
 308 {
 309     DPRINTF(TLB, "TLB: Demapping All pid=%#d\n", partition_id);
 310     cacheValid = false;
 311     for (int x = 0; x < size; x++) {
 312         if (tlb[x].valid && !tlb[x].pte.locked() &&
 313                 tlb[x].range.partitionId == partition_id) {
 314             freeList.push_front(&tlb[x]);
 315             tlb[x].valid = false;
 316             if (tlb[x].used) {
 317                 tlb[x].used = false;
 318                 usedEntries--;
 319             }
 320             lookupTable.erase(tlb[x].range);
 321         }
 322     }
 323 }
 324
 325 void
 326 TLB::flushAll()
 327 {
 328     cacheValid = false;
 329     lookupTable.clear();
 330
 331     for (int x = 0; x < size; x++) {
 332         if (tlb[x].valid)
 333             freeList.push_back(&tlb[x]);
 334         tlb[x].valid = false;
 335         tlb[x].used = false;
 336     }
 337     usedEntries = 0;
 338 }
 339
 340 uint64_t
 341 TLB::TteRead(int entry)
 342 {
 343     if (entry >= size)
 344         panic("entry: %d\n", entry);
 345
 346     assert(entry < size);
 347     if (tlb[entry].valid)
 348         return tlb[entry].pte();
 349     else
 350         return (uint64_t)-1ll;
 351 }
 352
 353 uint64_t
 354 TLB::TagRead(int entry)
 355 {
 356     assert(entry < size);
 357     uint64_t tag;
 358     if (!tlb[entry].valid)
 359         return (uint64_t)-1ll;
 360
 361     tag = tlb[entry].range.contextId;
 362     tag |= tlb[entry].range.va;
 363     tag |= (uint64_t)tlb[entry].range.partitionId << 61;
 364     tag |= tlb[entry].range.real ? ULL(1) << 60 : 0;
 365     tag |= (uint64_t)~tlb[entry].pte._size() << 56;
 366     return tag;
 367 }
 368
 369 bool
 370 TLB::validVirtualAddress(Addr va, bool am)
 371 {
 372     if (am)
 373         return true;
 374     if (va >= StartVAddrHole && va <= EndVAddrHole)
 375         return false;
 376     return true;
 377 }
 378
 379 void
 380 TLB::writeSfsr(bool write, ContextType ct, bool se, FaultTypes ft, int asi)
 381 {
 382     if (sfsr & 0x1)
 383         sfsr = 0x3;
 384     else
 385         sfsr = 1;
 386
 387     if (write)
 388         sfsr |= 1 << 2;
 389     sfsr |= ct << 4;
 390     if (se)
 391         sfsr |= 1 << 6;
 392     sfsr |= ft << 7;
 393     sfsr |= asi << 16;
 394 }
 395
 396 void
 397 TLB::writeTagAccess(Addr va, int context)
 398 {
 399     DPRINTF(TLB, "TLB: Writing Tag Access: va: %#X ctx: %#X value: %#X\n",
 400             va, context, mbits(va, 63,13) | mbits(context,12,0));
 401
 402     tag_access = mbits(va, 63,13) | mbits(context,12,0);
 403 }
 404
 405 void
 406 TLB::writeSfsr(Addr a, bool write, ContextType ct,
 407         bool se, FaultTypes ft, int asi)
 408 {
 409     DPRINTF(TLB, "TLB: Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n",
 410             a, (int)write, ct, ft, asi);
 411     TLB::writeSfsr(write, ct, se, ft, asi);
 412     sfar = a;
 413 }
 414
 415 Fault
 416 TLB::translateInst(RequestPtr req, ThreadContext *tc)
 417 {
 418     uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA);
 419
 420     Addr vaddr = req->getVaddr();
 421     TlbEntry *e;
 422
 423     assert(req->getArchFlags() == ASI_IMPLICIT);
 424
 425     DPRINTF(TLB, "TLB: ITB Request to translate va=%#x size=%d\n",
 426             vaddr, req->getSize());
 427
 428     // Be fast if we can!
 429     if (cacheValid && cacheState == tlbdata) {
 430         if (cacheEntry[0]) {
 431             if (cacheEntry[0]->range.va < vaddr + sizeof(MachInst) &&
 432                 cacheEntry[0]->range.va + cacheEntry[0]->range.size >= vaddr) {
 433                 req->setPaddr(cacheEntry[0]->pte.translate(vaddr));
 434                 return NoFault;
 435             }
 436         } else {
 437             req->setPaddr(vaddr & PAddrImplMask);
 438             return NoFault;
 439         }
 440     }
 441
 442     bool hpriv = bits(tlbdata,0,0);
 443     bool red = bits(tlbdata,1,1);
 444     bool priv = bits(tlbdata,2,2);
 445     bool addr_mask = bits(tlbdata,3,3);
 446     bool lsu_im = bits(tlbdata,4,4);
 447
 448     int part_id = bits(tlbdata,15,8);
 449     int tl = bits(tlbdata,18,16);
 450     int pri_context = bits(tlbdata,47,32);
 451     int context;
 452     ContextType ct;
 453     int asi;
 454     bool real = false;
 455
 456     DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsuim:%d part_id: %#X\n",
 457            priv, hpriv, red, lsu_im, part_id);
 458
 459     if (tl > 0) {
 460         asi = ASI_N;
 461         ct = Nucleus;
 462         context = 0;
 463     } else {
 464         asi = ASI_P;
 465         ct = Primary;
 466         context = pri_context;
 467     }
 468
 469     if ( hpriv || red ) {
 470         cacheValid = true;
 471         cacheState = tlbdata;
 472         cacheEntry[0] = NULL;
 473         req->setPaddr(vaddr & PAddrImplMask);
 474         return NoFault;
 475     }
 476
 477     // If the access is unaligned trap
 478     if (vaddr & 0x3) {
 479         writeSfsr(false, ct, false, OtherFault, asi);
 480         return new MemAddressNotAligned;
 481     }
 482
 483     if (addr_mask)
 484         vaddr = vaddr & VAddrAMask;
 485
 486     if (!validVirtualAddress(vaddr, addr_mask)) {
 487         writeSfsr(false, ct, false, VaOutOfRange, asi);
 488         return new InstructionAccessException;
 489     }
 490
 491     if (!lsu_im) {
 492         e = lookup(vaddr, part_id, true);
 493         real = true;
 494         context = 0;
 495     } else {
 496         e = lookup(vaddr, part_id, false, context);
 497     }
 498
 499     if (e == NULL || !e->valid) {
 500         writeTagAccess(vaddr, context);
 501         if (real) {
 502             return new InstructionRealTranslationMiss;
 503         } else {
 504             if (FullSystem)
 505                 return new FastInstructionAccessMMUMiss;
 506             else
 507                 return new FastInstructionAccessMMUMiss(req->getVaddr());
 508         }
 509     }
 510
 511     // were not priviledged accesing priv page
 512     if (!priv && e->pte.priv()) {
 513         writeTagAccess(vaddr, context);
 514         writeSfsr(false, ct, false, PrivViolation, asi);
 515         return new InstructionAccessException;
 516     }
 517
 518     // cache translation date for next translation
 519     cacheValid = true;
 520     cacheState = tlbdata;
 521     cacheEntry[0] = e;
 522
 523     req->setPaddr(e->pte.translate(vaddr));
 524     DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
 525     return NoFault;
 526 }
 527
 528 Fault
 529 TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
 530 {
 531     /*
 532      * @todo this could really use some profiling and fixing to make
 533      * it faster!
 534      */
 535     uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA);
 536     Addr vaddr = req->getVaddr();
 537     Addr size = req->getSize();
 538     ASI asi;
 539     asi = (ASI)req->getArchFlags();
 540     bool implicit = false;
 541     bool hpriv = bits(tlbdata,0,0);
 542     bool unaligned = vaddr & (size - 1);
 543
 544     DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n",
 545             vaddr, size, asi);
 546
 547     if (lookupTable.size() != 64 - freeList.size())
 548        panic("Lookup table size: %d tlb size: %d\n", lookupTable.size(),
 549                freeList.size());
 550     if (asi == ASI_IMPLICIT)
 551         implicit = true;
 552
 553     // Only use the fast path here if there doesn't need to be an unaligned
 554     // trap later
 555     if (!unaligned) {
 556         if (hpriv && implicit) {
 557             req->setPaddr(vaddr & PAddrImplMask);
 558             return NoFault;
 559         }
 560
 561         // Be fast if we can!
 562         if (cacheValid &&  cacheState == tlbdata) {
 563
 564
 565
 566             if (cacheEntry[0]) {
 567                 TlbEntry *ce = cacheEntry[0];
 568                 Addr ce_va = ce->range.va;
 569                 if (cacheAsi[0] == asi &&
 570                     ce_va < vaddr + size && ce_va + ce->range.size > vaddr &&
 571                     (!write || ce->pte.writable())) {
 572                     req->setPaddr(ce->pte.translate(vaddr));
 573                     if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1)
 574                         req->setFlags(Request::UNCACHEABLE);
 575                     DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
 576                     return NoFault;
 577                 } // if matched
 578             } // if cache entry valid
 579             if (cacheEntry[1]) {
 580                 TlbEntry *ce = cacheEntry[1];
 581                 Addr ce_va = ce->range.va;
 582                 if (cacheAsi[1] == asi &&
 583                     ce_va < vaddr + size && ce_va + ce->range.size > vaddr &&
 584                     (!write || ce->pte.writable())) {
 585                     req->setPaddr(ce->pte.translate(vaddr));
 586                     if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1)
 587                         req->setFlags(Request::UNCACHEABLE);
 588                     DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
 589                     return NoFault;
 590                 } // if matched
 591             } // if cache entry valid
 592         }
 593     }
 594
 595     bool red = bits(tlbdata,1,1);
 596     bool priv = bits(tlbdata,2,2);
 597     bool addr_mask = bits(tlbdata,3,3);
 598     bool lsu_dm = bits(tlbdata,5,5);
 599
 600     int part_id = bits(tlbdata,15,8);
 601     int tl = bits(tlbdata,18,16);
 602     int pri_context = bits(tlbdata,47,32);
 603     int sec_context = bits(tlbdata,63,48);
 604
 605     bool real = false;
 606     ContextType ct = Primary;
 607     int context = 0;
 608
 609     TlbEntry *e;
 610
 611     DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsudm:%d part_id: %#X\n",
 612             priv, hpriv, red, lsu_dm, part_id);
 613
 614     if (implicit) {
 615         if (tl > 0) {
 616             asi = ASI_N;
 617             ct = Nucleus;
 618             context = 0;
 619         } else {
 620             asi = ASI_P;
 621             ct = Primary;
 622             context = pri_context;
 623         }
 624     } else {
 625         // We need to check for priv level/asi priv
 626         if (!priv && !hpriv && !asiIsUnPriv(asi)) {
 627             // It appears that context should be Nucleus in these cases?
 628             writeSfsr(vaddr, write, Nucleus, false, IllegalAsi, asi);
 629             return new PrivilegedAction;
 630         }
 631
 632         if (!hpriv && asiIsHPriv(asi)) {
 633             writeSfsr(vaddr, write, Nucleus, false, IllegalAsi, asi);
 634             return new DataAccessException;
 635         }
 636
 637         if (asiIsPrimary(asi)) {
 638             context = pri_context;
 639             ct = Primary;
 640         } else if (asiIsSecondary(asi)) {
 641             context = sec_context;
 642             ct = Secondary;
 643         } else if (asiIsNucleus(asi)) {
 644             ct = Nucleus;
 645             context = 0;
 646         } else {  // ????
 647             ct = Primary;
 648             context = pri_context;
 649         }
 650     }
 651
 652     if (!implicit && asi != ASI_P && asi != ASI_S) {
 653         if (asiIsLittle(asi))
 654             panic("Little Endian ASIs not supported\n");
 655
 656         //XXX It's unclear from looking at the documentation how a no fault
 657         // load differs from a regular one, other than what happens concerning
 658         // nfo and e bits in the TTE
 659 //        if (asiIsNoFault(asi))
 660 //            panic("No Fault ASIs not supported\n");
 661
 662         if (asiIsPartialStore(asi))
 663             panic("Partial Store ASIs not supported\n");
 664
 665         if (asiIsCmt(asi))
 666             panic("Cmt ASI registers not implmented\n");
 667
 668         if (asiIsInterrupt(asi))
 669             goto handleIntRegAccess;
 670         if (asiIsMmu(asi))
 671             goto handleMmuRegAccess;
 672         if (asiIsScratchPad(asi))
 673             goto handleScratchRegAccess;
 674         if (asiIsQueue(asi))
 675             goto handleQueueRegAccess;
 676         if (asiIsSparcError(asi))
 677             goto handleSparcErrorRegAccess;
 678
 679         if (!asiIsReal(asi) && !asiIsNucleus(asi) && !asiIsAsIfUser(asi) &&
 680                 !asiIsTwin(asi) && !asiIsBlock(asi) && !asiIsNoFault(asi))
 681             panic("Accessing ASI %#X. Should we?\n", asi);
 682     }
 683
 684     // If the asi is unaligned trap
 685     if (unaligned) {
 686         writeSfsr(vaddr, false, ct, false, OtherFault, asi);
 687         return new MemAddressNotAligned;
 688     }
 689
 690     if (addr_mask)
 691         vaddr = vaddr & VAddrAMask;
 692
 693     if (!validVirtualAddress(vaddr, addr_mask)) {
 694         writeSfsr(vaddr, false, ct, true, VaOutOfRange, asi);
 695         return new DataAccessException;
 696     }
 697
 698     if ((!lsu_dm && !hpriv && !red) || asiIsReal(asi)) {
 699         real = true;
 700         context = 0;
 701     }
 702
 703     if (hpriv && (implicit || (!asiIsAsIfUser(asi) && !asiIsReal(asi)))) {
 704         req->setPaddr(vaddr & PAddrImplMask);
 705         return NoFault;
 706     }
 707
 708     e = lookup(vaddr, part_id, real, context);
 709
 710     if (e == NULL || !e->valid) {
 711         writeTagAccess(vaddr, context);
 712         DPRINTF(TLB, "TLB: DTB Failed to find matching TLB entry\n");
 713         if (real) {
 714             return new DataRealTranslationMiss;
 715         } else {
 716             if (FullSystem)
 717                 return new FastDataAccessMMUMiss;
 718             else
 719                 return new FastDataAccessMMUMiss(req->getVaddr());
 720         }
 721
 722     }
 723
 724     if (!priv && e->pte.priv()) {
 725         writeTagAccess(vaddr, context);
 726         writeSfsr(vaddr, write, ct, e->pte.sideffect(), PrivViolation, asi);
 727         return new DataAccessException;
 728     }
 729
 730     if (write && !e->pte.writable()) {
 731         writeTagAccess(vaddr, context);
 732         writeSfsr(vaddr, write, ct, e->pte.sideffect(), OtherFault, asi);
 733         return new FastDataAccessProtection;
 734     }
 735
 736     if (e->pte.nofault() && !asiIsNoFault(asi)) {
 737         writeTagAccess(vaddr, context);
 738         writeSfsr(vaddr, write, ct, e->pte.sideffect(), LoadFromNfo, asi);
 739         return new DataAccessException;
 740     }
 741
 742     if (e->pte.sideffect() && asiIsNoFault(asi)) {
 743         writeTagAccess(vaddr, context);
 744         writeSfsr(vaddr, write, ct, e->pte.sideffect(), SideEffect, asi);
 745         return new DataAccessException;
 746     }
 747
 748     if (e->pte.sideffect() || (e->pte.paddr() >> 39) & 1)
 749         req->setFlags(Request::UNCACHEABLE);
 750
 751     // cache translation date for next translation
 752     cacheState = tlbdata;
 753     if (!cacheValid) {
 754         cacheEntry[1] = NULL;
 755         cacheEntry[0] = NULL;
 756     }
 757
 758     if (cacheEntry[0] != e && cacheEntry[1] != e) {
 759         cacheEntry[1] = cacheEntry[0];
 760         cacheEntry[0] = e;
 761         cacheAsi[1] = cacheAsi[0];
 762         cacheAsi[0] = asi;
 763         if (implicit)
 764             cacheAsi[0] = (ASI)0;
 765     }
 766     cacheValid = true;
 767     req->setPaddr(e->pte.translate(vaddr));
 768     DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
 769     return NoFault;
 770
 771     /** Normal flow ends here. */
 772 handleIntRegAccess:
 773     if (!hpriv) {
 774         writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi);
 775         if (priv)
 776             return new DataAccessException;
 777          else
 778             return new PrivilegedAction;
 779     }
 780
 781     if ((asi == ASI_SWVR_UDB_INTR_W && !write) ||
 782         (asi == ASI_SWVR_UDB_INTR_R && write)) {
 783         writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi);
 784         return new DataAccessException;
 785     }
 786
 787     goto regAccessOk;
 788
 789
 790 handleScratchRegAccess:
 791     if (vaddr > 0x38 || (vaddr >= 0x20 && vaddr < 0x30 && !hpriv)) {
 792         writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi);
 793         return new DataAccessException;
 794     }
 795     goto regAccessOk;
 796
 797 handleQueueRegAccess:
 798     if (!priv  && !hpriv) {
 799         writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi);
 800         return new PrivilegedAction;
 801     }
 802     if ((!hpriv && vaddr & 0xF) || vaddr > 0x3f8 || vaddr < 0x3c0) {
 803         writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi);
 804         return new DataAccessException;
 805     }
 806     goto regAccessOk;
 807
 808 handleSparcErrorRegAccess:
 809     if (!hpriv) {
 810         writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi);
 811         if (priv)
 812             return new DataAccessException;
 813          else
 814             return new PrivilegedAction;
 815     }
 816     goto regAccessOk;
 817
 818
 819 regAccessOk:
 820 handleMmuRegAccess:
 821     DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n");
 822     req->setFlags(Request::MMAPPED_IPR);
 823     req->setPaddr(req->getVaddr());
 824     return NoFault;
 825 };
 826
 827 Fault
 828 TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
 829 {
 830     if (mode == Execute)
 831         return translateInst(req, tc);
 832     else
 833         return translateData(req, tc, mode == Write);
 834 }
 835
 836 void
 837 TLB::translateTiming(RequestPtr req, ThreadContext *tc,
 838         Translation *translation, Mode mode)
 839 {
 840     assert(translation);
 841     translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
 842 }
 843
 844 Fault
 845 TLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode)
 846 {
 847     panic("Not implemented\n");
 848     return NoFault;
 849 }
 850
 851 Fault
 852 TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const
 853 {
 854     return NoFault;
 855 }
 856
 857 Cycles
 858 TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
 859 {
 860     Addr va = pkt->getAddr();
 861     ASI asi = (ASI)pkt->req->getArchFlags();
 862     uint64_t temp;
 863
 864     DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n",
 865          (uint32_t)pkt->req->getArchFlags(), pkt->getAddr());
 866
 867     TLB *itb = tc->getITBPtr();
 868
 869     switch (asi) {
 870       case ASI_LSU_CONTROL_REG:
 871         assert(va == 0);
 872         pkt->set(tc->readMiscReg(MISCREG_MMU_LSU_CTRL));
 873         break;
 874       case ASI_MMU:
 875         switch (va) {
 876           case 0x8:
 877             pkt->set(tc->readMiscReg(MISCREG_MMU_P_CONTEXT));
 878             break;
 879           case 0x10:
 880             pkt->set(tc->readMiscReg(MISCREG_MMU_S_CONTEXT));
 881             break;
 882           default:
 883             goto doMmuReadError;
 884         }
 885         break;
 886       case ASI_QUEUE:
 887         pkt->set(tc->readMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD +
 888                     (va >> 4) - 0x3c));
 889         break;
 890       case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0:
 891         assert(va == 0);
 892         pkt->set(c0_tsb_ps0);
 893         break;
 894       case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1:
 895         assert(va == 0);
 896         pkt->set(c0_tsb_ps1);
 897         break;
 898       case ASI_DMMU_CTXT_ZERO_CONFIG:
 899         assert(va == 0);
 900         pkt->set(c0_config);
 901         break;
 902       case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0:
 903         assert(va == 0);
 904         pkt->set(itb->c0_tsb_ps0);
 905         break;
 906       case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1:
 907         assert(va == 0);
 908         pkt->set(itb->c0_tsb_ps1);
 909         break;
 910       case ASI_IMMU_CTXT_ZERO_CONFIG:
 911         assert(va == 0);
 912         pkt->set(itb->c0_config);
 913         break;
 914       case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0:
 915         assert(va == 0);
 916         pkt->set(cx_tsb_ps0);
 917         break;
 918       case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1:
 919         assert(va == 0);
 920         pkt->set(cx_tsb_ps1);
 921         break;
 922       case ASI_DMMU_CTXT_NONZERO_CONFIG:
 923         assert(va == 0);
 924         pkt->set(cx_config);
 925         break;
 926       case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0:
 927         assert(va == 0);
 928         pkt->set(itb->cx_tsb_ps0);
 929         break;
 930       case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1:
 931         assert(va == 0);
 932         pkt->set(itb->cx_tsb_ps1);
 933         break;
 934       case ASI_IMMU_CTXT_NONZERO_CONFIG:
 935         assert(va == 0);
 936         pkt->set(itb->cx_config);
 937         break;
 938       case ASI_SPARC_ERROR_STATUS_REG:
 939         pkt->set((uint64_t)0);
 940         break;
 941       case ASI_HYP_SCRATCHPAD:
 942       case ASI_SCRATCHPAD:
 943         pkt->set(tc->readMiscReg(MISCREG_SCRATCHPAD_R0 + (va >> 3)));
 944         break;
 945       case ASI_IMMU:
 946         switch (va) {
 947           case 0x0:
 948             temp = itb->tag_access;
 949             pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48);
 950             break;
 951           case 0x18:
 952             pkt->set(itb->sfsr);
 953             break;
 954           case 0x30:
 955             pkt->set(itb->tag_access);
 956             break;
 957           default:
 958             goto doMmuReadError;
 959         }
 960         break;
 961       case ASI_DMMU:
 962         switch (va) {
 963           case 0x0:
 964             temp = tag_access;
 965             pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48);
 966             break;
 967           case 0x18:
 968             pkt->set(sfsr);
 969             break;
 970           case 0x20:
 971             pkt->set(sfar);
 972             break;
 973           case 0x30:
 974             pkt->set(tag_access);
 975             break;
 976           case 0x80:
 977             pkt->set(tc->readMiscReg(MISCREG_MMU_PART_ID));
 978             break;
 979           default:
 980                 goto doMmuReadError;
 981         }
 982         break;
 983       case ASI_DMMU_TSB_PS0_PTR_REG:
 984         pkt->set(MakeTsbPtr(Ps0,
 985             tag_access,
 986             c0_tsb_ps0,
 987             c0_config,
 988             cx_tsb_ps0,
 989             cx_config));
 990         break;
 991       case ASI_DMMU_TSB_PS1_PTR_REG:
 992         pkt->set(MakeTsbPtr(Ps1,
 993                 tag_access,
 994                 c0_tsb_ps1,
 995                 c0_config,
 996                 cx_tsb_ps1,
 997                 cx_config));
 998         break;
 999       case ASI_IMMU_TSB_PS0_PTR_REG:
1000           pkt->set(MakeTsbPtr(Ps0,
1001                 itb->tag_access,
1002                 itb->c0_tsb_ps0,
1003                 itb->c0_config,
1004                 itb->cx_tsb_ps0,
1005                 itb->cx_config));
1006         break;
1007       case ASI_IMMU_TSB_PS1_PTR_REG:
1008           pkt->set(MakeTsbPtr(Ps1,
1009                 itb->tag_access,
1010                 itb->c0_tsb_ps1,
1011                 itb->c0_config,
1012                 itb->cx_tsb_ps1,
1013                 itb->cx_config));
1014         break;
1015       case ASI_SWVR_INTR_RECEIVE:
1016         {
1017             SparcISA::Interrupts * interrupts =
1018                 dynamic_cast<SparcISA::Interrupts *>(
1019                         tc->getCpuPtr()->getInterruptController());
1020             pkt->set(interrupts->get_vec(IT_INT_VEC));
1021         }
1022         break;
1023       case ASI_SWVR_UDB_INTR_R:
1024         {
1025             SparcISA::Interrupts * interrupts =
1026                 dynamic_cast<SparcISA::Interrupts *>(
1027                         tc->getCpuPtr()->getInterruptController());
1028             temp = findMsbSet(interrupts->get_vec(IT_INT_VEC));
1029             tc->getCpuPtr()->clearInterrupt(IT_INT_VEC, temp);
1030             pkt->set(temp);
1031         }
1032         break;
1033       default:
1034 doMmuReadError:
1035         panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n",
1036             (uint32_t)asi, va);
1037     }
1038     pkt->makeAtomicResponse();
1039     return Cycles(1);
1040 }
1041
1042 Cycles
1043 TLB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
1044 {
1045     uint64_t data = pkt->get<uint64_t>();
1046     Addr va = pkt->getAddr();
1047     ASI asi = (ASI)pkt->req->getArchFlags();
1048
1049     Addr ta_insert;
1050     Addr va_insert;
1051     Addr ct_insert;
1052     int part_insert;
1053     int entry_insert = -1;
1054     bool real_insert;
1055     bool ignore;
1056     int part_id;
1057     int ctx_id;
1058     PageTableEntry pte;
1059
1060     DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n",
1061          (uint32_t)asi, va, data);
1062
1063     TLB *itb = tc->getITBPtr();
1064
1065     switch (asi) {
1066       case ASI_LSU_CONTROL_REG:
1067         assert(va == 0);
1068         tc->setMiscReg(MISCREG_MMU_LSU_CTRL, data);
1069         break;
1070       case ASI_MMU:
1071         switch (va) {
1072           case 0x8:
1073             tc->setMiscReg(MISCREG_MMU_P_CONTEXT, data);
1074             break;
1075           case 0x10:
1076             tc->setMiscReg(MISCREG_MMU_S_CONTEXT, data);
1077             break;
1078           default:
1079             goto doMmuWriteError;
1080         }
1081         break;
1082       case ASI_QUEUE:
1083         assert(mbits(data,13,6) == data);
1084         tc->setMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD +
1085                     (va >> 4) - 0x3c, data);
1086         break;
1087       case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0:
1088         assert(va == 0);
1089         c0_tsb_ps0 = data;
1090         break;
1091       case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1:
1092         assert(va == 0);
1093         c0_tsb_ps1 = data;
1094         break;
1095       case ASI_DMMU_CTXT_ZERO_CONFIG:
1096         assert(va == 0);
1097         c0_config = data;
1098         break;
1099       case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0:
1100         assert(va == 0);
1101         itb->c0_tsb_ps0 = data;
1102         break;
1103       case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1:
1104         assert(va == 0);
1105         itb->c0_tsb_ps1 = data;
1106         break;
1107       case ASI_IMMU_CTXT_ZERO_CONFIG:
1108         assert(va == 0);
1109         itb->c0_config = data;
1110         break;
1111       case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0:
1112         assert(va == 0);
1113         cx_tsb_ps0 = data;
1114         break;
1115       case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1:
1116         assert(va == 0);
1117         cx_tsb_ps1 = data;
1118         break;
1119       case ASI_DMMU_CTXT_NONZERO_CONFIG:
1120         assert(va == 0);
1121         cx_config = data;
1122         break;
1123       case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0:
1124         assert(va == 0);
1125         itb->cx_tsb_ps0 = data;
1126         break;
1127       case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1:
1128         assert(va == 0);
1129         itb->cx_tsb_ps1 = data;
1130         break;
1131       case ASI_IMMU_CTXT_NONZERO_CONFIG:
1132         assert(va == 0);
1133         itb->cx_config = data;
1134         break;
1135       case ASI_SPARC_ERROR_EN_REG:
1136       case ASI_SPARC_ERROR_STATUS_REG:
1137         inform("Ignoring write to SPARC ERROR regsiter\n");
1138         break;
1139       case ASI_HYP_SCRATCHPAD:
1140       case ASI_SCRATCHPAD:
1141         tc->setMiscReg(MISCREG_SCRATCHPAD_R0 + (va >> 3), data);
1142         break;
1143       case ASI_IMMU:
1144         switch (va) {
1145           case 0x18:
1146             itb->sfsr = data;
1147             break;
1148           case 0x30:
1149             sext<59>(bits(data, 59,0));
1150             itb->tag_access = data;
1151             break;
1152           default:
1153             goto doMmuWriteError;
1154         }
1155         break;
1156       case ASI_ITLB_DATA_ACCESS_REG:
1157         entry_insert = bits(va, 8,3);
1158       case ASI_ITLB_DATA_IN_REG:
1159         assert(entry_insert != -1 || mbits(va,10,9) == va);
1160         ta_insert = itb->tag_access;
1161         va_insert = mbits(ta_insert, 63,13);
1162         ct_insert = mbits(ta_insert, 12,0);
1163         part_insert = tc->readMiscReg(MISCREG_MMU_PART_ID);
1164         real_insert = bits(va, 9,9);
1165         pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v :
1166                 PageTableEntry::sun4u);
1167         tc->getITBPtr()->insert(va_insert, part_insert, ct_insert, real_insert,
1168                 pte, entry_insert);
1169         break;
1170       case ASI_DTLB_DATA_ACCESS_REG:
1171         entry_insert = bits(va, 8,3);
1172       case ASI_DTLB_DATA_IN_REG:
1173         assert(entry_insert != -1 || mbits(va,10,9) == va);
1174         ta_insert = tag_access;
1175         va_insert = mbits(ta_insert, 63,13);
1176         ct_insert = mbits(ta_insert, 12,0);
1177         part_insert = tc->readMiscReg(MISCREG_MMU_PART_ID);
1178         real_insert = bits(va, 9,9);
1179         pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v :
1180                 PageTableEntry::sun4u);
1181         insert(va_insert, part_insert, ct_insert, real_insert, pte,
1182                entry_insert);
1183         break;
1184       case ASI_IMMU_DEMAP:
1185         ignore = false;
1186         ctx_id = -1;
1187         part_id =  tc->readMiscReg(MISCREG_MMU_PART_ID);
1188         switch (bits(va,5,4)) {
1189           case 0:
1190             ctx_id = tc->readMiscReg(MISCREG_MMU_P_CONTEXT);
1191             break;
1192           case 1:
1193             ignore = true;
1194             break;
1195           case 3:
1196             ctx_id = 0;
1197             break;
1198           default:
1199             ignore = true;
1200         }
1201
1202         switch (bits(va,7,6)) {
1203           case 0: // demap page
1204             if (!ignore)
1205                 tc->getITBPtr()->demapPage(mbits(va,63,13), part_id,
1206                         bits(va,9,9), ctx_id);
1207             break;
1208           case 1: // demap context
1209             if (!ignore)
1210                 tc->getITBPtr()->demapContext(part_id, ctx_id);
1211             break;
1212           case 2:
1213             tc->getITBPtr()->demapAll(part_id);
1214             break;
1215           default:
1216             panic("Invalid type for IMMU demap\n");
1217         }
1218         break;
1219       case ASI_DMMU:
1220         switch (va) {
1221           case 0x18:
1222             sfsr = data;
1223             break;
1224           case 0x30:
1225             sext<59>(bits(data, 59,0));
1226             tag_access = data;
1227             break;
1228           case 0x80:
1229             tc->setMiscReg(MISCREG_MMU_PART_ID, data);
1230             break;
1231           default:
1232             goto doMmuWriteError;
1233         }
1234         break;
1235       case ASI_DMMU_DEMAP:
1236         ignore = false;
1237         ctx_id = -1;
1238         part_id =  tc->readMiscReg(MISCREG_MMU_PART_ID);
1239         switch (bits(va,5,4)) {
1240           case 0:
1241             ctx_id = tc->readMiscReg(MISCREG_MMU_P_CONTEXT);
1242             break;
1243           case 1:
1244             ctx_id = tc->readMiscReg(MISCREG_MMU_S_CONTEXT);
1245             break;
1246           case 3:
1247             ctx_id = 0;
1248             break;
1249           default:
1250             ignore = true;
1251         }
1252
1253         switch (bits(va,7,6)) {
1254           case 0: // demap page
1255             if (!ignore)
1256                 demapPage(mbits(va,63,13), part_id, bits(va,9,9), ctx_id);
1257             break;
1258           case 1: // demap context
1259             if (!ignore)
1260                 demapContext(part_id, ctx_id);
1261             break;
1262           case 2:
1263             demapAll(part_id);
1264             break;
1265           default:
1266             panic("Invalid type for IMMU demap\n");
1267         }
1268         break;
1269        case ASI_SWVR_INTR_RECEIVE:
1270         {
1271             int msb;
1272             // clear all the interrupts that aren't set in the write
1273             SparcISA::Interrupts * interrupts =
1274                 dynamic_cast<SparcISA::Interrupts *>(
1275                         tc->getCpuPtr()->getInterruptController());
1276             while (interrupts->get_vec(IT_INT_VEC) & data) {
1277                 msb = findMsbSet(interrupts->get_vec(IT_INT_VEC) & data);
1278                 tc->getCpuPtr()->clearInterrupt(IT_INT_VEC, msb);
1279             }
1280         }
1281         break;
1282       case ASI_SWVR_UDB_INTR_W:
1283             tc->getSystemPtr()->threadContexts[bits(data,12,8)]->getCpuPtr()->
1284             postInterrupt(bits(data, 5, 0), 0);
1285         break;
1286       default:
1287 doMmuWriteError:
1288         panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n",
1289             (uint32_t)pkt->req->getArchFlags(), pkt->getAddr(), data);
1290     }
1291     pkt->makeAtomicResponse();
1292     return Cycles(1);
1293 }
1294
1295 void
1296 TLB::GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs)
1297 {
1298     uint64_t tag_access = mbits(addr,63,13) | mbits(ctx,12,0);
1299     TLB * itb = tc->getITBPtr();
1300     ptrs[0] = MakeTsbPtr(Ps0, tag_access,
1301                 c0_tsb_ps0,
1302                 c0_config,
1303                 cx_tsb_ps0,
1304                 cx_config);
1305     ptrs[1] = MakeTsbPtr(Ps1, tag_access,
1306                 c0_tsb_ps1,
1307                 c0_config,
1308                 cx_tsb_ps1,
1309                 cx_config);
1310     ptrs[2] = MakeTsbPtr(Ps0, tag_access,
1311                 itb->c0_tsb_ps0,
1312                 itb->c0_config,
1313                 itb->cx_tsb_ps0,
1314                 itb->cx_config);
1315     ptrs[3] = MakeTsbPtr(Ps1, tag_access,
1316                 itb->c0_tsb_ps1,
1317                 itb->c0_config,
1318                 itb->cx_tsb_ps1,
1319                 itb->cx_config);
1320 }
1321
1322 uint64_t
1323 TLB::MakeTsbPtr(TsbPageSize ps, uint64_t tag_access, uint64_t c0_tsb,
1324         uint64_t c0_config, uint64_t cX_tsb, uint64_t cX_config)
1325 {
1326     uint64_t tsb;
1327     uint64_t config;
1328
1329     if (bits(tag_access, 12,0) == 0) {
1330         tsb = c0_tsb;
1331         config = c0_config;
1332     } else {
1333         tsb = cX_tsb;
1334         config = cX_config;
1335     }
1336
1337     uint64_t ptr = mbits(tsb,63,13);
1338     bool split = bits(tsb,12,12);
1339     int tsb_size = bits(tsb,3,0);
1340     int page_size = (ps == Ps0) ? bits(config, 2,0) : bits(config,10,8);
1341
1342     if (ps == Ps1  && split)
1343         ptr |= ULL(1) << (13 + tsb_size);
1344     ptr |= (tag_access >> (9 + page_size * 3)) & mask(12+tsb_size, 4);
1345
1346     return ptr;
1347 }
1348
1349 void
1350 TLB::serialize(std::ostream &os)
1351 {
1352     SERIALIZE_SCALAR(size);
1353     SERIALIZE_SCALAR(usedEntries);
1354     SERIALIZE_SCALAR(lastReplaced);
1355
1356     // convert the pointer based free list into an index based one
1357     int *free_list = (int*)malloc(sizeof(int) * size);
1358     int cntr = 0;
1359     std::list<TlbEntry*>::iterator i;
1360     i = freeList.begin();
1361     while (i != freeList.end()) {
1362         free_list[cntr++] = ((size_t)*i - (size_t)tlb)/ sizeof(TlbEntry);
1363         i++;
1364     }
1365     SERIALIZE_SCALAR(cntr);
1366     SERIALIZE_ARRAY(free_list,  cntr);
1367
1368     SERIALIZE_SCALAR(c0_tsb_ps0);
1369     SERIALIZE_SCALAR(c0_tsb_ps1);
1370     SERIALIZE_SCALAR(c0_config);
1371     SERIALIZE_SCALAR(cx_tsb_ps0);
1372     SERIALIZE_SCALAR(cx_tsb_ps1);
1373     SERIALIZE_SCALAR(cx_config);
1374     SERIALIZE_SCALAR(sfsr);
1375     SERIALIZE_SCALAR(tag_access);
1376
1377     for (int x = 0; x < size; x++) {
1378         nameOut(os, csprintf("%s.PTE%d", name(), x));
1379         tlb[x].serialize(os);
1380     }
1381     SERIALIZE_SCALAR(sfar);
1382 }
1383
1384 void
1385 TLB::unserialize(Checkpoint *cp, const std::string &section)
1386 {
1387     int oldSize;
1388
1389     paramIn(cp, section, "size", oldSize);
1390     if (oldSize != size)
1391         panic("Don't support unserializing different sized TLBs\n");
1392     UNSERIALIZE_SCALAR(usedEntries);
1393     UNSERIALIZE_SCALAR(lastReplaced);
1394
1395     int cntr;
1396     UNSERIALIZE_SCALAR(cntr);
1397
1398     int *free_list = (int*)malloc(sizeof(int) * cntr);
1399     freeList.clear();
1400     UNSERIALIZE_ARRAY(free_list,  cntr);
1401     for (int x = 0; x < cntr; x++)
1402         freeList.push_back(&tlb[free_list[x]]);
1403
1404     UNSERIALIZE_SCALAR(c0_tsb_ps0);
1405     UNSERIALIZE_SCALAR(c0_tsb_ps1);
1406     UNSERIALIZE_SCALAR(c0_config);
1407     UNSERIALIZE_SCALAR(cx_tsb_ps0);
1408     UNSERIALIZE_SCALAR(cx_tsb_ps1);
1409     UNSERIALIZE_SCALAR(cx_config);
1410     UNSERIALIZE_SCALAR(sfsr);
1411     UNSERIALIZE_SCALAR(tag_access);
1412
1413     lookupTable.clear();
1414     for (int x = 0; x < size; x++) {
1415         tlb[x].unserialize(cp, csprintf("%s.PTE%d", section, x));
1416         if (tlb[x].valid)
1417             lookupTable.insert(tlb[x].range, &tlb[x]);
1418
1419     }
1420     UNSERIALIZE_SCALAR(sfar);
1421 }
1422
1423 } // namespace SparcISA
1424
1425 SparcISA::TLB *
1426 SparcTLBParams::create()
1427 {
1428     return new SparcISA::TLB(this);
1429 }