2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 #include "arch/sparc/asi.hh"
34 #include "arch/sparc/miscregfile.hh"
35 #include "arch/sparc/tlb.hh"
36 #include "base/bitfield.hh"
37 #include "base/trace.hh"
38 #include "cpu/thread_context.hh"
39 #include "cpu/base.hh"
40 #include "mem/packet_access.hh"
41 #include "mem/request.hh"
42 #include "sim/builder.hh"
44 /* @todo remove some of the magic constants. -- ali
49 TLB::TLB(const std::string
&name
, int s
)
50 : SimObject(name
), size(s
), usedEntries(0), lastReplaced(0),
53 // To make this work you'll have to change the hypervisor and OS
55 fatal("SPARC T1 TLB registers don't support more than 64 TLB entries.");
57 tlb
= new TlbEntry
[size
];
58 std::memset(tlb
, 0, sizeof(TlbEntry
) * size
);
60 for (int x
= 0; x
< size
; x
++)
61 freeList
.push_back(&tlb
[x
]);
68 for (i
= lookupTable
.begin(); i
!= lookupTable
.end(); i
++) {
69 TlbEntry
*t
= i
->second
;
70 if (!t
->pte
.locked()) {
79 TLB::insert(Addr va
, int partition_id
, int context_id
, bool real
,
80 const PageTableEntry
& PTE
, int entry
)
85 TlbEntry
*new_entry
= NULL
;
90 va
&= ~(PTE
.size()-1);
92 tr.size = PTE.size() - 1;
93 tr.contextId = context_id;
94 tr.partitionId = partition_id;
98 DPRINTF(TLB
, "TLB: Inserting TLB Entry; va=%#x pa=%#x pid=%d cid=%d r=%d entryid=%d\n",
99 va
, PTE
.paddr(), partition_id
, context_id
, (int)real
, entry
);
101 // Demap any entry that conflicts
102 for (x
= 0; x
< size
; x
++) {
103 if (tlb
[x
].range
.real
== real
&&
104 tlb
[x
].range
.partitionId
== partition_id
&&
105 tlb
[x
].range
.va
< va
+ PTE
.size() - 1 &&
106 tlb
[x
].range
.va
+ tlb
[x
].range
.size
>= va
&&
107 (real
|| tlb
[x
].range
.contextId
== context_id
))
110 freeList
.push_front(&tlb
[x
]);
111 DPRINTF(TLB
, "TLB: Conflicting entry %#X , deleting it\n", x
);
113 tlb
[x
].valid
= false;
118 lookupTable
.erase(tlb
[x
].range
);
125 i = lookupTable.find(tr);
126 if (i != lookupTable.end()) {
127 i->second->valid = false;
128 if (i->second->used) {
129 i->second->used = false;
132 freeList.push_front(i->second);
133 DPRINTF(TLB, "TLB: Found conflicting entry %#X , deleting it\n",
135 lookupTable.erase(i);
140 assert(entry
< size
&& entry
>= 0);
141 new_entry
= &tlb
[entry
];
143 if (!freeList
.empty()) {
144 new_entry
= freeList
.front();
151 if (x
== lastReplaced
)
152 goto insertAllLocked
;
153 } while (tlb
[x
].pte
.locked());
158 for (x = 0; x < size; x++) {
159 if (!tlb[x].valid || !tlb[x].used) {
167 // Update the last ently if their all locked
169 new_entry
= &tlb
[size
-1];
172 freeList
.remove(new_entry
);
173 if (new_entry
->valid
&& new_entry
->used
)
175 if (new_entry
->valid
)
176 lookupTable
.erase(new_entry
->range
);
180 new_entry
->range
.va
= va
;
181 new_entry
->range
.size
= PTE
.size() - 1;
182 new_entry
->range
.partitionId
= partition_id
;
183 new_entry
->range
.contextId
= context_id
;
184 new_entry
->range
.real
= real
;
185 new_entry
->pte
= PTE
;
186 new_entry
->used
= true;;
187 new_entry
->valid
= true;
192 i
= lookupTable
.insert(new_entry
->range
, new_entry
);
193 assert(i
!= lookupTable
.end());
195 // If all entries have there used bit set, clear it on them all, but the
196 // one we just inserted
197 if (usedEntries
== size
) {
199 new_entry
->used
= true;
207 TLB::lookup(Addr va
, int partition_id
, bool real
, int context_id
)
213 DPRINTF(TLB
, "TLB: Looking up entry va=%#x pid=%d cid=%d r=%d\n",
214 va
, partition_id
, context_id
, real
);
215 // Assemble full address structure
217 tr
.size
= MachineBytes
;
218 tr
.contextId
= context_id
;
219 tr
.partitionId
= partition_id
;
222 // Try to find the entry
223 i
= lookupTable
.find(tr
);
224 if (i
== lookupTable
.end()) {
225 DPRINTF(TLB
, "TLB: No valid entry found\n");
229 // Mark the entries used bit and clear other used bits in needed
231 DPRINTF(TLB
, "TLB: Valid entry found pa: %#x size: %#x\n", t
->pte
.paddr(),
236 if (usedEntries
== size
) {
250 for (int x
= 0; x
< size
; x
++) {
252 DPRINTFN("%4d: %#2x:%#2x %c %#4x %#8x %#8x %#16x\n",
253 x
, tlb
[x
].range
.partitionId
, tlb
[x
].range
.contextId
,
254 tlb
[x
].range
.real
? 'R' : ' ', tlb
[x
].range
.size
,
255 tlb
[x
].range
.va
, tlb
[x
].pte
.paddr(), tlb
[x
].pte());
261 TLB::demapPage(Addr va
, int partition_id
, bool real
, int context_id
)
266 DPRINTF(IPR
, "TLB: Demapping Page va=%#x pid=%#d cid=%d r=%d\n",
267 va
, partition_id
, context_id
, real
);
271 // Assemble full address structure
273 tr
.size
= MachineBytes
;
274 tr
.contextId
= context_id
;
275 tr
.partitionId
= partition_id
;
278 // Demap any entry that conflicts
279 i
= lookupTable
.find(tr
);
280 if (i
!= lookupTable
.end()) {
281 DPRINTF(IPR
, "TLB: Demapped page\n");
282 i
->second
->valid
= false;
283 if (i
->second
->used
) {
284 i
->second
->used
= false;
287 freeList
.push_front(i
->second
);
288 lookupTable
.erase(i
);
293 TLB::demapContext(int partition_id
, int context_id
)
296 DPRINTF(IPR
, "TLB: Demapping Context pid=%#d cid=%d\n",
297 partition_id
, context_id
);
299 for (x
= 0; x
< size
; x
++) {
300 if (tlb
[x
].range
.contextId
== context_id
&&
301 tlb
[x
].range
.partitionId
== partition_id
) {
302 if (tlb
[x
].valid
== true) {
303 freeList
.push_front(&tlb
[x
]);
305 tlb
[x
].valid
= false;
310 lookupTable
.erase(tlb
[x
].range
);
316 TLB::demapAll(int partition_id
)
319 DPRINTF(TLB
, "TLB: Demapping All pid=%#d\n", partition_id
);
321 for (x
= 0; x
< size
; x
++) {
322 if (!tlb
[x
].pte
.locked() && tlb
[x
].range
.partitionId
== partition_id
) {
323 if (tlb
[x
].valid
== true){
324 freeList
.push_front(&tlb
[x
]);
326 tlb
[x
].valid
= false;
331 lookupTable
.erase(tlb
[x
].range
);
344 for (x
= 0; x
< size
; x
++) {
345 if (tlb
[x
].valid
== true)
346 freeList
.push_back(&tlb
[x
]);
347 tlb
[x
].valid
= false;
354 TLB::TteRead(int entry
) {
356 panic("entry: %d\n", entry
);
358 assert(entry
< size
);
359 if (tlb
[entry
].valid
)
360 return tlb
[entry
].pte();
362 return (uint64_t)-1ll;
366 TLB::TagRead(int entry
) {
367 assert(entry
< size
);
369 if (!tlb
[entry
].valid
)
370 return (uint64_t)-1ll;
372 tag
= tlb
[entry
].range
.contextId
;
373 tag
|= tlb
[entry
].range
.va
;
374 tag
|= (uint64_t)tlb
[entry
].range
.partitionId
<< 61;
375 tag
|= tlb
[entry
].range
.real
? ULL(1) << 60 : 0;
376 tag
|= (uint64_t)~tlb
[entry
].pte
._size() << 56;
381 TLB::validVirtualAddress(Addr va
, bool am
)
385 if (va
>= StartVAddrHole
&& va
<= EndVAddrHole
)
391 TLB::writeSfsr(ThreadContext
*tc
, int reg
, bool write
, ContextType ct
,
392 bool se
, FaultTypes ft
, int asi
)
395 sfsr
= tc
->readMiscReg(reg
);
409 tc
->setMiscRegWithEffect(reg
, sfsr
);
413 TLB::writeTagAccess(ThreadContext
*tc
, int reg
, Addr va
, int context
)
415 DPRINTF(TLB
, "TLB: Writing Tag Access: va: %#X ctx: %#X value: %#X\n",
416 va
, context
, mbits(va
, 63,13) | mbits(context
,12,0));
418 tc
->setMiscRegWithEffect(reg
, mbits(va
, 63,13) | mbits(context
,12,0));
422 ITB::writeSfsr(ThreadContext
*tc
, bool write
, ContextType ct
,
423 bool se
, FaultTypes ft
, int asi
)
425 DPRINTF(TLB
, "TLB: ITB Fault: w=%d ct=%d ft=%d asi=%d\n",
426 (int)write
, ct
, ft
, asi
);
427 TLB::writeSfsr(tc
, MISCREG_MMU_ITLB_SFSR
, write
, ct
, se
, ft
, asi
);
431 ITB::writeTagAccess(ThreadContext
*tc
, Addr va
, int context
)
433 TLB::writeTagAccess(tc
, MISCREG_MMU_ITLB_TAG_ACCESS
, va
, context
);
437 DTB::writeSfr(ThreadContext
*tc
, Addr a
, bool write
, ContextType ct
,
438 bool se
, FaultTypes ft
, int asi
)
440 DPRINTF(TLB
, "TLB: DTB Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n",
441 a
, (int)write
, ct
, ft
, asi
);
442 TLB::writeSfsr(tc
, MISCREG_MMU_DTLB_SFSR
, write
, ct
, se
, ft
, asi
);
443 tc
->setMiscRegWithEffect(MISCREG_MMU_DTLB_SFAR
, a
);
447 DTB::writeTagAccess(ThreadContext
*tc
, Addr va
, int context
)
449 TLB::writeTagAccess(tc
, MISCREG_MMU_DTLB_TAG_ACCESS
, va
, context
);
455 ITB::translate(RequestPtr
&req
, ThreadContext
*tc
)
457 uint64_t tlbdata
= tc
->readMiscReg(MISCREG_TLB_DATA
);
459 Addr vaddr
= req
->getVaddr();
462 assert(req
->getAsi() == ASI_IMPLICIT
);
464 DPRINTF(TLB
, "TLB: ITB Request to translate va=%#x size=%d\n",
465 vaddr
, req
->getSize());
467 // Be fast if we can!
468 if (cacheValid
&& cacheState
== tlbdata
) {
470 if (cacheEntry
->range
.va
< vaddr
+ sizeof(MachInst
) &&
471 cacheEntry
->range
.va
+ cacheEntry
->range
.size
>= vaddr
) {
472 req
->setPaddr(cacheEntry
->pte
.paddr() & ~(cacheEntry
->pte
.size()-1) |
473 vaddr
& cacheEntry
->pte
.size()-1 );
477 req
->setPaddr(vaddr
& PAddrImplMask
);
482 bool hpriv
= bits(tlbdata
,0,0);
483 bool red
= bits(tlbdata
,1,1);
484 bool priv
= bits(tlbdata
,2,2);
485 bool addr_mask
= bits(tlbdata
,3,3);
486 bool lsu_im
= bits(tlbdata
,4,4);
488 int part_id
= bits(tlbdata
,15,8);
489 int tl
= bits(tlbdata
,18,16);
490 int pri_context
= bits(tlbdata
,47,32);
496 DPRINTF(TLB
, "TLB: priv:%d hpriv:%d red:%d lsuim:%d part_id: %#X\n",
497 priv
, hpriv
, red
, lsu_im
, part_id
);
506 context
= pri_context
;
509 if ( hpriv
|| red
) {
511 cacheState
= tlbdata
;
513 req
->setPaddr(vaddr
& PAddrImplMask
);
517 // If the access is unaligned trap
519 writeSfsr(tc
, false, ct
, false, OtherFault
, asi
);
520 return new MemAddressNotAligned
;
524 vaddr
= vaddr
& VAddrAMask
;
526 if (!validVirtualAddress(vaddr
, addr_mask
)) {
527 writeSfsr(tc
, false, ct
, false, VaOutOfRange
, asi
);
528 return new InstructionAccessException
;
532 e
= lookup(vaddr
, part_id
, true);
536 e
= lookup(vaddr
, part_id
, false, context
);
539 if (e
== NULL
|| !e
->valid
) {
540 writeTagAccess(tc
, vaddr
, context
);
542 return new InstructionRealTranslationMiss
;
544 return new FastInstructionAccessMMUMiss
;
547 // were not priviledged accesing priv page
548 if (!priv
&& e
->pte
.priv()) {
549 writeTagAccess(tc
, vaddr
, context
);
550 writeSfsr(tc
, false, ct
, false, PrivViolation
, asi
);
551 return new InstructionAccessException
;
554 // cache translation date for next translation
556 cacheState
= tlbdata
;
559 req
->setPaddr(e
->pte
.paddr() & ~(e
->pte
.size()-1) |
560 vaddr
& e
->pte
.size()-1 );
561 DPRINTF(TLB
, "TLB: %#X -> %#X\n", vaddr
, req
->getPaddr());
568 DTB::translate(RequestPtr
&req
, ThreadContext
*tc
, bool write
)
570 /* @todo this could really use some profiling and fixing to make it faster! */
571 uint64_t tlbdata
= tc
->readMiscReg(MISCREG_TLB_DATA
);
572 Addr vaddr
= req
->getVaddr();
573 Addr size
= req
->getSize();
575 asi
= (ASI
)req
->getAsi();
576 bool implicit
= false;
577 bool hpriv
= bits(tlbdata
,0,0);
579 DPRINTF(TLB
, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n",
582 if (lookupTable
.size() != 64 - freeList
.size())
583 panic("Lookup table size: %d tlb size: %d\n", lookupTable
.size(),
585 if (asi
== ASI_IMPLICIT
)
588 if (hpriv
&& implicit
) {
589 req
->setPaddr(vaddr
& PAddrImplMask
);
593 // Be fast if we can!
594 if (cacheValid
&& cacheState
== tlbdata
) {
595 if (cacheEntry
[0] && cacheAsi
[0] == asi
&& cacheEntry
[0]->range
.va
< vaddr
+ size
&&
596 cacheEntry
[0]->range
.va
+ cacheEntry
[0]->range
.size
> vaddr
&&
597 (!write
|| cacheEntry
[0]->pte
.writable())) {
598 req
->setPaddr(cacheEntry
[0]->pte
.paddr() & ~(cacheEntry
[0]->pte
.size()-1) |
599 vaddr
& cacheEntry
[0]->pte
.size()-1 );
602 if (cacheEntry
[1] && cacheAsi
[1] == asi
&& cacheEntry
[1]->range
.va
< vaddr
+ size
&&
603 cacheEntry
[1]->range
.va
+ cacheEntry
[1]->range
.size
> vaddr
&&
604 (!write
|| cacheEntry
[1]->pte
.writable())) {
605 req
->setPaddr(cacheEntry
[1]->pte
.paddr() & ~(cacheEntry
[1]->pte
.size()-1) |
606 vaddr
& cacheEntry
[1]->pte
.size()-1 );
611 bool red
= bits(tlbdata
,1,1);
612 bool priv
= bits(tlbdata
,2,2);
613 bool addr_mask
= bits(tlbdata
,3,3);
614 bool lsu_dm
= bits(tlbdata
,5,5);
616 int part_id
= bits(tlbdata
,15,8);
617 int tl
= bits(tlbdata
,18,16);
618 int pri_context
= bits(tlbdata
,47,32);
619 int sec_context
= bits(tlbdata
,63,48);
622 ContextType ct
= Primary
;
627 DPRINTF(TLB
, "TLB: priv:%d hpriv:%d red:%d lsudm:%d part_id: %#X\n",
628 priv
, hpriv
, red
, lsu_dm
, part_id
);
638 context
= pri_context
;
641 // We need to check for priv level/asi priv
642 if (!priv
&& !hpriv
&& !AsiIsUnPriv(asi
)) {
643 // It appears that context should be Nucleus in these cases?
644 writeSfr(tc
, vaddr
, write
, Nucleus
, false, IllegalAsi
, asi
);
645 return new PrivilegedAction
;
648 if (!hpriv
&& AsiIsHPriv(asi
)) {
649 writeSfr(tc
, vaddr
, write
, Nucleus
, false, IllegalAsi
, asi
);
650 return new DataAccessException
;
653 if (AsiIsPrimary(asi
)) {
654 context
= pri_context
;
656 } else if (AsiIsSecondary(asi
)) {
657 context
= sec_context
;
659 } else if (AsiIsNucleus(asi
)) {
664 context
= pri_context
;
668 if (!implicit
&& asi
!= ASI_P
&& asi
!= ASI_S
) {
669 if (AsiIsLittle(asi
))
670 panic("Little Endian ASIs not supported\n");
672 panic("Block ASIs not supported\n");
673 if (AsiIsNoFault(asi
))
674 panic("No Fault ASIs not supported\n");
676 if (AsiIsPartialStore(asi
))
677 panic("Partial Store ASIs not supported\n");
678 if (AsiIsInterrupt(asi
))
679 panic("Interrupt ASIs not supported\n");
682 goto handleMmuRegAccess
;
683 if (AsiIsScratchPad(asi
))
684 goto handleScratchRegAccess
;
686 goto handleQueueRegAccess
;
687 if (AsiIsSparcError(asi
))
688 goto handleSparcErrorRegAccess
;
690 if (!AsiIsReal(asi
) && !AsiIsNucleus(asi
) && !AsiIsAsIfUser(asi
) &&
692 panic("Accessing ASI %#X. Should we?\n", asi
);
695 // If the asi is unaligned trap
696 if (vaddr
& size
-1) {
697 writeSfr(tc
, vaddr
, false, ct
, false, OtherFault
, asi
);
698 return new MemAddressNotAligned
;
702 vaddr
= vaddr
& VAddrAMask
;
704 if (!validVirtualAddress(vaddr
, addr_mask
)) {
705 writeSfr(tc
, vaddr
, false, ct
, true, VaOutOfRange
, asi
);
706 return new DataAccessException
;
710 if ((!lsu_dm
&& !hpriv
&& !red
) || AsiIsReal(asi
)) {
715 if (hpriv
&& (implicit
|| (!AsiIsAsIfUser(asi
) && !AsiIsReal(asi
)))) {
716 req
->setPaddr(vaddr
& PAddrImplMask
);
720 e
= lookup(vaddr
, part_id
, real
, context
);
722 if (e
== NULL
|| !e
->valid
) {
723 writeTagAccess(tc
, vaddr
, context
);
724 DPRINTF(TLB
, "TLB: DTB Failed to find matching TLB entry\n");
726 return new DataRealTranslationMiss
;
728 return new FastDataAccessMMUMiss
;
732 if (!priv
&& e
->pte
.priv()) {
733 writeTagAccess(tc
, vaddr
, context
);
734 writeSfr(tc
, vaddr
, write
, ct
, e
->pte
.sideffect(), PrivViolation
, asi
);
735 return new DataAccessException
;
738 if (write
&& !e
->pte
.writable()) {
739 writeTagAccess(tc
, vaddr
, context
);
740 writeSfr(tc
, vaddr
, write
, ct
, e
->pte
.sideffect(), OtherFault
, asi
);
741 return new FastDataAccessProtection
;
744 if (e
->pte
.nofault() && !AsiIsNoFault(asi
)) {
745 writeTagAccess(tc
, vaddr
, context
);
746 writeSfr(tc
, vaddr
, write
, ct
, e
->pte
.sideffect(), LoadFromNfo
, asi
);
747 return new DataAccessException
;
750 if (e
->pte
.sideffect() && AsiIsNoFault(asi
)) {
751 writeTagAccess(tc
, vaddr
, context
);
752 writeSfr(tc
, vaddr
, write
, ct
, e
->pte
.sideffect(), SideEffect
, asi
);
753 return new DataAccessException
;
757 if (e
->pte
.sideffect())
758 req
->setFlags(req
->getFlags() | UNCACHEABLE
);
760 // cache translation date for next translation
761 cacheState
= tlbdata
;
763 cacheEntry
[1] = NULL
;
764 cacheEntry
[0] = NULL
;
767 if (cacheEntry
[0] != e
&& cacheEntry
[1] != e
) {
768 cacheEntry
[1] = cacheEntry
[0];
770 cacheAsi
[1] = cacheAsi
[0];
773 cacheAsi
[0] = (ASI
)0;
776 req
->setPaddr(e
->pte
.paddr() & ~(e
->pte
.size()-1) |
777 vaddr
& e
->pte
.size()-1);
778 DPRINTF(TLB
, "TLB: %#X -> %#X\n", vaddr
, req
->getPaddr());
780 /** Normal flow ends here. */
782 handleScratchRegAccess
:
783 if (vaddr
> 0x38 || (vaddr
>= 0x20 && vaddr
< 0x30 && !hpriv
)) {
784 writeSfr(tc
, vaddr
, write
, Primary
, true, IllegalAsi
, asi
);
785 return new DataAccessException
;
789 handleQueueRegAccess
:
790 if (!priv
&& !hpriv
) {
791 writeSfr(tc
, vaddr
, write
, Primary
, true, IllegalAsi
, asi
);
792 return new PrivilegedAction
;
794 if (!hpriv
&& vaddr
& 0xF || vaddr
> 0x3f8 || vaddr
< 0x3c0) {
795 writeSfr(tc
, vaddr
, write
, Primary
, true, IllegalAsi
, asi
);
796 return new DataAccessException
;
800 handleSparcErrorRegAccess
:
803 writeSfr(tc
, vaddr
, write
, Primary
, true, IllegalAsi
, asi
);
804 return new DataAccessException
;
806 writeSfr(tc
, vaddr
, write
, Primary
, true, IllegalAsi
, asi
);
807 return new PrivilegedAction
;
815 DPRINTF(TLB
, "TLB: DTB Translating MM IPR access\n");
816 req
->setMmapedIpr(true);
817 req
->setPaddr(req
->getVaddr());
822 DTB::doMmuRegRead(ThreadContext
*tc
, Packet
*pkt
)
824 Addr va
= pkt
->getAddr();
825 ASI asi
= (ASI
)pkt
->req
->getAsi();
827 uint64_t tsbtemp
, cnftemp
;
829 DPRINTF(IPR
, "Memory Mapped IPR Read: asi=%#X a=%#x\n",
830 (uint32_t)pkt
->req
->getAsi(), pkt
->getAddr());
833 case ASI_LSU_CONTROL_REG
:
835 pkt
->set(tc
->readMiscRegWithEffect(MISCREG_MMU_LSU_CTRL
));
840 pkt
->set(tc
->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT
));
843 pkt
->set(tc
->readMiscRegWithEffect(MISCREG_MMU_S_CONTEXT
));
850 pkt
->set(tc
->readMiscRegWithEffect(MISCREG_QUEUE_CPU_MONDO_HEAD
+
853 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0
:
855 pkt
->set(tc
->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0
));
857 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1
:
859 pkt
->set(tc
->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1
));
861 case ASI_DMMU_CTXT_ZERO_CONFIG
:
863 pkt
->set(tc
->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG
));
865 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0
:
867 pkt
->set(tc
->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0
));
869 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1
:
871 pkt
->set(tc
->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1
));
873 case ASI_IMMU_CTXT_ZERO_CONFIG
:
875 pkt
->set(tc
->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG
));
877 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0
:
879 pkt
->set(tc
->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0
));
881 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1
:
883 pkt
->set(tc
->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1
));
885 case ASI_DMMU_CTXT_NONZERO_CONFIG
:
887 pkt
->set(tc
->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG
));
889 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0
:
891 pkt
->set(tc
->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0
));
893 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1
:
895 pkt
->set(tc
->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1
));
897 case ASI_IMMU_CTXT_NONZERO_CONFIG
:
899 pkt
->set(tc
->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG
));
901 case ASI_SPARC_ERROR_STATUS_REG
:
902 warn("returning 0 for SPARC ERROR regsiter read\n");
903 pkt
->set((uint64_t)0);
905 case ASI_HYP_SCRATCHPAD
:
907 pkt
->set(tc
->readMiscRegWithEffect(MISCREG_SCRATCHPAD_R0
+ (va
>> 3)));
912 temp
= tc
->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS
);
913 pkt
->set(bits(temp
,63,22) | bits(temp
,12,0) << 48);
916 pkt
->set(tc
->readMiscRegWithEffect(MISCREG_MMU_ITLB_SFSR
));
919 pkt
->set(tc
->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS
));
928 temp
= tc
->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS
);
929 pkt
->set(bits(temp
,63,22) | bits(temp
,12,0) << 48);
932 pkt
->set(tc
->readMiscRegWithEffect(MISCREG_MMU_DTLB_SFSR
));
935 pkt
->set(tc
->readMiscRegWithEffect(MISCREG_MMU_DTLB_SFAR
));
938 pkt
->set(tc
->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS
));
941 pkt
->set(tc
->readMiscRegWithEffect(MISCREG_MMU_PART_ID
));
947 case ASI_DMMU_TSB_PS0_PTR_REG
:
948 temp
= tc
->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS
);
949 if (bits(temp
,12,0) == 0) {
950 tsbtemp
= tc
->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0
);
951 cnftemp
= tc
->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG
);
953 tsbtemp
= tc
->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0
);
954 cnftemp
= tc
->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG
);
956 data
= mbits(tsbtemp
,63,13);
957 data
|= temp
>> (9 + bits(cnftemp
,2,0) * 3) &
958 mbits((uint64_t)-1ll,12+bits(tsbtemp
,3,0), 4);
961 case ASI_DMMU_TSB_PS1_PTR_REG
:
962 temp
= tc
->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS
);
963 if (bits(temp
,12,0) == 0) {
964 tsbtemp
= tc
->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1
);
965 cnftemp
= tc
->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG
);
967 tsbtemp
= tc
->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1
);
968 cnftemp
= tc
->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG
);
970 data
= mbits(tsbtemp
,63,13);
971 if (bits(tsbtemp
,12,12))
972 data
|= ULL(1) << (13+bits(tsbtemp
,3,0));
973 data
|= temp
>> (9 + bits(cnftemp
,10,8) * 3) &
974 mbits((uint64_t)-1ll,12+bits(tsbtemp
,3,0), 4);
977 case ASI_IMMU_TSB_PS0_PTR_REG
:
978 temp
= tc
->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS
);
979 if (bits(temp
,12,0) == 0) {
980 tsbtemp
= tc
->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0
);
981 cnftemp
= tc
->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG
);
983 tsbtemp
= tc
->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0
);
984 cnftemp
= tc
->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG
);
986 data
= mbits(tsbtemp
,63,13);
987 data
|= temp
>> (9 + bits(cnftemp
,2,0) * 3) &
988 mbits((uint64_t)-1ll,12+bits(tsbtemp
,3,0), 4);
991 case ASI_IMMU_TSB_PS1_PTR_REG
:
992 temp
= tc
->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS
);
993 if (bits(temp
,12,0) == 0) {
994 tsbtemp
= tc
->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1
);
995 cnftemp
= tc
->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG
);
997 tsbtemp
= tc
->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1
);
998 cnftemp
= tc
->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG
);
1000 data
= mbits(tsbtemp
,63,13);
1001 if (bits(tsbtemp
,12,12))
1002 data
|= ULL(1) << (13+bits(tsbtemp
,3,0));
1003 data
|= temp
>> (9 + bits(cnftemp
,10,8) * 3) &
1004 mbits((uint64_t)-1ll,12+bits(tsbtemp
,3,0), 4);
1010 panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n",
1013 pkt
->result
= Packet::Success
;
1014 return tc
->getCpuPtr()->cycles(1);
1018 DTB::doMmuRegWrite(ThreadContext
*tc
, Packet
*pkt
)
1020 uint64_t data
= gtoh(pkt
->get
<uint64_t>());
1021 Addr va
= pkt
->getAddr();
1022 ASI asi
= (ASI
)pkt
->req
->getAsi();
1028 int entry_insert
= -1;
1035 DPRINTF(IPR
, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n",
1036 (uint32_t)asi
, va
, data
);
1039 case ASI_LSU_CONTROL_REG
:
1041 tc
->setMiscRegWithEffect(MISCREG_MMU_LSU_CTRL
, data
);
1046 tc
->setMiscRegWithEffect(MISCREG_MMU_P_CONTEXT
, data
);
1049 tc
->setMiscRegWithEffect(MISCREG_MMU_S_CONTEXT
, data
);
1052 goto doMmuWriteError
;
1056 assert(mbits(data
,13,6) == data
);
1057 tc
->setMiscRegWithEffect(MISCREG_QUEUE_CPU_MONDO_HEAD
+
1058 (va
>> 4) - 0x3c, data
);
1060 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0
:
1062 tc
->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0
, data
);
1064 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1
:
1066 tc
->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1
, data
);
1068 case ASI_DMMU_CTXT_ZERO_CONFIG
:
1070 tc
->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG
, data
);
1072 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0
:
1074 tc
->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0
, data
);
1076 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1
:
1078 tc
->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1
, data
);
1080 case ASI_IMMU_CTXT_ZERO_CONFIG
:
1082 tc
->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG
, data
);
1084 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0
:
1086 tc
->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0
, data
);
1088 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1
:
1090 tc
->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1
, data
);
1092 case ASI_DMMU_CTXT_NONZERO_CONFIG
:
1094 tc
->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG
, data
);
1096 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0
:
1098 tc
->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0
, data
);
1100 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1
:
1102 tc
->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1
, data
);
1104 case ASI_IMMU_CTXT_NONZERO_CONFIG
:
1106 tc
->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG
, data
);
1108 case ASI_SPARC_ERROR_EN_REG
:
1109 case ASI_SPARC_ERROR_STATUS_REG
:
1110 warn("Ignoring write to SPARC ERROR regsiter\n");
1112 case ASI_HYP_SCRATCHPAD
:
1113 case ASI_SCRATCHPAD
:
1114 tc
->setMiscRegWithEffect(MISCREG_SCRATCHPAD_R0
+ (va
>> 3), data
);
1119 tc
->setMiscRegWithEffect(MISCREG_MMU_ITLB_SFSR
, data
);
1122 sext
<59>(bits(data
, 59,0));
1123 tc
->setMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS
, data
);
1126 goto doMmuWriteError
;
1129 case ASI_ITLB_DATA_ACCESS_REG
:
1130 entry_insert
= bits(va
, 8,3);
1131 case ASI_ITLB_DATA_IN_REG
:
1132 assert(entry_insert
!= -1 || mbits(va
,10,9) == va
);
1133 ta_insert
= tc
->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS
);
1134 va_insert
= mbits(ta_insert
, 63,13);
1135 ct_insert
= mbits(ta_insert
, 12,0);
1136 part_insert
= tc
->readMiscRegWithEffect(MISCREG_MMU_PART_ID
);
1137 real_insert
= bits(va
, 9,9);
1138 pte
.populate(data
, bits(va
,10,10) ? PageTableEntry::sun4v
:
1139 PageTableEntry::sun4u
);
1140 tc
->getITBPtr()->insert(va_insert
, part_insert
, ct_insert
, real_insert
,
1143 case ASI_DTLB_DATA_ACCESS_REG
:
1144 entry_insert
= bits(va
, 8,3);
1145 case ASI_DTLB_DATA_IN_REG
:
1146 assert(entry_insert
!= -1 || mbits(va
,10,9) == va
);
1147 ta_insert
= tc
->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS
);
1148 va_insert
= mbits(ta_insert
, 63,13);
1149 ct_insert
= mbits(ta_insert
, 12,0);
1150 part_insert
= tc
->readMiscRegWithEffect(MISCREG_MMU_PART_ID
);
1151 real_insert
= bits(va
, 9,9);
1152 pte
.populate(data
, bits(va
,10,10) ? PageTableEntry::sun4v
:
1153 PageTableEntry::sun4u
);
1154 insert(va_insert
, part_insert
, ct_insert
, real_insert
, pte
, entry_insert
);
1156 case ASI_IMMU_DEMAP
:
1159 part_id
= tc
->readMiscRegWithEffect(MISCREG_MMU_PART_ID
);
1160 switch (bits(va
,5,4)) {
1162 ctx_id
= tc
->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT
);
1174 switch(bits(va
,7,6)) {
1175 case 0: // demap page
1177 tc
->getITBPtr()->demapPage(mbits(va
,63,13), part_id
,
1178 bits(va
,9,9), ctx_id
);
1180 case 1: //demap context
1182 tc
->getITBPtr()->demapContext(part_id
, ctx_id
);
1185 tc
->getITBPtr()->demapAll(part_id
);
1188 panic("Invalid type for IMMU demap\n");
1194 tc
->setMiscRegWithEffect(MISCREG_MMU_DTLB_SFSR
, data
);
1197 sext
<59>(bits(data
, 59,0));
1198 tc
->setMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS
, data
);
1201 tc
->setMiscRegWithEffect(MISCREG_MMU_PART_ID
, data
);
1204 goto doMmuWriteError
;
1207 case ASI_DMMU_DEMAP
:
1210 part_id
= tc
->readMiscRegWithEffect(MISCREG_MMU_PART_ID
);
1211 switch (bits(va
,5,4)) {
1213 ctx_id
= tc
->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT
);
1216 ctx_id
= tc
->readMiscRegWithEffect(MISCREG_MMU_S_CONTEXT
);
1225 switch(bits(va
,7,6)) {
1226 case 0: // demap page
1228 demapPage(mbits(va
,63,13), part_id
, bits(va
,9,9), ctx_id
);
1230 case 1: //demap context
1232 demapContext(part_id
, ctx_id
);
1238 panic("Invalid type for IMMU demap\n");
1243 panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n",
1244 (uint32_t)pkt
->req
->getAsi(), pkt
->getAddr(), data
);
1246 pkt
->result
= Packet::Success
;
1247 return tc
->getCpuPtr()->cycles(1);
1251 TLB::serialize(std::ostream
&os
)
1253 panic("Need to implement serialize tlb for SPARC\n");
1257 TLB::unserialize(Checkpoint
*cp
, const std::string
§ion
)
1259 panic("Need to implement unserialize tlb for SPARC\n");
1263 DEFINE_SIM_OBJECT_CLASS_NAME("SparcTLB", TLB
)
1265 BEGIN_DECLARE_SIM_OBJECT_PARAMS(ITB
)
1269 END_DECLARE_SIM_OBJECT_PARAMS(ITB
)
1271 BEGIN_INIT_SIM_OBJECT_PARAMS(ITB
)
1273 INIT_PARAM_DFLT(size
, "TLB size", 48)
1275 END_INIT_SIM_OBJECT_PARAMS(ITB
)
1278 CREATE_SIM_OBJECT(ITB
)
1280 return new ITB(getInstanceName(), size
);
1283 REGISTER_SIM_OBJECT("SparcITB", ITB
)
1285 BEGIN_DECLARE_SIM_OBJECT_PARAMS(DTB
)
1289 END_DECLARE_SIM_OBJECT_PARAMS(DTB
)
1291 BEGIN_INIT_SIM_OBJECT_PARAMS(DTB
)
1293 INIT_PARAM_DFLT(size
, "TLB size", 64)
1295 END_INIT_SIM_OBJECT_PARAMS(DTB
)
1298 CREATE_SIM_OBJECT(DTB
)
1300 return new DTB(getInstanceName(), size
);
1303 REGISTER_SIM_OBJECT("SparcDTB", DTB
)