2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 #include "arch/sparc/asi.hh"
34 #include "arch/sparc/miscregfile.hh"
35 #include "arch/sparc/tlb.hh"
36 #include "base/bitfield.hh"
37 #include "base/trace.hh"
38 #include "cpu/thread_context.hh"
39 #include "cpu/base.hh"
40 #include "mem/packet_access.hh"
41 #include "mem/request.hh"
42 #include "sim/builder.hh"
43 #include "sim/system.hh"
45 /* @todo remove some of the magic constants. -- ali
49 TLB::TLB(const std::string
&name
, int s
)
50 : SimObject(name
), size(s
), usedEntries(0), lastReplaced(0),
53 // To make this work you'll have to change the hypervisor and OS
55 fatal("SPARC T1 TLB registers don't support more than 64 TLB entries.");
57 tlb
= new TlbEntry
[size
];
58 std::memset(tlb
, 0, sizeof(TlbEntry
) * size
);
60 for (int x
= 0; x
< size
; x
++)
61 freeList
.push_back(&tlb
[x
]);
68 for (i
= lookupTable
.begin(); i
!= lookupTable
.end(); i
++) {
69 TlbEntry
*t
= i
->second
;
70 if (!t
->pte
.locked()) {
79 TLB::insert(Addr va
, int partition_id
, int context_id
, bool real
,
80 const PageTableEntry
& PTE
, int entry
)
85 TlbEntry
*new_entry
= NULL
;
90 va
&= ~(PTE
.size()-1);
92 tr.size = PTE.size() - 1;
93 tr.contextId = context_id;
94 tr.partitionId = partition_id;
98 DPRINTF(TLB
, "TLB: Inserting TLB Entry; va=%#x pa=%#x pid=%d cid=%d r=%d entryid=%d\n",
99 va
, PTE
.paddr(), partition_id
, context_id
, (int)real
, entry
);
101 // Demap any entry that conflicts
102 for (x
= 0; x
< size
; x
++) {
103 if (tlb
[x
].range
.real
== real
&&
104 tlb
[x
].range
.partitionId
== partition_id
&&
105 tlb
[x
].range
.va
< va
+ PTE
.size() - 1 &&
106 tlb
[x
].range
.va
+ tlb
[x
].range
.size
>= va
&&
107 (real
|| tlb
[x
].range
.contextId
== context_id
))
110 freeList
.push_front(&tlb
[x
]);
111 DPRINTF(TLB
, "TLB: Conflicting entry %#X , deleting it\n", x
);
113 tlb
[x
].valid
= false;
118 lookupTable
.erase(tlb
[x
].range
);
125 i = lookupTable.find(tr);
126 if (i != lookupTable.end()) {
127 i->second->valid = false;
128 if (i->second->used) {
129 i->second->used = false;
132 freeList.push_front(i->second);
133 DPRINTF(TLB, "TLB: Found conflicting entry %#X , deleting it\n",
135 lookupTable.erase(i);
140 assert(entry
< size
&& entry
>= 0);
141 new_entry
= &tlb
[entry
];
143 if (!freeList
.empty()) {
144 new_entry
= freeList
.front();
151 if (x
== lastReplaced
)
152 goto insertAllLocked
;
153 } while (tlb
[x
].pte
.locked());
158 for (x = 0; x < size; x++) {
159 if (!tlb[x].valid || !tlb[x].used) {
167 // Update the last ently if their all locked
169 new_entry
= &tlb
[size
-1];
172 freeList
.remove(new_entry
);
173 if (new_entry
->valid
&& new_entry
->used
)
175 if (new_entry
->valid
)
176 lookupTable
.erase(new_entry
->range
);
180 new_entry
->range
.va
= va
;
181 new_entry
->range
.size
= PTE
.size() - 1;
182 new_entry
->range
.partitionId
= partition_id
;
183 new_entry
->range
.contextId
= context_id
;
184 new_entry
->range
.real
= real
;
185 new_entry
->pte
= PTE
;
186 new_entry
->used
= true;;
187 new_entry
->valid
= true;
192 i
= lookupTable
.insert(new_entry
->range
, new_entry
);
193 assert(i
!= lookupTable
.end());
195 // If all entries have there used bit set, clear it on them all, but the
196 // one we just inserted
197 if (usedEntries
== size
) {
199 new_entry
->used
= true;
207 TLB::lookup(Addr va
, int partition_id
, bool real
, int context_id
, bool
214 DPRINTF(TLB
, "TLB: Looking up entry va=%#x pid=%d cid=%d r=%d\n",
215 va
, partition_id
, context_id
, real
);
216 // Assemble full address structure
218 tr
.size
= MachineBytes
;
219 tr
.contextId
= context_id
;
220 tr
.partitionId
= partition_id
;
223 // Try to find the entry
224 i
= lookupTable
.find(tr
);
225 if (i
== lookupTable
.end()) {
226 DPRINTF(TLB
, "TLB: No valid entry found\n");
230 // Mark the entries used bit and clear other used bits in needed
232 DPRINTF(TLB
, "TLB: Valid entry found pa: %#x size: %#x\n", t
->pte
.paddr(),
235 // Update the used bits only if this is a real access (not a fake one from
237 if (!t
->used
&& update_used
) {
240 if (usedEntries
== size
) {
254 for (int x
= 0; x
< size
; x
++) {
256 DPRINTFN("%4d: %#2x:%#2x %c %#4x %#8x %#8x %#16x\n",
257 x
, tlb
[x
].range
.partitionId
, tlb
[x
].range
.contextId
,
258 tlb
[x
].range
.real
? 'R' : ' ', tlb
[x
].range
.size
,
259 tlb
[x
].range
.va
, tlb
[x
].pte
.paddr(), tlb
[x
].pte());
265 TLB::demapPage(Addr va
, int partition_id
, bool real
, int context_id
)
270 DPRINTF(IPR
, "TLB: Demapping Page va=%#x pid=%#d cid=%d r=%d\n",
271 va
, partition_id
, context_id
, real
);
275 // Assemble full address structure
277 tr
.size
= MachineBytes
;
278 tr
.contextId
= context_id
;
279 tr
.partitionId
= partition_id
;
282 // Demap any entry that conflicts
283 i
= lookupTable
.find(tr
);
284 if (i
!= lookupTable
.end()) {
285 DPRINTF(IPR
, "TLB: Demapped page\n");
286 i
->second
->valid
= false;
287 if (i
->second
->used
) {
288 i
->second
->used
= false;
291 freeList
.push_front(i
->second
);
292 lookupTable
.erase(i
);
297 TLB::demapContext(int partition_id
, int context_id
)
300 DPRINTF(IPR
, "TLB: Demapping Context pid=%#d cid=%d\n",
301 partition_id
, context_id
);
303 for (x
= 0; x
< size
; x
++) {
304 if (tlb
[x
].range
.contextId
== context_id
&&
305 tlb
[x
].range
.partitionId
== partition_id
) {
306 if (tlb
[x
].valid
== true) {
307 freeList
.push_front(&tlb
[x
]);
309 tlb
[x
].valid
= false;
314 lookupTable
.erase(tlb
[x
].range
);
320 TLB::demapAll(int partition_id
)
323 DPRINTF(TLB
, "TLB: Demapping All pid=%#d\n", partition_id
);
325 for (x
= 0; x
< size
; x
++) {
326 if (!tlb
[x
].pte
.locked() && tlb
[x
].range
.partitionId
== partition_id
) {
327 if (tlb
[x
].valid
== true){
328 freeList
.push_front(&tlb
[x
]);
330 tlb
[x
].valid
= false;
335 lookupTable
.erase(tlb
[x
].range
);
348 for (x
= 0; x
< size
; x
++) {
349 if (tlb
[x
].valid
== true)
350 freeList
.push_back(&tlb
[x
]);
351 tlb
[x
].valid
= false;
358 TLB::TteRead(int entry
) {
360 panic("entry: %d\n", entry
);
362 assert(entry
< size
);
363 if (tlb
[entry
].valid
)
364 return tlb
[entry
].pte();
366 return (uint64_t)-1ll;
370 TLB::TagRead(int entry
) {
371 assert(entry
< size
);
373 if (!tlb
[entry
].valid
)
374 return (uint64_t)-1ll;
376 tag
= tlb
[entry
].range
.contextId
;
377 tag
|= tlb
[entry
].range
.va
;
378 tag
|= (uint64_t)tlb
[entry
].range
.partitionId
<< 61;
379 tag
|= tlb
[entry
].range
.real
? ULL(1) << 60 : 0;
380 tag
|= (uint64_t)~tlb
[entry
].pte
._size() << 56;
385 TLB::validVirtualAddress(Addr va
, bool am
)
389 if (va
>= StartVAddrHole
&& va
<= EndVAddrHole
)
395 TLB::writeSfsr(ThreadContext
*tc
, int reg
, bool write
, ContextType ct
,
396 bool se
, FaultTypes ft
, int asi
)
399 sfsr
= tc
->readMiscRegNoEffect(reg
);
413 tc
->setMiscReg(reg
, sfsr
);
417 TLB::writeTagAccess(ThreadContext
*tc
, int reg
, Addr va
, int context
)
419 DPRINTF(TLB
, "TLB: Writing Tag Access: va: %#X ctx: %#X value: %#X\n",
420 va
, context
, mbits(va
, 63,13) | mbits(context
,12,0));
422 tc
->setMiscReg(reg
, mbits(va
, 63,13) | mbits(context
,12,0));
426 ITB::writeSfsr(ThreadContext
*tc
, bool write
, ContextType ct
,
427 bool se
, FaultTypes ft
, int asi
)
429 DPRINTF(TLB
, "TLB: ITB Fault: w=%d ct=%d ft=%d asi=%d\n",
430 (int)write
, ct
, ft
, asi
);
431 TLB::writeSfsr(tc
, MISCREG_MMU_ITLB_SFSR
, write
, ct
, se
, ft
, asi
);
435 ITB::writeTagAccess(ThreadContext
*tc
, Addr va
, int context
)
437 TLB::writeTagAccess(tc
, MISCREG_MMU_ITLB_TAG_ACCESS
, va
, context
);
441 DTB::writeSfr(ThreadContext
*tc
, Addr a
, bool write
, ContextType ct
,
442 bool se
, FaultTypes ft
, int asi
)
444 DPRINTF(TLB
, "TLB: DTB Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n",
445 a
, (int)write
, ct
, ft
, asi
);
446 TLB::writeSfsr(tc
, MISCREG_MMU_DTLB_SFSR
, write
, ct
, se
, ft
, asi
);
447 tc
->setMiscReg(MISCREG_MMU_DTLB_SFAR
, a
);
451 DTB::writeTagAccess(ThreadContext
*tc
, Addr va
, int context
)
453 TLB::writeTagAccess(tc
, MISCREG_MMU_DTLB_TAG_ACCESS
, va
, context
);
459 ITB::translate(RequestPtr
&req
, ThreadContext
*tc
)
461 uint64_t tlbdata
= tc
->readMiscRegNoEffect(MISCREG_TLB_DATA
);
463 Addr vaddr
= req
->getVaddr();
466 assert(req
->getAsi() == ASI_IMPLICIT
);
468 DPRINTF(TLB
, "TLB: ITB Request to translate va=%#x size=%d\n",
469 vaddr
, req
->getSize());
471 // Be fast if we can!
472 if (cacheValid
&& cacheState
== tlbdata
) {
474 if (cacheEntry
->range
.va
< vaddr
+ sizeof(MachInst
) &&
475 cacheEntry
->range
.va
+ cacheEntry
->range
.size
>= vaddr
) {
476 req
->setPaddr(cacheEntry
->pte
.paddr() & ~(cacheEntry
->pte
.size()-1) |
477 vaddr
& cacheEntry
->pte
.size()-1 );
481 req
->setPaddr(vaddr
& PAddrImplMask
);
486 bool hpriv
= bits(tlbdata
,0,0);
487 bool red
= bits(tlbdata
,1,1);
488 bool priv
= bits(tlbdata
,2,2);
489 bool addr_mask
= bits(tlbdata
,3,3);
490 bool lsu_im
= bits(tlbdata
,4,4);
492 int part_id
= bits(tlbdata
,15,8);
493 int tl
= bits(tlbdata
,18,16);
494 int pri_context
= bits(tlbdata
,47,32);
500 DPRINTF(TLB
, "TLB: priv:%d hpriv:%d red:%d lsuim:%d part_id: %#X\n",
501 priv
, hpriv
, red
, lsu_im
, part_id
);
510 context
= pri_context
;
513 if ( hpriv
|| red
) {
515 cacheState
= tlbdata
;
517 req
->setPaddr(vaddr
& PAddrImplMask
);
521 // If the access is unaligned trap
523 writeSfsr(tc
, false, ct
, false, OtherFault
, asi
);
524 return new MemAddressNotAligned
;
528 vaddr
= vaddr
& VAddrAMask
;
530 if (!validVirtualAddress(vaddr
, addr_mask
)) {
531 writeSfsr(tc
, false, ct
, false, VaOutOfRange
, asi
);
532 return new InstructionAccessException
;
536 e
= lookup(vaddr
, part_id
, true);
540 e
= lookup(vaddr
, part_id
, false, context
);
543 if (e
== NULL
|| !e
->valid
) {
544 writeTagAccess(tc
, vaddr
, context
);
546 return new InstructionRealTranslationMiss
;
548 return new FastInstructionAccessMMUMiss
;
551 // were not priviledged accesing priv page
552 if (!priv
&& e
->pte
.priv()) {
553 writeTagAccess(tc
, vaddr
, context
);
554 writeSfsr(tc
, false, ct
, false, PrivViolation
, asi
);
555 return new InstructionAccessException
;
558 // cache translation date for next translation
560 cacheState
= tlbdata
;
563 req
->setPaddr(e
->pte
.paddr() & ~(e
->pte
.size()-1) |
564 vaddr
& e
->pte
.size()-1 );
565 DPRINTF(TLB
, "TLB: %#X -> %#X\n", vaddr
, req
->getPaddr());
572 DTB::translate(RequestPtr
&req
, ThreadContext
*tc
, bool write
)
574 /* @todo this could really use some profiling and fixing to make it faster! */
575 uint64_t tlbdata
= tc
->readMiscRegNoEffect(MISCREG_TLB_DATA
);
576 Addr vaddr
= req
->getVaddr();
577 Addr size
= req
->getSize();
579 asi
= (ASI
)req
->getAsi();
580 bool implicit
= false;
581 bool hpriv
= bits(tlbdata
,0,0);
583 DPRINTF(TLB
, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n",
586 if (lookupTable
.size() != 64 - freeList
.size())
587 panic("Lookup table size: %d tlb size: %d\n", lookupTable
.size(),
589 if (asi
== ASI_IMPLICIT
)
592 if (hpriv
&& implicit
) {
593 req
->setPaddr(vaddr
& PAddrImplMask
);
597 // Be fast if we can!
598 if (cacheValid
&& cacheState
== tlbdata
) {
603 TlbEntry
*ce
= cacheEntry
[0];
604 Addr ce_va
= ce
->range
.va
;
605 if (cacheAsi
[0] == asi
&&
606 ce_va
< vaddr
+ size
&& ce_va
+ ce
->range
.size
> vaddr
&&
607 (!write
|| ce
->pte
.writable())) {
608 req
->setPaddr(ce
->pte
.paddrMask() | vaddr
& ce
->pte
.sizeMask());
609 if (ce
->pte
.sideffect() || (ce
->pte
.paddr() >> 39) & 1)
610 req
->setFlags(req
->getFlags() | UNCACHEABLE
);
611 DPRINTF(TLB
, "TLB: %#X -> %#X\n", vaddr
, req
->getPaddr());
614 } // if cache entry valid
616 TlbEntry
*ce
= cacheEntry
[1];
617 Addr ce_va
= ce
->range
.va
;
618 if (cacheAsi
[1] == asi
&&
619 ce_va
< vaddr
+ size
&& ce_va
+ ce
->range
.size
> vaddr
&&
620 (!write
|| ce
->pte
.writable())) {
621 req
->setPaddr(ce
->pte
.paddrMask() | vaddr
& ce
->pte
.sizeMask());
622 if (ce
->pte
.sideffect() || (ce
->pte
.paddr() >> 39) & 1)
623 req
->setFlags(req
->getFlags() | UNCACHEABLE
);
624 DPRINTF(TLB
, "TLB: %#X -> %#X\n", vaddr
, req
->getPaddr());
627 } // if cache entry valid
630 bool red
= bits(tlbdata
,1,1);
631 bool priv
= bits(tlbdata
,2,2);
632 bool addr_mask
= bits(tlbdata
,3,3);
633 bool lsu_dm
= bits(tlbdata
,5,5);
635 int part_id
= bits(tlbdata
,15,8);
636 int tl
= bits(tlbdata
,18,16);
637 int pri_context
= bits(tlbdata
,47,32);
638 int sec_context
= bits(tlbdata
,63,48);
641 ContextType ct
= Primary
;
646 DPRINTF(TLB
, "TLB: priv:%d hpriv:%d red:%d lsudm:%d part_id: %#X\n",
647 priv
, hpriv
, red
, lsu_dm
, part_id
);
657 context
= pri_context
;
660 // We need to check for priv level/asi priv
661 if (!priv
&& !hpriv
&& !AsiIsUnPriv(asi
)) {
662 // It appears that context should be Nucleus in these cases?
663 writeSfr(tc
, vaddr
, write
, Nucleus
, false, IllegalAsi
, asi
);
664 return new PrivilegedAction
;
667 if (!hpriv
&& AsiIsHPriv(asi
)) {
668 writeSfr(tc
, vaddr
, write
, Nucleus
, false, IllegalAsi
, asi
);
669 return new DataAccessException
;
672 if (AsiIsPrimary(asi
)) {
673 context
= pri_context
;
675 } else if (AsiIsSecondary(asi
)) {
676 context
= sec_context
;
678 } else if (AsiIsNucleus(asi
)) {
683 context
= pri_context
;
687 if (!implicit
&& asi
!= ASI_P
&& asi
!= ASI_S
) {
688 if (AsiIsLittle(asi
))
689 panic("Little Endian ASIs not supported\n");
690 if (AsiIsNoFault(asi
))
691 panic("No Fault ASIs not supported\n");
693 if (AsiIsPartialStore(asi
))
694 panic("Partial Store ASIs not supported\n");
697 panic("Cmt ASI registers not implmented\n");
699 if (AsiIsInterrupt(asi
))
700 goto handleIntRegAccess
;
702 goto handleMmuRegAccess
;
703 if (AsiIsScratchPad(asi
))
704 goto handleScratchRegAccess
;
706 goto handleQueueRegAccess
;
707 if (AsiIsSparcError(asi
))
708 goto handleSparcErrorRegAccess
;
710 if (!AsiIsReal(asi
) && !AsiIsNucleus(asi
) && !AsiIsAsIfUser(asi
) &&
711 !AsiIsTwin(asi
) && !AsiIsBlock(asi
))
712 panic("Accessing ASI %#X. Should we?\n", asi
);
715 // If the asi is unaligned trap
716 if (vaddr
& size
-1) {
717 writeSfr(tc
, vaddr
, false, ct
, false, OtherFault
, asi
);
718 return new MemAddressNotAligned
;
722 vaddr
= vaddr
& VAddrAMask
;
724 if (!validVirtualAddress(vaddr
, addr_mask
)) {
725 writeSfr(tc
, vaddr
, false, ct
, true, VaOutOfRange
, asi
);
726 return new DataAccessException
;
730 if ((!lsu_dm
&& !hpriv
&& !red
) || AsiIsReal(asi
)) {
735 if (hpriv
&& (implicit
|| (!AsiIsAsIfUser(asi
) && !AsiIsReal(asi
)))) {
736 req
->setPaddr(vaddr
& PAddrImplMask
);
740 e
= lookup(vaddr
, part_id
, real
, context
);
742 if (e
== NULL
|| !e
->valid
) {
743 writeTagAccess(tc
, vaddr
, context
);
744 DPRINTF(TLB
, "TLB: DTB Failed to find matching TLB entry\n");
746 return new DataRealTranslationMiss
;
748 return new FastDataAccessMMUMiss
;
752 if (!priv
&& e
->pte
.priv()) {
753 writeTagAccess(tc
, vaddr
, context
);
754 writeSfr(tc
, vaddr
, write
, ct
, e
->pte
.sideffect(), PrivViolation
, asi
);
755 return new DataAccessException
;
758 if (write
&& !e
->pte
.writable()) {
759 writeTagAccess(tc
, vaddr
, context
);
760 writeSfr(tc
, vaddr
, write
, ct
, e
->pte
.sideffect(), OtherFault
, asi
);
761 return new FastDataAccessProtection
;
764 if (e
->pte
.nofault() && !AsiIsNoFault(asi
)) {
765 writeTagAccess(tc
, vaddr
, context
);
766 writeSfr(tc
, vaddr
, write
, ct
, e
->pte
.sideffect(), LoadFromNfo
, asi
);
767 return new DataAccessException
;
770 if (e
->pte
.sideffect() && AsiIsNoFault(asi
)) {
771 writeTagAccess(tc
, vaddr
, context
);
772 writeSfr(tc
, vaddr
, write
, ct
, e
->pte
.sideffect(), SideEffect
, asi
);
773 return new DataAccessException
;
777 if (e
->pte
.sideffect() || (e
->pte
.paddr() >> 39) & 1)
778 req
->setFlags(req
->getFlags() | UNCACHEABLE
);
780 // cache translation date for next translation
781 cacheState
= tlbdata
;
783 cacheEntry
[1] = NULL
;
784 cacheEntry
[0] = NULL
;
787 if (cacheEntry
[0] != e
&& cacheEntry
[1] != e
) {
788 cacheEntry
[1] = cacheEntry
[0];
790 cacheAsi
[1] = cacheAsi
[0];
793 cacheAsi
[0] = (ASI
)0;
796 req
->setPaddr(e
->pte
.paddr() & ~(e
->pte
.size()-1) |
797 vaddr
& e
->pte
.size()-1);
798 DPRINTF(TLB
, "TLB: %#X -> %#X\n", vaddr
, req
->getPaddr());
801 /** Normal flow ends here. */
804 writeSfr(tc
, vaddr
, write
, Primary
, true, IllegalAsi
, asi
);
806 return new DataAccessException
;
808 return new PrivilegedAction
;
811 if (asi
== ASI_SWVR_UDB_INTR_W
&& !write
||
812 asi
== ASI_SWVR_UDB_INTR_R
&& write
) {
813 writeSfr(tc
, vaddr
, write
, Primary
, true, IllegalAsi
, asi
);
814 return new DataAccessException
;
820 handleScratchRegAccess
:
821 if (vaddr
> 0x38 || (vaddr
>= 0x20 && vaddr
< 0x30 && !hpriv
)) {
822 writeSfr(tc
, vaddr
, write
, Primary
, true, IllegalAsi
, asi
);
823 return new DataAccessException
;
827 handleQueueRegAccess
:
828 if (!priv
&& !hpriv
) {
829 writeSfr(tc
, vaddr
, write
, Primary
, true, IllegalAsi
, asi
);
830 return new PrivilegedAction
;
832 if (!hpriv
&& vaddr
& 0xF || vaddr
> 0x3f8 || vaddr
< 0x3c0) {
833 writeSfr(tc
, vaddr
, write
, Primary
, true, IllegalAsi
, asi
);
834 return new DataAccessException
;
838 handleSparcErrorRegAccess
:
840 writeSfr(tc
, vaddr
, write
, Primary
, true, IllegalAsi
, asi
);
842 return new DataAccessException
;
844 return new PrivilegedAction
;
851 DPRINTF(TLB
, "TLB: DTB Translating MM IPR access\n");
852 req
->setMmapedIpr(true);
853 req
->setPaddr(req
->getVaddr());
858 DTB::doMmuRegRead(ThreadContext
*tc
, Packet
*pkt
)
860 Addr va
= pkt
->getAddr();
861 ASI asi
= (ASI
)pkt
->req
->getAsi();
864 DPRINTF(IPR
, "Memory Mapped IPR Read: asi=%#X a=%#x\n",
865 (uint32_t)pkt
->req
->getAsi(), pkt
->getAddr());
868 case ASI_LSU_CONTROL_REG
:
870 pkt
->set(tc
->readMiscReg(MISCREG_MMU_LSU_CTRL
));
875 pkt
->set(tc
->readMiscReg(MISCREG_MMU_P_CONTEXT
));
878 pkt
->set(tc
->readMiscReg(MISCREG_MMU_S_CONTEXT
));
885 pkt
->set(tc
->readMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD
+
888 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0
:
890 pkt
->set(tc
->readMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS0
));
892 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1
:
894 pkt
->set(tc
->readMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS1
));
896 case ASI_DMMU_CTXT_ZERO_CONFIG
:
898 pkt
->set(tc
->readMiscReg(MISCREG_MMU_DTLB_C0_CONFIG
));
900 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0
:
902 pkt
->set(tc
->readMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS0
));
904 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1
:
906 pkt
->set(tc
->readMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS1
));
908 case ASI_IMMU_CTXT_ZERO_CONFIG
:
910 pkt
->set(tc
->readMiscReg(MISCREG_MMU_ITLB_C0_CONFIG
));
912 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0
:
914 pkt
->set(tc
->readMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS0
));
916 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1
:
918 pkt
->set(tc
->readMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS1
));
920 case ASI_DMMU_CTXT_NONZERO_CONFIG
:
922 pkt
->set(tc
->readMiscReg(MISCREG_MMU_DTLB_CX_CONFIG
));
924 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0
:
926 pkt
->set(tc
->readMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS0
));
928 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1
:
930 pkt
->set(tc
->readMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS1
));
932 case ASI_IMMU_CTXT_NONZERO_CONFIG
:
934 pkt
->set(tc
->readMiscReg(MISCREG_MMU_ITLB_CX_CONFIG
));
936 case ASI_SPARC_ERROR_STATUS_REG
:
937 pkt
->set((uint64_t)0);
939 case ASI_HYP_SCRATCHPAD
:
941 pkt
->set(tc
->readMiscReg(MISCREG_SCRATCHPAD_R0
+ (va
>> 3)));
946 temp
= tc
->readMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS
);
947 pkt
->set(bits(temp
,63,22) | bits(temp
,12,0) << 48);
950 pkt
->set(tc
->readMiscReg(MISCREG_MMU_ITLB_SFSR
));
953 pkt
->set(tc
->readMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS
));
962 temp
= tc
->readMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS
);
963 pkt
->set(bits(temp
,63,22) | bits(temp
,12,0) << 48);
966 pkt
->set(tc
->readMiscReg(MISCREG_MMU_DTLB_SFSR
));
969 pkt
->set(tc
->readMiscReg(MISCREG_MMU_DTLB_SFAR
));
972 pkt
->set(tc
->readMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS
));
975 pkt
->set(tc
->readMiscReg(MISCREG_MMU_PART_ID
));
981 case ASI_DMMU_TSB_PS0_PTR_REG
:
982 pkt
->set(MakeTsbPtr(Ps0
,
983 tc
->readMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS
),
984 tc
->readMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS0
),
985 tc
->readMiscReg(MISCREG_MMU_DTLB_C0_CONFIG
),
986 tc
->readMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS0
),
987 tc
->readMiscReg(MISCREG_MMU_DTLB_CX_CONFIG
)));
989 case ASI_DMMU_TSB_PS1_PTR_REG
:
990 pkt
->set(MakeTsbPtr(Ps1
,
991 tc
->readMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS
),
992 tc
->readMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS1
),
993 tc
->readMiscReg(MISCREG_MMU_DTLB_C0_CONFIG
),
994 tc
->readMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS1
),
995 tc
->readMiscReg(MISCREG_MMU_DTLB_CX_CONFIG
)));
997 case ASI_IMMU_TSB_PS0_PTR_REG
:
998 pkt
->set(MakeTsbPtr(Ps0
,
999 tc
->readMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS
),
1000 tc
->readMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS0
),
1001 tc
->readMiscReg(MISCREG_MMU_ITLB_C0_CONFIG
),
1002 tc
->readMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS0
),
1003 tc
->readMiscReg(MISCREG_MMU_ITLB_CX_CONFIG
)));
1005 case ASI_IMMU_TSB_PS1_PTR_REG
:
1006 pkt
->set(MakeTsbPtr(Ps1
,
1007 tc
->readMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS
),
1008 tc
->readMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS1
),
1009 tc
->readMiscReg(MISCREG_MMU_ITLB_C0_CONFIG
),
1010 tc
->readMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS1
),
1011 tc
->readMiscReg(MISCREG_MMU_ITLB_CX_CONFIG
)));
1013 case ASI_SWVR_INTR_RECEIVE
:
1014 pkt
->set(tc
->getCpuPtr()->get_interrupts(IT_INT_VEC
));
1016 case ASI_SWVR_UDB_INTR_R
:
1017 temp
= findMsbSet(tc
->getCpuPtr()->get_interrupts(IT_INT_VEC
));
1018 tc
->getCpuPtr()->clear_interrupt(IT_INT_VEC
, temp
);
1023 panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n",
1026 pkt
->result
= Packet::Success
;
1027 return tc
->getCpuPtr()->cycles(1);
1031 DTB::doMmuRegWrite(ThreadContext
*tc
, Packet
*pkt
)
1033 uint64_t data
= gtoh(pkt
->get
<uint64_t>());
1034 Addr va
= pkt
->getAddr();
1035 ASI asi
= (ASI
)pkt
->req
->getAsi();
1041 int entry_insert
= -1;
1048 DPRINTF(IPR
, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n",
1049 (uint32_t)asi
, va
, data
);
1052 case ASI_LSU_CONTROL_REG
:
1054 tc
->setMiscReg(MISCREG_MMU_LSU_CTRL
, data
);
1059 tc
->setMiscReg(MISCREG_MMU_P_CONTEXT
, data
);
1062 tc
->setMiscReg(MISCREG_MMU_S_CONTEXT
, data
);
1065 goto doMmuWriteError
;
1069 assert(mbits(data
,13,6) == data
);
1070 tc
->setMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD
+
1071 (va
>> 4) - 0x3c, data
);
1073 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0
:
1075 tc
->setMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS0
, data
);
1077 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1
:
1079 tc
->setMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS1
, data
);
1081 case ASI_DMMU_CTXT_ZERO_CONFIG
:
1083 tc
->setMiscReg(MISCREG_MMU_DTLB_C0_CONFIG
, data
);
1085 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0
:
1087 tc
->setMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS0
, data
);
1089 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1
:
1091 tc
->setMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS1
, data
);
1093 case ASI_IMMU_CTXT_ZERO_CONFIG
:
1095 tc
->setMiscReg(MISCREG_MMU_ITLB_C0_CONFIG
, data
);
1097 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0
:
1099 tc
->setMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS0
, data
);
1101 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1
:
1103 tc
->setMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS1
, data
);
1105 case ASI_DMMU_CTXT_NONZERO_CONFIG
:
1107 tc
->setMiscReg(MISCREG_MMU_DTLB_CX_CONFIG
, data
);
1109 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0
:
1111 tc
->setMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS0
, data
);
1113 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1
:
1115 tc
->setMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS1
, data
);
1117 case ASI_IMMU_CTXT_NONZERO_CONFIG
:
1119 tc
->setMiscReg(MISCREG_MMU_ITLB_CX_CONFIG
, data
);
1121 case ASI_SPARC_ERROR_EN_REG
:
1122 case ASI_SPARC_ERROR_STATUS_REG
:
1123 warn("Ignoring write to SPARC ERROR regsiter\n");
1125 case ASI_HYP_SCRATCHPAD
:
1126 case ASI_SCRATCHPAD
:
1127 tc
->setMiscReg(MISCREG_SCRATCHPAD_R0
+ (va
>> 3), data
);
1132 tc
->setMiscReg(MISCREG_MMU_ITLB_SFSR
, data
);
1135 sext
<59>(bits(data
, 59,0));
1136 tc
->setMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS
, data
);
1139 goto doMmuWriteError
;
1142 case ASI_ITLB_DATA_ACCESS_REG
:
1143 entry_insert
= bits(va
, 8,3);
1144 case ASI_ITLB_DATA_IN_REG
:
1145 assert(entry_insert
!= -1 || mbits(va
,10,9) == va
);
1146 ta_insert
= tc
->readMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS
);
1147 va_insert
= mbits(ta_insert
, 63,13);
1148 ct_insert
= mbits(ta_insert
, 12,0);
1149 part_insert
= tc
->readMiscReg(MISCREG_MMU_PART_ID
);
1150 real_insert
= bits(va
, 9,9);
1151 pte
.populate(data
, bits(va
,10,10) ? PageTableEntry::sun4v
:
1152 PageTableEntry::sun4u
);
1153 tc
->getITBPtr()->insert(va_insert
, part_insert
, ct_insert
, real_insert
,
1156 case ASI_DTLB_DATA_ACCESS_REG
:
1157 entry_insert
= bits(va
, 8,3);
1158 case ASI_DTLB_DATA_IN_REG
:
1159 assert(entry_insert
!= -1 || mbits(va
,10,9) == va
);
1160 ta_insert
= tc
->readMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS
);
1161 va_insert
= mbits(ta_insert
, 63,13);
1162 ct_insert
= mbits(ta_insert
, 12,0);
1163 part_insert
= tc
->readMiscReg(MISCREG_MMU_PART_ID
);
1164 real_insert
= bits(va
, 9,9);
1165 pte
.populate(data
, bits(va
,10,10) ? PageTableEntry::sun4v
:
1166 PageTableEntry::sun4u
);
1167 insert(va_insert
, part_insert
, ct_insert
, real_insert
, pte
, entry_insert
);
1169 case ASI_IMMU_DEMAP
:
1172 part_id
= tc
->readMiscReg(MISCREG_MMU_PART_ID
);
1173 switch (bits(va
,5,4)) {
1175 ctx_id
= tc
->readMiscReg(MISCREG_MMU_P_CONTEXT
);
1187 switch(bits(va
,7,6)) {
1188 case 0: // demap page
1190 tc
->getITBPtr()->demapPage(mbits(va
,63,13), part_id
,
1191 bits(va
,9,9), ctx_id
);
1193 case 1: //demap context
1195 tc
->getITBPtr()->demapContext(part_id
, ctx_id
);
1198 tc
->getITBPtr()->demapAll(part_id
);
1201 panic("Invalid type for IMMU demap\n");
1207 tc
->setMiscReg(MISCREG_MMU_DTLB_SFSR
, data
);
1210 sext
<59>(bits(data
, 59,0));
1211 tc
->setMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS
, data
);
1214 tc
->setMiscReg(MISCREG_MMU_PART_ID
, data
);
1217 goto doMmuWriteError
;
1220 case ASI_DMMU_DEMAP
:
1223 part_id
= tc
->readMiscReg(MISCREG_MMU_PART_ID
);
1224 switch (bits(va
,5,4)) {
1226 ctx_id
= tc
->readMiscReg(MISCREG_MMU_P_CONTEXT
);
1229 ctx_id
= tc
->readMiscReg(MISCREG_MMU_S_CONTEXT
);
1238 switch(bits(va
,7,6)) {
1239 case 0: // demap page
1241 demapPage(mbits(va
,63,13), part_id
, bits(va
,9,9), ctx_id
);
1243 case 1: //demap context
1245 demapContext(part_id
, ctx_id
);
1251 panic("Invalid type for IMMU demap\n");
1254 case ASI_SWVR_INTR_RECEIVE
:
1256 // clear all the interrupts that aren't set in the write
1257 while(tc
->getCpuPtr()->get_interrupts(IT_INT_VEC
) & data
) {
1258 msb
= findMsbSet(tc
->getCpuPtr()->get_interrupts(IT_INT_VEC
) & data
);
1259 tc
->getCpuPtr()->clear_interrupt(IT_INT_VEC
, msb
);
1262 case ASI_SWVR_UDB_INTR_W
:
1263 tc
->getSystemPtr()->threadContexts
[bits(data
,12,8)]->getCpuPtr()->
1264 post_interrupt(bits(data
,5,0),0);
1268 panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n",
1269 (uint32_t)pkt
->req
->getAsi(), pkt
->getAddr(), data
);
1271 pkt
->result
= Packet::Success
;
1272 return tc
->getCpuPtr()->cycles(1);
1276 DTB::GetTsbPtr(ThreadContext
*tc
, Addr addr
, int ctx
, Addr
*ptrs
)
1278 uint64_t tag_access
= mbits(addr
,63,13) | mbits(ctx
,12,0);
1279 ptrs
[0] = MakeTsbPtr(Ps0
, tag_access
,
1280 tc
->readMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS0
),
1281 tc
->readMiscReg(MISCREG_MMU_DTLB_C0_CONFIG
),
1282 tc
->readMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS0
),
1283 tc
->readMiscReg(MISCREG_MMU_DTLB_CX_CONFIG
));
1284 ptrs
[1] = MakeTsbPtr(Ps1
, tag_access
,
1285 tc
->readMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS1
),
1286 tc
->readMiscReg(MISCREG_MMU_DTLB_C0_CONFIG
),
1287 tc
->readMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS1
),
1288 tc
->readMiscReg(MISCREG_MMU_DTLB_CX_CONFIG
));
1289 ptrs
[2] = MakeTsbPtr(Ps0
, tag_access
,
1290 tc
->readMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS0
),
1291 tc
->readMiscReg(MISCREG_MMU_ITLB_C0_CONFIG
),
1292 tc
->readMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS0
),
1293 tc
->readMiscReg(MISCREG_MMU_ITLB_CX_CONFIG
));
1294 ptrs
[3] = MakeTsbPtr(Ps1
, tag_access
,
1295 tc
->readMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS1
),
1296 tc
->readMiscReg(MISCREG_MMU_ITLB_C0_CONFIG
),
1297 tc
->readMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS1
),
1298 tc
->readMiscReg(MISCREG_MMU_ITLB_CX_CONFIG
));
1306 DTB::MakeTsbPtr(TsbPageSize ps
, uint64_t tag_access
, uint64_t c0_tsb
,
1307 uint64_t c0_config
, uint64_t cX_tsb
, uint64_t cX_config
)
1312 if (bits(tag_access
, 12,0) == 0) {
1320 uint64_t ptr
= mbits(tsb
,63,13);
1321 bool split
= bits(tsb
,12,12);
1322 int tsb_size
= bits(tsb
,3,0);
1323 int page_size
= (ps
== Ps0
) ? bits(config
, 2,0) : bits(config
,10,8);
1325 if (ps
== Ps1
&& split
)
1326 ptr
|= ULL(1) << (13 + tsb_size
);
1327 ptr
|= (tag_access
>> (9 + page_size
* 3)) & mask(12+tsb_size
, 4);
1334 TLB::serialize(std::ostream
&os
)
1336 SERIALIZE_SCALAR(size
);
1337 SERIALIZE_SCALAR(usedEntries
);
1338 SERIALIZE_SCALAR(lastReplaced
);
1340 // convert the pointer based free list into an index based one
1341 int *free_list
= (int*)malloc(sizeof(int) * size
);
1343 std::list
<TlbEntry
*>::iterator i
;
1344 i
= freeList
.begin();
1345 while (i
!= freeList
.end()) {
1346 free_list
[cntr
++] = ((size_t)*i
- (size_t)tlb
)/ sizeof(TlbEntry
);
1349 SERIALIZE_SCALAR(cntr
);
1350 SERIALIZE_ARRAY(free_list
, cntr
);
1352 for (int x
= 0; x
< size
; x
++) {
1353 nameOut(os
, csprintf("%s.PTE%d", name(), x
));
1354 tlb
[x
].serialize(os
);
1359 TLB::unserialize(Checkpoint
*cp
, const std::string
§ion
)
1363 paramIn(cp
, section
, "size", oldSize
);
1364 if (oldSize
!= size
)
1365 panic("Don't support unserializing different sized TLBs\n");
1366 UNSERIALIZE_SCALAR(usedEntries
);
1367 UNSERIALIZE_SCALAR(lastReplaced
);
1370 UNSERIALIZE_SCALAR(cntr
);
1372 int *free_list
= (int*)malloc(sizeof(int) * cntr
);
1374 UNSERIALIZE_ARRAY(free_list
, cntr
);
1375 for (int x
= 0; x
< cntr
; x
++)
1376 freeList
.push_back(&tlb
[free_list
[x
]]);
1378 lookupTable
.clear();
1379 for (int x
= 0; x
< size
; x
++) {
1380 tlb
[x
].unserialize(cp
, csprintf("%s.PTE%d", section
, x
));
1382 lookupTable
.insert(tlb
[x
].range
, &tlb
[x
]);
1387 /* end namespace SparcISA */ }
1389 using namespace SparcISA
;
1391 DEFINE_SIM_OBJECT_CLASS_NAME("SparcTLB", TLB
)
1393 BEGIN_DECLARE_SIM_OBJECT_PARAMS(ITB
)
1397 END_DECLARE_SIM_OBJECT_PARAMS(ITB
)
1399 BEGIN_INIT_SIM_OBJECT_PARAMS(ITB
)
1401 INIT_PARAM_DFLT(size
, "TLB size", 48)
1403 END_INIT_SIM_OBJECT_PARAMS(ITB
)
1406 CREATE_SIM_OBJECT(ITB
)
1408 return new ITB(getInstanceName(), size
);
1411 REGISTER_SIM_OBJECT("SparcITB", ITB
)
1413 BEGIN_DECLARE_SIM_OBJECT_PARAMS(DTB
)
1417 END_DECLARE_SIM_OBJECT_PARAMS(DTB
)
1419 BEGIN_INIT_SIM_OBJECT_PARAMS(DTB
)
1421 INIT_PARAM_DFLT(size
, "TLB size", 64)
1423 END_INIT_SIM_OBJECT_PARAMS(DTB
)
1426 CREATE_SIM_OBJECT(DTB
)
1428 return new DTB(getInstanceName(), size
);
1431 REGISTER_SIM_OBJECT("SparcDTB", DTB
)