src/arch/sparc/tlb.cc

   1 /*
   2  * Copyright (c) 2001-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Ali Saidi
  29  */
  30
  31 #include "arch/sparc/asi.hh"
  32 #include "arch/sparc/miscregfile.hh"
  33 #include "arch/sparc/tlb.hh"
  34 #include "base/bitfield.hh"
  35 #include "base/trace.hh"
  36 #include "cpu/thread_context.hh"
  37 #include "cpu/base.hh"
  38 #include "mem/packet_access.hh"
  39 #include "mem/request.hh"
  40 #include "sim/builder.hh"
  41
  42 /* @todo remove some of the magic constants.  -- ali
  43  * */
  44 namespace SparcISA
  45 {
  46
  47 TLB::TLB(const std::string &name, int s)
  48     : SimObject(name), size(s), usedEntries(0), lastReplaced(0),
  49       cacheValid(false)
  50 {
  51     // To make this work you'll have to change the hypervisor and OS
  52     if (size > 64)
  53         fatal("SPARC T1 TLB registers don't support more than 64 TLB entries.");
  54
  55     tlb = new TlbEntry[size];
  56     memset(tlb, 0, sizeof(TlbEntry) * size);
  57
  58     for (int x = 0; x < size; x++)
  59         freeList.push_back(&tlb[x]);
  60 }
  61
  62 void
  63 TLB::clearUsedBits()
  64 {
  65     MapIter i;
  66     for (i = lookupTable.begin(); i != lookupTable.end(); i++) {
  67         TlbEntry *t = i->second;
  68         if (!t->pte.locked()) {
  69             t->used = false;
  70             usedEntries--;
  71         }
  72     }
  73 }
  74
  75
  76 void
  77 TLB::insert(Addr va, int partition_id, int context_id, bool real,
  78         const PageTableEntry& PTE, int entry)
  79 {
  80
  81
  82     MapIter i;
  83     TlbEntry *new_entry = NULL;
  84 //    TlbRange tr;
  85     int x;
  86
  87     cacheValid = false;
  88     va &= ~(PTE.size()-1);
  89  /*   tr.va = va;
  90     tr.size = PTE.size() - 1;
  91     tr.contextId = context_id;
  92     tr.partitionId = partition_id;
  93     tr.real = real;
  94 */
  95
  96     DPRINTF(TLB, "TLB: Inserting TLB Entry; va=%#x pa=%#x pid=%d cid=%d r=%d entryid=%d\n",
  97             va, PTE.paddr(), partition_id, context_id, (int)real, entry);
  98
  99     // Demap any entry that conflicts
 100     for (x = 0; x < size; x++) {
 101         if (tlb[x].range.real == real &&
 102             tlb[x].range.partitionId == partition_id &&
 103             tlb[x].range.va < va + PTE.size() - 1 &&
 104             tlb[x].range.va + tlb[x].range.size >= va &&
 105             (real || tlb[x].range.contextId == context_id ))
 106         {
 107             if (tlb[x].valid) {
 108                 freeList.push_front(&tlb[x]);
 109                 DPRINTF(TLB, "TLB: Conflicting entry %#X , deleting it\n", x);
 110
 111                 tlb[x].valid = false;
 112                 if (tlb[x].used) {
 113                     tlb[x].used = false;
 114                     usedEntries--;
 115                 }
 116                 lookupTable.erase(tlb[x].range);
 117             }
 118         }
 119     }
 120
 121
 122 /*
 123     i = lookupTable.find(tr);
 124     if (i != lookupTable.end()) {
 125         i->second->valid = false;
 126         if (i->second->used) {
 127             i->second->used = false;
 128             usedEntries--;
 129         }
 130         freeList.push_front(i->second);
 131         DPRINTF(TLB, "TLB: Found conflicting entry %#X , deleting it\n",
 132                 i->second);
 133         lookupTable.erase(i);
 134     }
 135 */
 136
 137     if (entry != -1) {
 138         assert(entry < size && entry >= 0);
 139         new_entry = &tlb[entry];
 140     } else {
 141         if (!freeList.empty()) {
 142             new_entry = freeList.front();
 143         } else {
 144             x = lastReplaced;
 145             do {
 146                 ++x;
 147                 if (x == size)
 148                     x = 0;
 149                 if (x == lastReplaced)
 150                     goto insertAllLocked;
 151             } while (tlb[x].pte.locked());
 152             lastReplaced = x;
 153             new_entry = &tlb[x];
 154         }
 155         /*
 156         for (x = 0; x < size; x++) {
 157             if (!tlb[x].valid || !tlb[x].used)  {
 158                 new_entry = &tlb[x];
 159                 break;
 160             }
 161         }*/
 162     }
 163
 164 insertAllLocked:
 165     // Update the last ently if their all locked
 166     if (!new_entry) {
 167         new_entry = &tlb[size-1];
 168     }
 169
 170     freeList.remove(new_entry);
 171     if (new_entry->valid && new_entry->used)
 172         usedEntries--;
 173
 174     lookupTable.erase(new_entry->range);
 175
 176
 177     DPRINTF(TLB, "Using entry: %#X\n", new_entry);
 178
 179     assert(PTE.valid());
 180     new_entry->range.va = va;
 181     new_entry->range.size = PTE.size() - 1;
 182     new_entry->range.partitionId = partition_id;
 183     new_entry->range.contextId = context_id;
 184     new_entry->range.real = real;
 185     new_entry->pte = PTE;
 186     new_entry->used = true;;
 187     new_entry->valid = true;
 188     usedEntries++;
 189
 190
 191
 192     i = lookupTable.insert(new_entry->range, new_entry);
 193     assert(i != lookupTable.end());
 194
 195     // If all entries have there used bit set, clear it on them all, but the
 196     // one we just inserted
 197     if (usedEntries == size) {
 198         clearUsedBits();
 199         new_entry->used = true;
 200         usedEntries++;
 201     }
 202
 203 }
 204
 205
 206 TlbEntry*
 207 TLB::lookup(Addr va, int partition_id, bool real, int context_id)
 208 {
 209     MapIter i;
 210     TlbRange tr;
 211     TlbEntry *t;
 212
 213     DPRINTF(TLB, "TLB: Looking up entry va=%#x pid=%d cid=%d r=%d\n",
 214             va, partition_id, context_id, real);
 215     // Assemble full address structure
 216     tr.va = va;
 217     tr.size = MachineBytes;
 218     tr.contextId = context_id;
 219     tr.partitionId = partition_id;
 220     tr.real = real;
 221
 222     // Try to find the entry
 223     i = lookupTable.find(tr);
 224     if (i == lookupTable.end()) {
 225         DPRINTF(TLB, "TLB: No valid entry found\n");
 226         return NULL;
 227     }
 228
 229     // Mark the entries used bit and clear other used bits in needed
 230     t = i->second;
 231     DPRINTF(TLB, "TLB: Valid entry found pa: %#x size: %#x\n", t->pte.paddr(),
 232             t->pte.size());
 233     if (!t->used) {
 234         t->used = true;
 235         usedEntries++;
 236         if (usedEntries == size) {
 237             clearUsedBits();
 238             t->used = true;
 239             usedEntries++;
 240         }
 241     }
 242
 243     return t;
 244 }
 245
 246 void
 247 TLB::dumpAll()
 248 {
 249     MapIter i;
 250     for (int x = 0; x < size; x++) {
 251         if (tlb[x].valid) {
 252            DPRINTFN("%4d:  %#2x:%#2x %c %#4x %#8x %#8x %#16x\n",
 253                    x, tlb[x].range.partitionId, tlb[x].range.contextId,
 254                    tlb[x].range.real ? 'R' : ' ', tlb[x].range.size,
 255                    tlb[x].range.va, tlb[x].pte.paddr(), tlb[x].pte());
 256         }
 257     }
 258 }
 259
 260 void
 261 TLB::demapPage(Addr va, int partition_id, bool real, int context_id)
 262 {
 263     TlbRange tr;
 264     MapIter i;
 265
 266     DPRINTF(IPR, "TLB: Demapping Page va=%#x pid=%#d cid=%d r=%d\n",
 267             va, partition_id, context_id, real);
 268
 269     cacheValid = false;
 270
 271     // Assemble full address structure
 272     tr.va = va;
 273     tr.size = MachineBytes;
 274     tr.contextId = context_id;
 275     tr.partitionId = partition_id;
 276     tr.real = real;
 277
 278     // Demap any entry that conflicts
 279     i = lookupTable.find(tr);
 280     if (i != lookupTable.end()) {
 281         DPRINTF(IPR, "TLB: Demapped page\n");
 282         i->second->valid = false;
 283         if (i->second->used) {
 284             i->second->used = false;
 285             usedEntries--;
 286         }
 287         freeList.push_front(i->second);
 288         DPRINTF(TLB, "Freeing TLB entry : %#X\n", i->second);
 289         lookupTable.erase(i);
 290     }
 291 }
 292
 293 void
 294 TLB::demapContext(int partition_id, int context_id)
 295 {
 296     int x;
 297     DPRINTF(IPR, "TLB: Demapping Context pid=%#d cid=%d\n",
 298             partition_id, context_id);
 299     cacheValid = false;
 300     for (x = 0; x < size; x++) {
 301         if (tlb[x].range.contextId == context_id &&
 302             tlb[x].range.partitionId == partition_id) {
 303             if (tlb[x].valid == true) {
 304                 freeList.push_front(&tlb[x]);
 305                 DPRINTF(TLB, "Freeing TLB entry : %#X\n", &tlb[x]);
 306             }
 307             tlb[x].valid = false;
 308             if (tlb[x].used) {
 309                 tlb[x].used = false;
 310                 usedEntries--;
 311             }
 312             lookupTable.erase(tlb[x].range);
 313         }
 314     }
 315 }
 316
 317 void
 318 TLB::demapAll(int partition_id)
 319 {
 320     int x;
 321     DPRINTF(TLB, "TLB: Demapping All pid=%#d\n", partition_id);
 322     cacheValid = false;
 323     for (x = 0; x < size; x++) {
 324         if (!tlb[x].pte.locked() && tlb[x].range.partitionId == partition_id) {
 325             if (tlb[x].valid == true){
 326                 freeList.push_front(&tlb[x]);
 327                 DPRINTF(TLB, "Freeing TLB entry : %#X\n", &tlb[x]);
 328             }
 329             tlb[x].valid = false;
 330             if (tlb[x].used) {
 331                 tlb[x].used = false;
 332                 usedEntries--;
 333             }
 334             lookupTable.erase(tlb[x].range);
 335         }
 336     }
 337 }
 338
 339 void
 340 TLB::invalidateAll()
 341 {
 342     int x;
 343     cacheValid = false;
 344
 345     freeList.clear();
 346     lookupTable.clear();
 347     for (x = 0; x < size; x++) {
 348         if (tlb[x].valid == true)
 349             freeList.push_back(&tlb[x]);
 350         tlb[x].valid = false;
 351         tlb[x].used = false;
 352     }
 353     usedEntries = 0;
 354 }
 355
 356 uint64_t
 357 TLB::TteRead(int entry) {
 358     if (entry >= size)
 359         panic("entry: %d\n", entry);
 360
 361     assert(entry < size);
 362     if (tlb[entry].valid)
 363         return tlb[entry].pte();
 364     else
 365         return (uint64_t)-1ll;
 366 }
 367
 368 uint64_t
 369 TLB::TagRead(int entry) {
 370     assert(entry < size);
 371     uint64_t tag;
 372     if (!tlb[entry].valid)
 373         return (uint64_t)-1ll;
 374
 375     tag = tlb[entry].range.contextId;
 376     tag |= tlb[entry].range.va;
 377     tag |= (uint64_t)tlb[entry].range.partitionId << 61;
 378     tag |= tlb[entry].range.real ? ULL(1) << 60 : 0;
 379     tag |= (uint64_t)~tlb[entry].pte._size() << 56;
 380     return tag;
 381 }
 382
 383 bool
 384 TLB::validVirtualAddress(Addr va, bool am)
 385 {
 386     if (am)
 387         return true;
 388     if (va >= StartVAddrHole && va <= EndVAddrHole)
 389         return false;
 390     return true;
 391 }
 392
 393 void
 394 TLB::writeSfsr(ThreadContext *tc, int reg,  bool write, ContextType ct,
 395         bool se, FaultTypes ft, int asi)
 396 {
 397     uint64_t sfsr;
 398     sfsr = tc->readMiscReg(reg);
 399
 400     if (sfsr & 0x1)
 401         sfsr = 0x3;
 402     else
 403         sfsr = 1;
 404
 405     if (write)
 406         sfsr |= 1 << 2;
 407     sfsr |= ct << 4;
 408     if (se)
 409         sfsr |= 1 << 6;
 410     sfsr |= ft << 7;
 411     sfsr |= asi << 16;
 412     tc->setMiscRegWithEffect(reg, sfsr);
 413 }
 414
 415 void
 416 TLB::writeTagAccess(ThreadContext *tc, int reg, Addr va, int context)
 417 {
 418     DPRINTF(TLB, "TLB: Writing Tag Access: va: %#X ctx: %#X value: %#X\n",
 419             va, context, mbits(va, 63,13) | mbits(context,12,0));
 420
 421     tc->setMiscRegWithEffect(reg, mbits(va, 63,13) | mbits(context,12,0));
 422 }
 423
 424 void
 425 ITB::writeSfsr(ThreadContext *tc, bool write, ContextType ct,
 426         bool se, FaultTypes ft, int asi)
 427 {
 428     DPRINTF(TLB, "TLB: ITB Fault:  w=%d ct=%d ft=%d asi=%d\n",
 429              (int)write, ct, ft, asi);
 430     TLB::writeSfsr(tc, MISCREG_MMU_ITLB_SFSR, write, ct, se, ft, asi);
 431 }
 432
 433 void
 434 ITB::writeTagAccess(ThreadContext *tc, Addr va, int context)
 435 {
 436     TLB::writeTagAccess(tc, MISCREG_MMU_ITLB_TAG_ACCESS, va, context);
 437 }
 438
 439 void
 440 DTB::writeSfr(ThreadContext *tc, Addr a, bool write, ContextType ct,
 441         bool se, FaultTypes ft, int asi)
 442 {
 443     DPRINTF(TLB, "TLB: DTB Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n",
 444             a, (int)write, ct, ft, asi);
 445     TLB::writeSfsr(tc, MISCREG_MMU_DTLB_SFSR, write, ct, se, ft, asi);
 446     tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_SFAR, a);
 447 }
 448
 449 void
 450 DTB::writeTagAccess(ThreadContext *tc, Addr va, int context)
 451 {
 452     TLB::writeTagAccess(tc, MISCREG_MMU_DTLB_TAG_ACCESS, va, context);
 453 }
 454
 455
 456
 457 Fault
 458 ITB::translate(RequestPtr &req, ThreadContext *tc)
 459 {
 460     uint64_t tlbdata = tc->readMiscReg(MISCREG_TLB_DATA);
 461
 462     Addr vaddr = req->getVaddr();
 463     TlbEntry *e;
 464
 465     assert(req->getAsi() == ASI_IMPLICIT);
 466
 467     DPRINTF(TLB, "TLB: ITB Request to translate va=%#x size=%d\n",
 468             vaddr, req->getSize());
 469
 470     // Be fast if we can!
 471     if (cacheValid && cacheState == tlbdata) {
 472         if (cacheEntry) {
 473             if (cacheEntry->range.va < vaddr + sizeof(MachInst) &&
 474                 cacheEntry->range.va + cacheEntry->range.size >= vaddr) {
 475                     req->setPaddr(cacheEntry->pte.paddr() & ~(cacheEntry->pte.size()-1) |
 476                                   vaddr & cacheEntry->pte.size()-1 );
 477                     return NoFault;
 478             }
 479         } else {
 480             req->setPaddr(vaddr & PAddrImplMask);
 481             return NoFault;
 482         }
 483     }
 484
 485     bool hpriv = bits(tlbdata,0,0);
 486     bool red = bits(tlbdata,1,1);
 487     bool priv = bits(tlbdata,2,2);
 488     bool addr_mask = bits(tlbdata,3,3);
 489     bool lsu_im = bits(tlbdata,4,4);
 490
 491     int part_id = bits(tlbdata,15,8);
 492     int tl = bits(tlbdata,18,16);
 493     int pri_context = bits(tlbdata,47,32);
 494     int context;
 495     ContextType ct;
 496     int asi;
 497     bool real = false;
 498
 499     DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsuim:%d part_id: %#X\n",
 500            priv, hpriv, red, lsu_im, part_id);
 501
 502     if (tl > 0) {
 503         asi = ASI_N;
 504         ct = Nucleus;
 505         context = 0;
 506     } else {
 507         asi = ASI_P;
 508         ct = Primary;
 509         context = pri_context;
 510     }
 511
 512     if ( hpriv || red ) {
 513         cacheValid = true;
 514         cacheState = tlbdata;
 515         cacheEntry = NULL;
 516         req->setPaddr(vaddr & PAddrImplMask);
 517         return NoFault;
 518     }
 519
 520     // If the access is unaligned trap
 521     if (vaddr & 0x3) {
 522         writeSfsr(tc, false, ct, false, OtherFault, asi);
 523         return new MemAddressNotAligned;
 524     }
 525
 526     if (addr_mask)
 527         vaddr = vaddr & VAddrAMask;
 528
 529     if (!validVirtualAddress(vaddr, addr_mask)) {
 530         writeSfsr(tc, false, ct, false, VaOutOfRange, asi);
 531         return new InstructionAccessException;
 532     }
 533
 534     if (!lsu_im) {
 535         e = lookup(vaddr, part_id, true);
 536         real = true;
 537         context = 0;
 538     } else {
 539         e = lookup(vaddr, part_id, false, context);
 540     }
 541
 542     if (e == NULL || !e->valid) {
 543         writeTagAccess(tc, vaddr, context);
 544         if (real)
 545             return new InstructionRealTranslationMiss;
 546         else
 547             return new FastInstructionAccessMMUMiss;
 548     }
 549
 550     // were not priviledged accesing priv page
 551     if (!priv && e->pte.priv()) {
 552         writeSfsr(tc, false, ct, false, PrivViolation, asi);
 553         return new InstructionAccessException;
 554     }
 555
 556     // cache translation date for next translation
 557     cacheValid = true;
 558     cacheState = tlbdata;
 559     cacheEntry = e;
 560
 561     req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) |
 562                   vaddr & e->pte.size()-1 );
 563     DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
 564     return NoFault;
 565 }
 566
 567
 568
 569 Fault
 570 DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
 571 {
 572     /* @todo this could really use some profiling and fixing to make it faster! */
 573     uint64_t tlbdata = tc->readMiscReg(MISCREG_TLB_DATA);
 574     Addr vaddr = req->getVaddr();
 575     Addr size = req->getSize();
 576     ASI asi;
 577     asi = (ASI)req->getAsi();
 578     bool implicit = false;
 579     bool hpriv = bits(tlbdata,0,0);
 580
 581     DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n",
 582             vaddr, size, asi);
 583
 584     if (asi == ASI_IMPLICIT)
 585         implicit = true;
 586
 587     if (hpriv && implicit) {
 588         req->setPaddr(vaddr & PAddrImplMask);
 589         return NoFault;
 590     }
 591
 592     // Be fast if we can!
 593     if (cacheValid &&  cacheState == tlbdata) {
 594         if (cacheEntry[0] && cacheAsi[0] == asi && cacheEntry[0]->range.va < vaddr + size &&
 595             cacheEntry[0]->range.va + cacheEntry[0]->range.size > vaddr) {
 596                 req->setPaddr(cacheEntry[0]->pte.paddr() & ~(cacheEntry[0]->pte.size()-1) |
 597                               vaddr & cacheEntry[0]->pte.size()-1 );
 598                 return NoFault;
 599         }
 600         if (cacheEntry[1] && cacheAsi[1] == asi && cacheEntry[1]->range.va < vaddr + size &&
 601             cacheEntry[1]->range.va + cacheEntry[1]->range.size > vaddr) {
 602                 req->setPaddr(cacheEntry[1]->pte.paddr() & ~(cacheEntry[1]->pte.size()-1) |
 603                               vaddr & cacheEntry[1]->pte.size()-1 );
 604                 return NoFault;
 605         }
 606     }
 607
 608     bool red = bits(tlbdata,1,1);
 609     bool priv = bits(tlbdata,2,2);
 610     bool addr_mask = bits(tlbdata,3,3);
 611     bool lsu_dm = bits(tlbdata,5,5);
 612
 613     int part_id = bits(tlbdata,15,8);
 614     int tl = bits(tlbdata,18,16);
 615     int pri_context = bits(tlbdata,47,32);
 616     int sec_context = bits(tlbdata,63,48);
 617
 618     bool real = false;
 619     ContextType ct = Primary;
 620     int context = 0;
 621
 622     TlbEntry *e;
 623
 624     DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsudm:%d part_id: %#X\n",
 625            priv, hpriv, red, lsu_dm, part_id);
 626
 627     if (implicit) {
 628         if (tl > 0) {
 629             asi = ASI_N;
 630             ct = Nucleus;
 631             context = 0;
 632         } else {
 633             asi = ASI_P;
 634             ct = Primary;
 635             context = pri_context;
 636         }
 637     } else {
 638         // We need to check for priv level/asi priv
 639         if (!priv && !hpriv && !AsiIsUnPriv(asi)) {
 640             // It appears that context should be Nucleus in these cases?
 641             writeSfr(tc, vaddr, write, Nucleus, false, IllegalAsi, asi);
 642             return new PrivilegedAction;
 643         }
 644
 645         if (!hpriv && AsiIsHPriv(asi)) {
 646             writeSfr(tc, vaddr, write, Nucleus, false, IllegalAsi, asi);
 647             return new DataAccessException;
 648         }
 649
 650         if (AsiIsPrimary(asi)) {
 651             context = pri_context;
 652             ct = Primary;
 653         } else if (AsiIsSecondary(asi)) {
 654             context = sec_context;
 655             ct = Secondary;
 656         } else if (AsiIsNucleus(asi)) {
 657             ct = Nucleus;
 658             context = 0;
 659         } else {  // ????
 660             ct = Primary;
 661             context = pri_context;
 662         }
 663     }
 664
 665     if (!implicit && asi != ASI_P && asi != ASI_S) {
 666         if (AsiIsLittle(asi))
 667             panic("Little Endian ASIs not supported\n");
 668         if (AsiIsBlock(asi))
 669             panic("Block ASIs not supported\n");
 670         if (AsiIsNoFault(asi))
 671             panic("No Fault ASIs not supported\n");
 672
 673         if (AsiIsPartialStore(asi))
 674             panic("Partial Store ASIs not supported\n");
 675         if (AsiIsInterrupt(asi))
 676             panic("Interrupt ASIs not supported\n");
 677
 678         if (AsiIsMmu(asi))
 679             goto handleMmuRegAccess;
 680         if (AsiIsScratchPad(asi))
 681             goto handleScratchRegAccess;
 682         if (AsiIsQueue(asi))
 683             goto handleQueueRegAccess;
 684         if (AsiIsSparcError(asi))
 685             goto handleSparcErrorRegAccess;
 686
 687         if (!AsiIsReal(asi) && !AsiIsNucleus(asi) && !AsiIsAsIfUser(asi) &&
 688                 !AsiIsTwin(asi))
 689             panic("Accessing ASI %#X. Should we?\n", asi);
 690     }
 691
 692     // If the asi is unaligned trap
 693     if (vaddr & size-1) {
 694         writeSfr(tc, vaddr, false, ct, false, OtherFault, asi);
 695         return new MemAddressNotAligned;
 696     }
 697
 698     if (addr_mask)
 699         vaddr = vaddr & VAddrAMask;
 700
 701     if (!validVirtualAddress(vaddr, addr_mask)) {
 702         writeSfr(tc, vaddr, false, ct, true, VaOutOfRange, asi);
 703         return new DataAccessException;
 704     }
 705
 706
 707     if ((!lsu_dm && !hpriv && !red) || AsiIsReal(asi)) {
 708         real = true;
 709         context = 0;
 710     };
 711
 712     if (hpriv && (implicit || (!AsiIsAsIfUser(asi) && !AsiIsReal(asi)))) {
 713         req->setPaddr(vaddr & PAddrImplMask);
 714         return NoFault;
 715     }
 716
 717     e = lookup(vaddr, part_id, real, context);
 718
 719     if (e == NULL || !e->valid) {
 720         writeTagAccess(tc, vaddr, context);
 721         DPRINTF(TLB, "TLB: DTB Failed to find matching TLB entry\n");
 722         if (real)
 723             return new DataRealTranslationMiss;
 724         else
 725             return new FastDataAccessMMUMiss;
 726
 727     }
 728
 729
 730     if (write && !e->pte.writable()) {
 731         writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), OtherFault, asi);
 732         return new FastDataAccessProtection;
 733     }
 734
 735     if (e->pte.nofault() && !AsiIsNoFault(asi)) {
 736         writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), LoadFromNfo, asi);
 737         return new DataAccessException;
 738     }
 739
 740     if (e->pte.sideffect())
 741         req->setFlags(req->getFlags() | UNCACHEABLE);
 742
 743
 744     if (!priv && e->pte.priv()) {
 745         writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), PrivViolation, asi);
 746         return new DataAccessException;
 747     }
 748
 749     // cache translation date for next translation
 750     cacheState = tlbdata;
 751     if (!cacheValid) {
 752         cacheEntry[1] = NULL;
 753         cacheEntry[0] = NULL;
 754     }
 755
 756     if (cacheEntry[0] != e && cacheEntry[1] != e) {
 757         cacheEntry[1] = cacheEntry[0];
 758         cacheEntry[0] = e;
 759         cacheAsi[1] = cacheAsi[0];
 760         cacheAsi[0] = asi;
 761         if (implicit)
 762             cacheAsi[0] = (ASI)0;
 763     }
 764     cacheValid = true;
 765     req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) |
 766                   vaddr & e->pte.size()-1);
 767     DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
 768     return NoFault;
 769     /** Normal flow ends here. */
 770
 771 handleScratchRegAccess:
 772     if (vaddr > 0x38 || (vaddr >= 0x20 && vaddr < 0x30 && !hpriv)) {
 773         writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
 774         return new DataAccessException;
 775     }
 776     goto regAccessOk;
 777
 778 handleQueueRegAccess:
 779     if (!priv  && !hpriv) {
 780         writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
 781         return new PrivilegedAction;
 782     }
 783     if (!hpriv && vaddr & 0xF || vaddr > 0x3f8 || vaddr < 0x3c0) {
 784         writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
 785         return new DataAccessException;
 786     }
 787     goto regAccessOk;
 788
 789 handleSparcErrorRegAccess:
 790     if (!hpriv) {
 791         if (priv) {
 792             writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
 793             return new DataAccessException;
 794         } else {
 795             writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
 796             return new PrivilegedAction;
 797         }
 798     }
 799     goto regAccessOk;
 800
 801
 802 regAccessOk:
 803 handleMmuRegAccess:
 804     DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n");
 805     req->setMmapedIpr(true);
 806     req->setPaddr(req->getVaddr());
 807     return NoFault;
 808 };
 809
 810 Tick
 811 DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
 812 {
 813     Addr va = pkt->getAddr();
 814     ASI asi = (ASI)pkt->req->getAsi();
 815     uint64_t temp, data;
 816     uint64_t tsbtemp, cnftemp;
 817
 818     DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n",
 819          (uint32_t)pkt->req->getAsi(), pkt->getAddr());
 820
 821     switch (asi) {
 822       case ASI_LSU_CONTROL_REG:
 823         assert(va == 0);
 824         pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_LSU_CTRL));
 825         break;
 826       case ASI_MMU:
 827         switch (va) {
 828           case 0x8:
 829             pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT));
 830             break;
 831           case 0x10:
 832             pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_S_CONTEXT));
 833             break;
 834           default:
 835             goto doMmuReadError;
 836         }
 837         break;
 838       case ASI_QUEUE:
 839         pkt->set(tc->readMiscRegWithEffect(MISCREG_QUEUE_CPU_MONDO_HEAD +
 840                     (va >> 4) - 0x3c));
 841         break;
 842       case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0:
 843         assert(va == 0);
 844         pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0));
 845         break;
 846       case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1:
 847         assert(va == 0);
 848         pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1));
 849         break;
 850       case ASI_DMMU_CTXT_ZERO_CONFIG:
 851         assert(va == 0);
 852         pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG));
 853         break;
 854       case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0:
 855         assert(va == 0);
 856         pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0));
 857         break;
 858       case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1:
 859         assert(va == 0);
 860         pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1));
 861         break;
 862       case ASI_IMMU_CTXT_ZERO_CONFIG:
 863         assert(va == 0);
 864         pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG));
 865         break;
 866       case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0:
 867         assert(va == 0);
 868         pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0));
 869         break;
 870       case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1:
 871         assert(va == 0);
 872         pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1));
 873         break;
 874       case ASI_DMMU_CTXT_NONZERO_CONFIG:
 875         assert(va == 0);
 876         pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG));
 877         break;
 878       case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0:
 879         assert(va == 0);
 880         pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0));
 881         break;
 882       case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1:
 883         assert(va == 0);
 884         pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1));
 885         break;
 886       case ASI_IMMU_CTXT_NONZERO_CONFIG:
 887         assert(va == 0);
 888         pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG));
 889         break;
 890       case ASI_SPARC_ERROR_STATUS_REG:
 891         warn("returning 0 for  SPARC ERROR regsiter read\n");
 892         pkt->set((uint64_t)0);
 893         break;
 894       case ASI_HYP_SCRATCHPAD:
 895       case ASI_SCRATCHPAD:
 896         pkt->set(tc->readMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3)));
 897         break;
 898       case ASI_IMMU:
 899         switch (va) {
 900           case 0x0:
 901             temp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS);
 902             pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48);
 903             break;
 904           case 0x18:
 905             pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_SFSR));
 906             break;
 907           case 0x30:
 908             pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS));
 909             break;
 910           default:
 911             goto doMmuReadError;
 912         }
 913         break;
 914       case ASI_DMMU:
 915         switch (va) {
 916           case 0x0:
 917             temp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS);
 918             pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48);
 919             break;
 920           case 0x18:
 921             pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_SFSR));
 922             break;
 923           case 0x20:
 924             pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_SFAR));
 925             break;
 926           case 0x30:
 927             pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS));
 928             break;
 929           case 0x80:
 930             pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID));
 931             break;
 932           default:
 933                 goto doMmuReadError;
 934         }
 935         break;
 936       case ASI_DMMU_TSB_PS0_PTR_REG:
 937         temp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS);
 938         if (bits(temp,12,0) == 0) {
 939             tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0);
 940             cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG);
 941         } else {
 942             tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0);
 943             cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG);
 944         }
 945         data = mbits(tsbtemp,63,13);
 946         data |= temp >> (9 + bits(cnftemp,2,0) * 3) &
 947             mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4);
 948         pkt->set(data);
 949         break;
 950       case ASI_DMMU_TSB_PS1_PTR_REG:
 951         temp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS);
 952         if (bits(temp,12,0) == 0) {
 953             tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1);
 954             cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG);
 955         } else {
 956             tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1);
 957             cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG);
 958         }
 959         data = mbits(tsbtemp,63,13);
 960         if (bits(tsbtemp,12,12))
 961             data |= ULL(1) << (13+bits(tsbtemp,3,0));
 962         data |= temp >> (9 + bits(cnftemp,10,8) * 3) &
 963             mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4);
 964         pkt->set(data);
 965         break;
 966       case ASI_IMMU_TSB_PS0_PTR_REG:
 967         temp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS);
 968         if (bits(temp,12,0) == 0) {
 969             tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0);
 970             cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG);
 971         } else {
 972             tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0);
 973             cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG);
 974         }
 975         data = mbits(tsbtemp,63,13);
 976         data |= temp >> (9 + bits(cnftemp,2,0) * 3) &
 977             mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4);
 978         pkt->set(data);
 979         break;
 980       case ASI_IMMU_TSB_PS1_PTR_REG:
 981         temp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS);
 982         if (bits(temp,12,0) == 0) {
 983             tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1);
 984             cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG);
 985         } else {
 986             tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1);
 987             cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG);
 988         }
 989         data = mbits(tsbtemp,63,13);
 990         if (bits(tsbtemp,12,12))
 991             data |= ULL(1) << (13+bits(tsbtemp,3,0));
 992         data |= temp >> (9 + bits(cnftemp,10,8) * 3) &
 993             mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4);
 994         pkt->set(data);
 995         break;
 996
 997       default:
 998 doMmuReadError:
 999         panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n",
1000             (uint32_t)asi, va);
1001     }
1002     pkt->result = Packet::Success;
1003     return tc->getCpuPtr()->cycles(1);
1004 }
1005
1006 Tick
1007 DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
1008 {
1009     uint64_t data = gtoh(pkt->get<uint64_t>());
1010     Addr va = pkt->getAddr();
1011     ASI asi = (ASI)pkt->req->getAsi();
1012
1013     Addr ta_insert;
1014     Addr va_insert;
1015     Addr ct_insert;
1016     int part_insert;
1017     int entry_insert = -1;
1018     bool real_insert;
1019     bool ignore;
1020     int part_id;
1021     int ctx_id;
1022     PageTableEntry pte;
1023
1024     DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n",
1025          (uint32_t)asi, va, data);
1026
1027     switch (asi) {
1028       case ASI_LSU_CONTROL_REG:
1029         assert(va == 0);
1030         tc->setMiscRegWithEffect(MISCREG_MMU_LSU_CTRL, data);
1031         break;
1032       case ASI_MMU:
1033         switch (va) {
1034           case 0x8:
1035             tc->setMiscRegWithEffect(MISCREG_MMU_P_CONTEXT, data);
1036             break;
1037           case 0x10:
1038             tc->setMiscRegWithEffect(MISCREG_MMU_S_CONTEXT, data);
1039             break;
1040           default:
1041             goto doMmuWriteError;
1042         }
1043         break;
1044       case ASI_QUEUE:
1045         assert(mbits(data,13,6) == data);
1046         tc->setMiscRegWithEffect(MISCREG_QUEUE_CPU_MONDO_HEAD +
1047                     (va >> 4) - 0x3c, data);
1048         break;
1049       case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0:
1050         assert(va == 0);
1051         tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0, data);
1052         break;
1053       case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1:
1054         assert(va == 0);
1055         tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1, data);
1056         break;
1057       case ASI_DMMU_CTXT_ZERO_CONFIG:
1058         assert(va == 0);
1059         tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG, data);
1060         break;
1061       case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0:
1062         assert(va == 0);
1063         tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0, data);
1064         break;
1065       case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1:
1066         assert(va == 0);
1067         tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1, data);
1068         break;
1069       case ASI_IMMU_CTXT_ZERO_CONFIG:
1070         assert(va == 0);
1071         tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG, data);
1072         break;
1073       case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0:
1074         assert(va == 0);
1075         tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0, data);
1076         break;
1077       case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1:
1078         assert(va == 0);
1079         tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1, data);
1080         break;
1081       case ASI_DMMU_CTXT_NONZERO_CONFIG:
1082         assert(va == 0);
1083         tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG, data);
1084         break;
1085       case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0:
1086         assert(va == 0);
1087         tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0, data);
1088         break;
1089       case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1:
1090         assert(va == 0);
1091         tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1, data);
1092         break;
1093       case ASI_IMMU_CTXT_NONZERO_CONFIG:
1094         assert(va == 0);
1095         tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG, data);
1096         break;
1097       case ASI_SPARC_ERROR_EN_REG:
1098       case ASI_SPARC_ERROR_STATUS_REG:
1099         warn("Ignoring write to SPARC ERROR regsiter\n");
1100         break;
1101       case ASI_HYP_SCRATCHPAD:
1102       case ASI_SCRATCHPAD:
1103         tc->setMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3), data);
1104         break;
1105       case ASI_IMMU:
1106         switch (va) {
1107           case 0x18:
1108             tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_SFSR, data);
1109             break;
1110           case 0x30:
1111             sext<59>(bits(data, 59,0));
1112             tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS, data);
1113             break;
1114           default:
1115             goto doMmuWriteError;
1116         }
1117         break;
1118       case ASI_ITLB_DATA_ACCESS_REG:
1119         entry_insert = bits(va, 8,3);
1120       case ASI_ITLB_DATA_IN_REG:
1121         assert(entry_insert != -1 || mbits(va,10,9) == va);
1122         ta_insert = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS);
1123         va_insert = mbits(ta_insert, 63,13);
1124         ct_insert = mbits(ta_insert, 12,0);
1125         part_insert = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID);
1126         real_insert = bits(va, 9,9);
1127         pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v :
1128                 PageTableEntry::sun4u);
1129         tc->getITBPtr()->insert(va_insert, part_insert, ct_insert, real_insert,
1130                 pte, entry_insert);
1131         break;
1132       case ASI_DTLB_DATA_ACCESS_REG:
1133         entry_insert = bits(va, 8,3);
1134       case ASI_DTLB_DATA_IN_REG:
1135         assert(entry_insert != -1 || mbits(va,10,9) == va);
1136         ta_insert = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS);
1137         va_insert = mbits(ta_insert, 63,13);
1138         ct_insert = mbits(ta_insert, 12,0);
1139         part_insert = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID);
1140         real_insert = bits(va, 9,9);
1141         pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v :
1142                 PageTableEntry::sun4u);
1143         insert(va_insert, part_insert, ct_insert, real_insert, pte, entry_insert);
1144         break;
1145       case ASI_IMMU_DEMAP:
1146         ignore = false;
1147         ctx_id = -1;
1148         part_id =  tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID);
1149         switch (bits(va,5,4)) {
1150           case 0:
1151             ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT);
1152             break;
1153           case 1:
1154             ignore = true;
1155             break;
1156           case 3:
1157             ctx_id = 0;
1158             break;
1159           default:
1160             ignore = true;
1161         }
1162
1163         switch(bits(va,7,6)) {
1164           case 0: // demap page
1165             if (!ignore)
1166                 tc->getITBPtr()->demapPage(mbits(va,63,13), part_id,
1167                         bits(va,9,9), ctx_id);
1168             break;
1169           case 1: //demap context
1170             if (!ignore)
1171                 tc->getITBPtr()->demapContext(part_id, ctx_id);
1172             break;
1173           case 2:
1174             tc->getITBPtr()->demapAll(part_id);
1175             break;
1176           default:
1177             panic("Invalid type for IMMU demap\n");
1178         }
1179         break;
1180       case ASI_DMMU:
1181         switch (va) {
1182           case 0x18:
1183             tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_SFSR, data);
1184             break;
1185           case 0x30:
1186             sext<59>(bits(data, 59,0));
1187             tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS, data);
1188             break;
1189           case 0x80:
1190             tc->setMiscRegWithEffect(MISCREG_MMU_PART_ID, data);
1191             break;
1192           default:
1193             goto doMmuWriteError;
1194         }
1195         break;
1196       case ASI_DMMU_DEMAP:
1197         ignore = false;
1198         ctx_id = -1;
1199         part_id =  tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID);
1200         switch (bits(va,5,4)) {
1201           case 0:
1202             ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT);
1203             break;
1204           case 1:
1205             ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_S_CONTEXT);
1206             break;
1207           case 3:
1208             ctx_id = 0;
1209             break;
1210           default:
1211             ignore = true;
1212         }
1213
1214         switch(bits(va,7,6)) {
1215           case 0: // demap page
1216             if (!ignore)
1217                 demapPage(mbits(va,63,13), part_id, bits(va,9,9), ctx_id);
1218             break;
1219           case 1: //demap context
1220             if (!ignore)
1221                 demapContext(part_id, ctx_id);
1222             break;
1223           case 2:
1224             demapAll(part_id);
1225             break;
1226           default:
1227             panic("Invalid type for IMMU demap\n");
1228         }
1229         break;
1230       default:
1231 doMmuWriteError:
1232         panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n",
1233             (uint32_t)pkt->req->getAsi(), pkt->getAddr(), data);
1234     }
1235     pkt->result = Packet::Success;
1236     return tc->getCpuPtr()->cycles(1);
1237 }
1238
1239 void
1240 TLB::serialize(std::ostream &os)
1241 {
1242     panic("Need to implement serialize tlb for SPARC\n");
1243 }
1244
1245 void
1246 TLB::unserialize(Checkpoint *cp, const std::string &section)
1247 {
1248     panic("Need to implement unserialize tlb for SPARC\n");
1249 }
1250
1251
1252 DEFINE_SIM_OBJECT_CLASS_NAME("SparcTLB", TLB)
1253
1254 BEGIN_DECLARE_SIM_OBJECT_PARAMS(ITB)
1255
1256     Param<int> size;
1257
1258 END_DECLARE_SIM_OBJECT_PARAMS(ITB)
1259
1260 BEGIN_INIT_SIM_OBJECT_PARAMS(ITB)
1261
1262     INIT_PARAM_DFLT(size, "TLB size", 48)
1263
1264 END_INIT_SIM_OBJECT_PARAMS(ITB)
1265
1266
1267 CREATE_SIM_OBJECT(ITB)
1268 {
1269     return new ITB(getInstanceName(), size);
1270 }
1271
1272 REGISTER_SIM_OBJECT("SparcITB", ITB)
1273
1274 BEGIN_DECLARE_SIM_OBJECT_PARAMS(DTB)
1275
1276     Param<int> size;
1277
1278 END_DECLARE_SIM_OBJECT_PARAMS(DTB)
1279
1280 BEGIN_INIT_SIM_OBJECT_PARAMS(DTB)
1281
1282     INIT_PARAM_DFLT(size, "TLB size", 64)
1283
1284 END_INIT_SIM_OBJECT_PARAMS(DTB)
1285
1286
1287 CREATE_SIM_OBJECT(DTB)
1288 {
1289     return new DTB(getInstanceName(), size);
1290 }
1291
1292 REGISTER_SIM_OBJECT("SparcDTB", DTB)
1293 }