2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 #include "arch/sparc/asi.hh"
34 #include "arch/sparc/faults.hh"
35 #include "arch/sparc/registers.hh"
36 #include "arch/sparc/tlb.hh"
37 #include "base/bitfield.hh"
38 #include "base/trace.hh"
39 #include "cpu/thread_context.hh"
40 #include "cpu/base.hh"
41 #include "mem/packet_access.hh"
42 #include "mem/request.hh"
43 #include "sim/system.hh"
45 /* @todo remove some of the magic constants. -- ali
49 TLB::TLB(const Params
*p
)
50 : BaseTLB(p
), size(p
->size
), usedEntries(0), lastReplaced(0),
53 // To make this work you'll have to change the hypervisor and OS
55 fatal("SPARC T1 TLB registers don't support more than 64 TLB entries");
57 tlb
= new TlbEntry
[size
];
58 std::memset(tlb
, 0, sizeof(TlbEntry
) * size
);
60 for (int x
= 0; x
< size
; x
++)
61 freeList
.push_back(&tlb
[x
]);
80 for (i
= lookupTable
.begin(); i
!= lookupTable
.end(); i
++) {
81 TlbEntry
*t
= i
->second
;
82 if (!t
->pte
.locked()) {
91 TLB::insert(Addr va
, int partition_id
, int context_id
, bool real
,
92 const PageTableEntry
& PTE
, int entry
)
95 TlbEntry
*new_entry
= NULL
;
100 va
&= ~(PTE
.size()-1);
102 tr.size = PTE.size() - 1;
103 tr.contextId = context_id;
104 tr.partitionId = partition_id;
109 "TLB: Inserting Entry; va=%#x pa=%#x pid=%d cid=%d r=%d entryid=%d\n",
110 va
, PTE
.paddr(), partition_id
, context_id
, (int)real
, entry
);
112 // Demap any entry that conflicts
113 for (x
= 0; x
< size
; x
++) {
114 if (tlb
[x
].range
.real
== real
&&
115 tlb
[x
].range
.partitionId
== partition_id
&&
116 tlb
[x
].range
.va
< va
+ PTE
.size() - 1 &&
117 tlb
[x
].range
.va
+ tlb
[x
].range
.size
>= va
&&
118 (real
|| tlb
[x
].range
.contextId
== context_id
))
121 freeList
.push_front(&tlb
[x
]);
122 DPRINTF(TLB
, "TLB: Conflicting entry %#X , deleting it\n", x
);
124 tlb
[x
].valid
= false;
129 lookupTable
.erase(tlb
[x
].range
);
135 assert(entry
< size
&& entry
>= 0);
136 new_entry
= &tlb
[entry
];
138 if (!freeList
.empty()) {
139 new_entry
= freeList
.front();
146 if (x
== lastReplaced
)
147 goto insertAllLocked
;
148 } while (tlb
[x
].pte
.locked());
155 // Update the last ently if their all locked
157 new_entry
= &tlb
[size
-1];
160 freeList
.remove(new_entry
);
161 if (new_entry
->valid
&& new_entry
->used
)
163 if (new_entry
->valid
)
164 lookupTable
.erase(new_entry
->range
);
168 new_entry
->range
.va
= va
;
169 new_entry
->range
.size
= PTE
.size() - 1;
170 new_entry
->range
.partitionId
= partition_id
;
171 new_entry
->range
.contextId
= context_id
;
172 new_entry
->range
.real
= real
;
173 new_entry
->pte
= PTE
;
174 new_entry
->used
= true;;
175 new_entry
->valid
= true;
178 i
= lookupTable
.insert(new_entry
->range
, new_entry
);
179 assert(i
!= lookupTable
.end());
181 // If all entries have their used bit set, clear it on them all,
182 // but the one we just inserted
183 if (usedEntries
== size
) {
185 new_entry
->used
= true;
192 TLB::lookup(Addr va
, int partition_id
, bool real
, int context_id
,
199 DPRINTF(TLB
, "TLB: Looking up entry va=%#x pid=%d cid=%d r=%d\n",
200 va
, partition_id
, context_id
, real
);
201 // Assemble full address structure
204 tr
.contextId
= context_id
;
205 tr
.partitionId
= partition_id
;
208 // Try to find the entry
209 i
= lookupTable
.find(tr
);
210 if (i
== lookupTable
.end()) {
211 DPRINTF(TLB
, "TLB: No valid entry found\n");
215 // Mark the entries used bit and clear other used bits in needed
217 DPRINTF(TLB
, "TLB: Valid entry found pa: %#x size: %#x\n", t
->pte
.paddr(),
220 // Update the used bits only if this is a real access (not a fake
221 // one from virttophys()
222 if (!t
->used
&& update_used
) {
225 if (usedEntries
== size
) {
239 for (int x
= 0; x
< size
; x
++) {
241 DPRINTFN("%4d: %#2x:%#2x %c %#4x %#8x %#8x %#16x\n",
242 x
, tlb
[x
].range
.partitionId
, tlb
[x
].range
.contextId
,
243 tlb
[x
].range
.real
? 'R' : ' ', tlb
[x
].range
.size
,
244 tlb
[x
].range
.va
, tlb
[x
].pte
.paddr(), tlb
[x
].pte());
250 TLB::demapPage(Addr va
, int partition_id
, bool real
, int context_id
)
255 DPRINTF(IPR
, "TLB: Demapping Page va=%#x pid=%#d cid=%d r=%d\n",
256 va
, partition_id
, context_id
, real
);
260 // Assemble full address structure
263 tr
.contextId
= context_id
;
264 tr
.partitionId
= partition_id
;
267 // Demap any entry that conflicts
268 i
= lookupTable
.find(tr
);
269 if (i
!= lookupTable
.end()) {
270 DPRINTF(IPR
, "TLB: Demapped page\n");
271 i
->second
->valid
= false;
272 if (i
->second
->used
) {
273 i
->second
->used
= false;
276 freeList
.push_front(i
->second
);
277 lookupTable
.erase(i
);
282 TLB::demapContext(int partition_id
, int context_id
)
284 DPRINTF(IPR
, "TLB: Demapping Context pid=%#d cid=%d\n",
285 partition_id
, context_id
);
287 for (int x
= 0; x
< size
; x
++) {
288 if (tlb
[x
].range
.contextId
== context_id
&&
289 tlb
[x
].range
.partitionId
== partition_id
) {
290 if (tlb
[x
].valid
== true) {
291 freeList
.push_front(&tlb
[x
]);
293 tlb
[x
].valid
= false;
298 lookupTable
.erase(tlb
[x
].range
);
304 TLB::demapAll(int partition_id
)
306 DPRINTF(TLB
, "TLB: Demapping All pid=%#d\n", partition_id
);
308 for (int x
= 0; x
< size
; x
++) {
309 if (tlb
[x
].valid
&& !tlb
[x
].pte
.locked() &&
310 tlb
[x
].range
.partitionId
== partition_id
) {
311 freeList
.push_front(&tlb
[x
]);
312 tlb
[x
].valid
= false;
317 lookupTable
.erase(tlb
[x
].range
);
328 for (int x
= 0; x
< size
; x
++) {
329 if (tlb
[x
].valid
== true)
330 freeList
.push_back(&tlb
[x
]);
331 tlb
[x
].valid
= false;
338 TLB::TteRead(int entry
)
341 panic("entry: %d\n", entry
);
343 assert(entry
< size
);
344 if (tlb
[entry
].valid
)
345 return tlb
[entry
].pte();
347 return (uint64_t)-1ll;
351 TLB::TagRead(int entry
)
353 assert(entry
< size
);
355 if (!tlb
[entry
].valid
)
356 return (uint64_t)-1ll;
358 tag
= tlb
[entry
].range
.contextId
;
359 tag
|= tlb
[entry
].range
.va
;
360 tag
|= (uint64_t)tlb
[entry
].range
.partitionId
<< 61;
361 tag
|= tlb
[entry
].range
.real
? ULL(1) << 60 : 0;
362 tag
|= (uint64_t)~tlb
[entry
].pte
._size() << 56;
367 TLB::validVirtualAddress(Addr va
, bool am
)
371 if (va
>= StartVAddrHole
&& va
<= EndVAddrHole
)
377 TLB::writeSfsr(bool write
, ContextType ct
, bool se
, FaultTypes ft
, int asi
)
394 TLB::writeTagAccess(Addr va
, int context
)
396 DPRINTF(TLB
, "TLB: Writing Tag Access: va: %#X ctx: %#X value: %#X\n",
397 va
, context
, mbits(va
, 63,13) | mbits(context
,12,0));
399 tag_access
= mbits(va
, 63,13) | mbits(context
,12,0);
403 TLB::writeSfsr(Addr a
, bool write
, ContextType ct
,
404 bool se
, FaultTypes ft
, int asi
)
406 DPRINTF(TLB
, "TLB: Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n",
407 a
, (int)write
, ct
, ft
, asi
);
408 TLB::writeSfsr(write
, ct
, se
, ft
, asi
);
413 TLB::translateInst(RequestPtr req
, ThreadContext
*tc
)
415 uint64_t tlbdata
= tc
->readMiscRegNoEffect(MISCREG_TLB_DATA
);
417 Addr vaddr
= req
->getVaddr();
420 assert(req
->getAsi() == ASI_IMPLICIT
);
422 DPRINTF(TLB
, "TLB: ITB Request to translate va=%#x size=%d\n",
423 vaddr
, req
->getSize());
425 // Be fast if we can!
426 if (cacheValid
&& cacheState
== tlbdata
) {
428 if (cacheEntry
[0]->range
.va
< vaddr
+ sizeof(MachInst
) &&
429 cacheEntry
[0]->range
.va
+ cacheEntry
[0]->range
.size
>= vaddr
) {
430 req
->setPaddr(cacheEntry
[0]->pte
.translate(vaddr
));
434 req
->setPaddr(vaddr
& PAddrImplMask
);
439 bool hpriv
= bits(tlbdata
,0,0);
440 bool red
= bits(tlbdata
,1,1);
441 bool priv
= bits(tlbdata
,2,2);
442 bool addr_mask
= bits(tlbdata
,3,3);
443 bool lsu_im
= bits(tlbdata
,4,4);
445 int part_id
= bits(tlbdata
,15,8);
446 int tl
= bits(tlbdata
,18,16);
447 int pri_context
= bits(tlbdata
,47,32);
453 DPRINTF(TLB
, "TLB: priv:%d hpriv:%d red:%d lsuim:%d part_id: %#X\n",
454 priv
, hpriv
, red
, lsu_im
, part_id
);
463 context
= pri_context
;
466 if ( hpriv
|| red
) {
468 cacheState
= tlbdata
;
469 cacheEntry
[0] = NULL
;
470 req
->setPaddr(vaddr
& PAddrImplMask
);
474 // If the access is unaligned trap
476 writeSfsr(false, ct
, false, OtherFault
, asi
);
477 return new MemAddressNotAligned
;
481 vaddr
= vaddr
& VAddrAMask
;
483 if (!validVirtualAddress(vaddr
, addr_mask
)) {
484 writeSfsr(false, ct
, false, VaOutOfRange
, asi
);
485 return new InstructionAccessException
;
489 e
= lookup(vaddr
, part_id
, true);
493 e
= lookup(vaddr
, part_id
, false, context
);
496 if (e
== NULL
|| !e
->valid
) {
497 writeTagAccess(vaddr
, context
);
499 return new InstructionRealTranslationMiss
;
502 return new FastInstructionAccessMMUMiss
;
504 return new FastInstructionAccessMMUMiss(req
->getVaddr());
508 // were not priviledged accesing priv page
509 if (!priv
&& e
->pte
.priv()) {
510 writeTagAccess(vaddr
, context
);
511 writeSfsr(false, ct
, false, PrivViolation
, asi
);
512 return new InstructionAccessException
;
515 // cache translation date for next translation
517 cacheState
= tlbdata
;
520 req
->setPaddr(e
->pte
.translate(vaddr
));
521 DPRINTF(TLB
, "TLB: %#X -> %#X\n", vaddr
, req
->getPaddr());
526 TLB::translateData(RequestPtr req
, ThreadContext
*tc
, bool write
)
529 * @todo this could really use some profiling and fixing to make
532 uint64_t tlbdata
= tc
->readMiscRegNoEffect(MISCREG_TLB_DATA
);
533 Addr vaddr
= req
->getVaddr();
534 Addr size
= req
->getSize();
536 asi
= (ASI
)req
->getAsi();
537 bool implicit
= false;
538 bool hpriv
= bits(tlbdata
,0,0);
539 bool unaligned
= vaddr
& (size
- 1);
541 DPRINTF(TLB
, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n",
544 if (lookupTable
.size() != 64 - freeList
.size())
545 panic("Lookup table size: %d tlb size: %d\n", lookupTable
.size(),
547 if (asi
== ASI_IMPLICIT
)
550 // Only use the fast path here if there doesn't need to be an unaligned
553 if (hpriv
&& implicit
) {
554 req
->setPaddr(vaddr
& PAddrImplMask
);
558 // Be fast if we can!
559 if (cacheValid
&& cacheState
== tlbdata
) {
564 TlbEntry
*ce
= cacheEntry
[0];
565 Addr ce_va
= ce
->range
.va
;
566 if (cacheAsi
[0] == asi
&&
567 ce_va
< vaddr
+ size
&& ce_va
+ ce
->range
.size
> vaddr
&&
568 (!write
|| ce
->pte
.writable())) {
569 req
->setPaddr(ce
->pte
.translate(vaddr
));
570 if (ce
->pte
.sideffect() || (ce
->pte
.paddr() >> 39) & 1)
571 req
->setFlags(Request::UNCACHEABLE
);
572 DPRINTF(TLB
, "TLB: %#X -> %#X\n", vaddr
, req
->getPaddr());
575 } // if cache entry valid
577 TlbEntry
*ce
= cacheEntry
[1];
578 Addr ce_va
= ce
->range
.va
;
579 if (cacheAsi
[1] == asi
&&
580 ce_va
< vaddr
+ size
&& ce_va
+ ce
->range
.size
> vaddr
&&
581 (!write
|| ce
->pte
.writable())) {
582 req
->setPaddr(ce
->pte
.translate(vaddr
));
583 if (ce
->pte
.sideffect() || (ce
->pte
.paddr() >> 39) & 1)
584 req
->setFlags(Request::UNCACHEABLE
);
585 DPRINTF(TLB
, "TLB: %#X -> %#X\n", vaddr
, req
->getPaddr());
588 } // if cache entry valid
592 bool red
= bits(tlbdata
,1,1);
593 bool priv
= bits(tlbdata
,2,2);
594 bool addr_mask
= bits(tlbdata
,3,3);
595 bool lsu_dm
= bits(tlbdata
,5,5);
597 int part_id
= bits(tlbdata
,15,8);
598 int tl
= bits(tlbdata
,18,16);
599 int pri_context
= bits(tlbdata
,47,32);
600 int sec_context
= bits(tlbdata
,63,48);
603 ContextType ct
= Primary
;
608 DPRINTF(TLB
, "TLB: priv:%d hpriv:%d red:%d lsudm:%d part_id: %#X\n",
609 priv
, hpriv
, red
, lsu_dm
, part_id
);
619 context
= pri_context
;
622 // We need to check for priv level/asi priv
623 if (!priv
&& !hpriv
&& !asiIsUnPriv(asi
)) {
624 // It appears that context should be Nucleus in these cases?
625 writeSfsr(vaddr
, write
, Nucleus
, false, IllegalAsi
, asi
);
626 return new PrivilegedAction
;
629 if (!hpriv
&& asiIsHPriv(asi
)) {
630 writeSfsr(vaddr
, write
, Nucleus
, false, IllegalAsi
, asi
);
631 return new DataAccessException
;
634 if (asiIsPrimary(asi
)) {
635 context
= pri_context
;
637 } else if (asiIsSecondary(asi
)) {
638 context
= sec_context
;
640 } else if (asiIsNucleus(asi
)) {
645 context
= pri_context
;
649 if (!implicit
&& asi
!= ASI_P
&& asi
!= ASI_S
) {
650 if (asiIsLittle(asi
))
651 panic("Little Endian ASIs not supported\n");
653 //XXX It's unclear from looking at the documentation how a no fault
654 // load differs from a regular one, other than what happens concerning
655 // nfo and e bits in the TTE
656 // if (asiIsNoFault(asi))
657 // panic("No Fault ASIs not supported\n");
659 if (asiIsPartialStore(asi
))
660 panic("Partial Store ASIs not supported\n");
663 panic("Cmt ASI registers not implmented\n");
665 if (asiIsInterrupt(asi
))
666 goto handleIntRegAccess
;
668 goto handleMmuRegAccess
;
669 if (asiIsScratchPad(asi
))
670 goto handleScratchRegAccess
;
672 goto handleQueueRegAccess
;
673 if (asiIsSparcError(asi
))
674 goto handleSparcErrorRegAccess
;
676 if (!asiIsReal(asi
) && !asiIsNucleus(asi
) && !asiIsAsIfUser(asi
) &&
677 !asiIsTwin(asi
) && !asiIsBlock(asi
) && !asiIsNoFault(asi
))
678 panic("Accessing ASI %#X. Should we?\n", asi
);
681 // If the asi is unaligned trap
683 writeSfsr(vaddr
, false, ct
, false, OtherFault
, asi
);
684 return new MemAddressNotAligned
;
688 vaddr
= vaddr
& VAddrAMask
;
690 if (!validVirtualAddress(vaddr
, addr_mask
)) {
691 writeSfsr(vaddr
, false, ct
, true, VaOutOfRange
, asi
);
692 return new DataAccessException
;
695 if ((!lsu_dm
&& !hpriv
&& !red
) || asiIsReal(asi
)) {
700 if (hpriv
&& (implicit
|| (!asiIsAsIfUser(asi
) && !asiIsReal(asi
)))) {
701 req
->setPaddr(vaddr
& PAddrImplMask
);
705 e
= lookup(vaddr
, part_id
, real
, context
);
707 if (e
== NULL
|| !e
->valid
) {
708 writeTagAccess(vaddr
, context
);
709 DPRINTF(TLB
, "TLB: DTB Failed to find matching TLB entry\n");
711 return new DataRealTranslationMiss
;
714 return new FastDataAccessMMUMiss
;
716 return new FastDataAccessMMUMiss(req
->getVaddr());
721 if (!priv
&& e
->pte
.priv()) {
722 writeTagAccess(vaddr
, context
);
723 writeSfsr(vaddr
, write
, ct
, e
->pte
.sideffect(), PrivViolation
, asi
);
724 return new DataAccessException
;
727 if (write
&& !e
->pte
.writable()) {
728 writeTagAccess(vaddr
, context
);
729 writeSfsr(vaddr
, write
, ct
, e
->pte
.sideffect(), OtherFault
, asi
);
730 return new FastDataAccessProtection
;
733 if (e
->pte
.nofault() && !asiIsNoFault(asi
)) {
734 writeTagAccess(vaddr
, context
);
735 writeSfsr(vaddr
, write
, ct
, e
->pte
.sideffect(), LoadFromNfo
, asi
);
736 return new DataAccessException
;
739 if (e
->pte
.sideffect() && asiIsNoFault(asi
)) {
740 writeTagAccess(vaddr
, context
);
741 writeSfsr(vaddr
, write
, ct
, e
->pte
.sideffect(), SideEffect
, asi
);
742 return new DataAccessException
;
745 if (e
->pte
.sideffect() || (e
->pte
.paddr() >> 39) & 1)
746 req
->setFlags(Request::UNCACHEABLE
);
748 // cache translation date for next translation
749 cacheState
= tlbdata
;
751 cacheEntry
[1] = NULL
;
752 cacheEntry
[0] = NULL
;
755 if (cacheEntry
[0] != e
&& cacheEntry
[1] != e
) {
756 cacheEntry
[1] = cacheEntry
[0];
758 cacheAsi
[1] = cacheAsi
[0];
761 cacheAsi
[0] = (ASI
)0;
764 req
->setPaddr(e
->pte
.translate(vaddr
));
765 DPRINTF(TLB
, "TLB: %#X -> %#X\n", vaddr
, req
->getPaddr());
768 /** Normal flow ends here. */
771 writeSfsr(vaddr
, write
, Primary
, true, IllegalAsi
, asi
);
773 return new DataAccessException
;
775 return new PrivilegedAction
;
778 if ((asi
== ASI_SWVR_UDB_INTR_W
&& !write
) ||
779 (asi
== ASI_SWVR_UDB_INTR_R
&& write
)) {
780 writeSfsr(vaddr
, write
, Primary
, true, IllegalAsi
, asi
);
781 return new DataAccessException
;
787 handleScratchRegAccess
:
788 if (vaddr
> 0x38 || (vaddr
>= 0x20 && vaddr
< 0x30 && !hpriv
)) {
789 writeSfsr(vaddr
, write
, Primary
, true, IllegalAsi
, asi
);
790 return new DataAccessException
;
794 handleQueueRegAccess
:
795 if (!priv
&& !hpriv
) {
796 writeSfsr(vaddr
, write
, Primary
, true, IllegalAsi
, asi
);
797 return new PrivilegedAction
;
799 if ((!hpriv
&& vaddr
& 0xF) || vaddr
> 0x3f8 || vaddr
< 0x3c0) {
800 writeSfsr(vaddr
, write
, Primary
, true, IllegalAsi
, asi
);
801 return new DataAccessException
;
805 handleSparcErrorRegAccess
:
807 writeSfsr(vaddr
, write
, Primary
, true, IllegalAsi
, asi
);
809 return new DataAccessException
;
811 return new PrivilegedAction
;
818 DPRINTF(TLB
, "TLB: DTB Translating MM IPR access\n");
819 req
->setFlags(Request::MMAPPED_IPR
);
820 req
->setPaddr(req
->getVaddr());
825 TLB::translateAtomic(RequestPtr req
, ThreadContext
*tc
, Mode mode
)
828 return translateInst(req
, tc
);
830 return translateData(req
, tc
, mode
== Write
);
834 TLB::translateTiming(RequestPtr req
, ThreadContext
*tc
,
835 Translation
*translation
, Mode mode
)
838 translation
->finish(translateAtomic(req
, tc
, mode
), req
, tc
, mode
);
844 TLB::doMmuRegRead(ThreadContext
*tc
, Packet
*pkt
)
846 Addr va
= pkt
->getAddr();
847 ASI asi
= (ASI
)pkt
->req
->getAsi();
850 DPRINTF(IPR
, "Memory Mapped IPR Read: asi=%#X a=%#x\n",
851 (uint32_t)pkt
->req
->getAsi(), pkt
->getAddr());
853 TLB
*itb
= tc
->getITBPtr();
856 case ASI_LSU_CONTROL_REG
:
858 pkt
->set(tc
->readMiscReg(MISCREG_MMU_LSU_CTRL
));
863 pkt
->set(tc
->readMiscReg(MISCREG_MMU_P_CONTEXT
));
866 pkt
->set(tc
->readMiscReg(MISCREG_MMU_S_CONTEXT
));
873 pkt
->set(tc
->readMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD
+
876 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0
:
878 pkt
->set(c0_tsb_ps0
);
880 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1
:
882 pkt
->set(c0_tsb_ps1
);
884 case ASI_DMMU_CTXT_ZERO_CONFIG
:
888 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0
:
890 pkt
->set(itb
->c0_tsb_ps0
);
892 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1
:
894 pkt
->set(itb
->c0_tsb_ps1
);
896 case ASI_IMMU_CTXT_ZERO_CONFIG
:
898 pkt
->set(itb
->c0_config
);
900 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0
:
902 pkt
->set(cx_tsb_ps0
);
904 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1
:
906 pkt
->set(cx_tsb_ps1
);
908 case ASI_DMMU_CTXT_NONZERO_CONFIG
:
912 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0
:
914 pkt
->set(itb
->cx_tsb_ps0
);
916 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1
:
918 pkt
->set(itb
->cx_tsb_ps1
);
920 case ASI_IMMU_CTXT_NONZERO_CONFIG
:
922 pkt
->set(itb
->cx_config
);
924 case ASI_SPARC_ERROR_STATUS_REG
:
925 pkt
->set((uint64_t)0);
927 case ASI_HYP_SCRATCHPAD
:
929 pkt
->set(tc
->readMiscReg(MISCREG_SCRATCHPAD_R0
+ (va
>> 3)));
934 temp
= itb
->tag_access
;
935 pkt
->set(bits(temp
,63,22) | bits(temp
,12,0) << 48);
941 pkt
->set(itb
->tag_access
);
951 pkt
->set(bits(temp
,63,22) | bits(temp
,12,0) << 48);
960 pkt
->set(tag_access
);
963 pkt
->set(tc
->readMiscReg(MISCREG_MMU_PART_ID
));
969 case ASI_DMMU_TSB_PS0_PTR_REG
:
970 pkt
->set(MakeTsbPtr(Ps0
,
977 case ASI_DMMU_TSB_PS1_PTR_REG
:
978 pkt
->set(MakeTsbPtr(Ps1
,
985 case ASI_IMMU_TSB_PS0_PTR_REG
:
986 pkt
->set(MakeTsbPtr(Ps0
,
993 case ASI_IMMU_TSB_PS1_PTR_REG
:
994 pkt
->set(MakeTsbPtr(Ps1
,
1001 case ASI_SWVR_INTR_RECEIVE
:
1003 SparcISA::Interrupts
* interrupts
=
1004 dynamic_cast<SparcISA::Interrupts
*>(
1005 tc
->getCpuPtr()->getInterruptController());
1006 pkt
->set(interrupts
->get_vec(IT_INT_VEC
));
1009 case ASI_SWVR_UDB_INTR_R
:
1011 SparcISA::Interrupts
* interrupts
=
1012 dynamic_cast<SparcISA::Interrupts
*>(
1013 tc
->getCpuPtr()->getInterruptController());
1014 temp
= findMsbSet(interrupts
->get_vec(IT_INT_VEC
));
1015 tc
->getCpuPtr()->clearInterrupt(IT_INT_VEC
, temp
);
1021 panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n",
1024 pkt
->makeAtomicResponse();
1025 return tc
->getCpuPtr()->ticks(1);
1029 TLB::doMmuRegWrite(ThreadContext
*tc
, Packet
*pkt
)
1031 uint64_t data
= pkt
->get
<uint64_t>();
1032 Addr va
= pkt
->getAddr();
1033 ASI asi
= (ASI
)pkt
->req
->getAsi();
1039 int entry_insert
= -1;
1046 DPRINTF(IPR
, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n",
1047 (uint32_t)asi
, va
, data
);
1049 TLB
*itb
= tc
->getITBPtr();
1052 case ASI_LSU_CONTROL_REG
:
1054 tc
->setMiscReg(MISCREG_MMU_LSU_CTRL
, data
);
1059 tc
->setMiscReg(MISCREG_MMU_P_CONTEXT
, data
);
1062 tc
->setMiscReg(MISCREG_MMU_S_CONTEXT
, data
);
1065 goto doMmuWriteError
;
1069 assert(mbits(data
,13,6) == data
);
1070 tc
->setMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD
+
1071 (va
>> 4) - 0x3c, data
);
1073 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0
:
1077 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1
:
1081 case ASI_DMMU_CTXT_ZERO_CONFIG
:
1085 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0
:
1087 itb
->c0_tsb_ps0
= data
;
1089 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1
:
1091 itb
->c0_tsb_ps1
= data
;
1093 case ASI_IMMU_CTXT_ZERO_CONFIG
:
1095 itb
->c0_config
= data
;
1097 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0
:
1101 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1
:
1105 case ASI_DMMU_CTXT_NONZERO_CONFIG
:
1109 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0
:
1111 itb
->cx_tsb_ps0
= data
;
1113 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1
:
1115 itb
->cx_tsb_ps1
= data
;
1117 case ASI_IMMU_CTXT_NONZERO_CONFIG
:
1119 itb
->cx_config
= data
;
1121 case ASI_SPARC_ERROR_EN_REG
:
1122 case ASI_SPARC_ERROR_STATUS_REG
:
1123 inform("Ignoring write to SPARC ERROR regsiter\n");
1125 case ASI_HYP_SCRATCHPAD
:
1126 case ASI_SCRATCHPAD
:
1127 tc
->setMiscReg(MISCREG_SCRATCHPAD_R0
+ (va
>> 3), data
);
1135 sext
<59>(bits(data
, 59,0));
1136 itb
->tag_access
= data
;
1139 goto doMmuWriteError
;
1142 case ASI_ITLB_DATA_ACCESS_REG
:
1143 entry_insert
= bits(va
, 8,3);
1144 case ASI_ITLB_DATA_IN_REG
:
1145 assert(entry_insert
!= -1 || mbits(va
,10,9) == va
);
1146 ta_insert
= itb
->tag_access
;
1147 va_insert
= mbits(ta_insert
, 63,13);
1148 ct_insert
= mbits(ta_insert
, 12,0);
1149 part_insert
= tc
->readMiscReg(MISCREG_MMU_PART_ID
);
1150 real_insert
= bits(va
, 9,9);
1151 pte
.populate(data
, bits(va
,10,10) ? PageTableEntry::sun4v
:
1152 PageTableEntry::sun4u
);
1153 tc
->getITBPtr()->insert(va_insert
, part_insert
, ct_insert
, real_insert
,
1156 case ASI_DTLB_DATA_ACCESS_REG
:
1157 entry_insert
= bits(va
, 8,3);
1158 case ASI_DTLB_DATA_IN_REG
:
1159 assert(entry_insert
!= -1 || mbits(va
,10,9) == va
);
1160 ta_insert
= tag_access
;
1161 va_insert
= mbits(ta_insert
, 63,13);
1162 ct_insert
= mbits(ta_insert
, 12,0);
1163 part_insert
= tc
->readMiscReg(MISCREG_MMU_PART_ID
);
1164 real_insert
= bits(va
, 9,9);
1165 pte
.populate(data
, bits(va
,10,10) ? PageTableEntry::sun4v
:
1166 PageTableEntry::sun4u
);
1167 insert(va_insert
, part_insert
, ct_insert
, real_insert
, pte
,
1170 case ASI_IMMU_DEMAP
:
1173 part_id
= tc
->readMiscReg(MISCREG_MMU_PART_ID
);
1174 switch (bits(va
,5,4)) {
1176 ctx_id
= tc
->readMiscReg(MISCREG_MMU_P_CONTEXT
);
1188 switch (bits(va
,7,6)) {
1189 case 0: // demap page
1191 tc
->getITBPtr()->demapPage(mbits(va
,63,13), part_id
,
1192 bits(va
,9,9), ctx_id
);
1194 case 1: // demap context
1196 tc
->getITBPtr()->demapContext(part_id
, ctx_id
);
1199 tc
->getITBPtr()->demapAll(part_id
);
1202 panic("Invalid type for IMMU demap\n");
1211 sext
<59>(bits(data
, 59,0));
1215 tc
->setMiscReg(MISCREG_MMU_PART_ID
, data
);
1218 goto doMmuWriteError
;
1221 case ASI_DMMU_DEMAP
:
1224 part_id
= tc
->readMiscReg(MISCREG_MMU_PART_ID
);
1225 switch (bits(va
,5,4)) {
1227 ctx_id
= tc
->readMiscReg(MISCREG_MMU_P_CONTEXT
);
1230 ctx_id
= tc
->readMiscReg(MISCREG_MMU_S_CONTEXT
);
1239 switch (bits(va
,7,6)) {
1240 case 0: // demap page
1242 demapPage(mbits(va
,63,13), part_id
, bits(va
,9,9), ctx_id
);
1244 case 1: // demap context
1246 demapContext(part_id
, ctx_id
);
1252 panic("Invalid type for IMMU demap\n");
1255 case ASI_SWVR_INTR_RECEIVE
:
1258 // clear all the interrupts that aren't set in the write
1259 SparcISA::Interrupts
* interrupts
=
1260 dynamic_cast<SparcISA::Interrupts
*>(
1261 tc
->getCpuPtr()->getInterruptController());
1262 while (interrupts
->get_vec(IT_INT_VEC
) & data
) {
1263 msb
= findMsbSet(interrupts
->get_vec(IT_INT_VEC
) & data
);
1264 tc
->getCpuPtr()->clearInterrupt(IT_INT_VEC
, msb
);
1268 case ASI_SWVR_UDB_INTR_W
:
1269 tc
->getSystemPtr()->threadContexts
[bits(data
,12,8)]->getCpuPtr()->
1270 postInterrupt(bits(data
, 5, 0), 0);
1274 panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n",
1275 (uint32_t)pkt
->req
->getAsi(), pkt
->getAddr(), data
);
1277 pkt
->makeAtomicResponse();
1278 return tc
->getCpuPtr()->ticks(1);
1284 TLB::GetTsbPtr(ThreadContext
*tc
, Addr addr
, int ctx
, Addr
*ptrs
)
1286 uint64_t tag_access
= mbits(addr
,63,13) | mbits(ctx
,12,0);
1287 TLB
* itb
= tc
->getITBPtr();
1288 ptrs
[0] = MakeTsbPtr(Ps0
, tag_access
,
1293 ptrs
[1] = MakeTsbPtr(Ps1
, tag_access
,
1298 ptrs
[2] = MakeTsbPtr(Ps0
, tag_access
,
1303 ptrs
[3] = MakeTsbPtr(Ps1
, tag_access
,
1311 TLB::MakeTsbPtr(TsbPageSize ps
, uint64_t tag_access
, uint64_t c0_tsb
,
1312 uint64_t c0_config
, uint64_t cX_tsb
, uint64_t cX_config
)
1317 if (bits(tag_access
, 12,0) == 0) {
1325 uint64_t ptr
= mbits(tsb
,63,13);
1326 bool split
= bits(tsb
,12,12);
1327 int tsb_size
= bits(tsb
,3,0);
1328 int page_size
= (ps
== Ps0
) ? bits(config
, 2,0) : bits(config
,10,8);
1330 if (ps
== Ps1
&& split
)
1331 ptr
|= ULL(1) << (13 + tsb_size
);
1332 ptr
|= (tag_access
>> (9 + page_size
* 3)) & mask(12+tsb_size
, 4);
1338 TLB::serialize(std::ostream
&os
)
1340 SERIALIZE_SCALAR(size
);
1341 SERIALIZE_SCALAR(usedEntries
);
1342 SERIALIZE_SCALAR(lastReplaced
);
1344 // convert the pointer based free list into an index based one
1345 int *free_list
= (int*)malloc(sizeof(int) * size
);
1347 std::list
<TlbEntry
*>::iterator i
;
1348 i
= freeList
.begin();
1349 while (i
!= freeList
.end()) {
1350 free_list
[cntr
++] = ((size_t)*i
- (size_t)tlb
)/ sizeof(TlbEntry
);
1353 SERIALIZE_SCALAR(cntr
);
1354 SERIALIZE_ARRAY(free_list
, cntr
);
1356 SERIALIZE_SCALAR(c0_tsb_ps0
);
1357 SERIALIZE_SCALAR(c0_tsb_ps1
);
1358 SERIALIZE_SCALAR(c0_config
);
1359 SERIALIZE_SCALAR(cx_tsb_ps0
);
1360 SERIALIZE_SCALAR(cx_tsb_ps1
);
1361 SERIALIZE_SCALAR(cx_config
);
1362 SERIALIZE_SCALAR(sfsr
);
1363 SERIALIZE_SCALAR(tag_access
);
1365 for (int x
= 0; x
< size
; x
++) {
1366 nameOut(os
, csprintf("%s.PTE%d", name(), x
));
1367 tlb
[x
].serialize(os
);
1369 SERIALIZE_SCALAR(sfar
);
1373 TLB::unserialize(Checkpoint
*cp
, const std::string
§ion
)
1377 paramIn(cp
, section
, "size", oldSize
);
1378 if (oldSize
!= size
)
1379 panic("Don't support unserializing different sized TLBs\n");
1380 UNSERIALIZE_SCALAR(usedEntries
);
1381 UNSERIALIZE_SCALAR(lastReplaced
);
1384 UNSERIALIZE_SCALAR(cntr
);
1386 int *free_list
= (int*)malloc(sizeof(int) * cntr
);
1388 UNSERIALIZE_ARRAY(free_list
, cntr
);
1389 for (int x
= 0; x
< cntr
; x
++)
1390 freeList
.push_back(&tlb
[free_list
[x
]]);
1392 UNSERIALIZE_SCALAR(c0_tsb_ps0
);
1393 UNSERIALIZE_SCALAR(c0_tsb_ps1
);
1394 UNSERIALIZE_SCALAR(c0_config
);
1395 UNSERIALIZE_SCALAR(cx_tsb_ps0
);
1396 UNSERIALIZE_SCALAR(cx_tsb_ps1
);
1397 UNSERIALIZE_SCALAR(cx_config
);
1398 UNSERIALIZE_SCALAR(sfsr
);
1399 UNSERIALIZE_SCALAR(tag_access
);
1401 lookupTable
.clear();
1402 for (int x
= 0; x
< size
; x
++) {
1403 tlb
[x
].unserialize(cp
, csprintf("%s.PTE%d", section
, x
));
1405 lookupTable
.insert(tlb
[x
].range
, &tlb
[x
]);
1408 UNSERIALIZE_SCALAR(sfar
);
1411 } // namespace SparcISA
1414 SparcTLBParams::create()
1416 return new SparcISA::TLB(this);