src/arch/sparc/tlb.cc

   1 /*
   2  * Copyright (c) 2001-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Ali Saidi
  29  */
  30
  31 #include <cstring>
  32
  33 #include "arch/sparc/asi.hh"
  34 #include "arch/sparc/miscregfile.hh"
  35 #include "arch/sparc/tlb.hh"
  36 #include "base/bitfield.hh"
  37 #include "base/trace.hh"
  38 #include "cpu/thread_context.hh"
  39 #include "cpu/base.hh"
  40 #include "mem/packet_access.hh"
  41 #include "mem/request.hh"
  42 #include "sim/builder.hh"
  43
  44 /* @todo remove some of the magic constants.  -- ali
  45  * */
  46 namespace SparcISA
  47 {
  48
  49 TLB::TLB(const std::string &name, int s)
  50     : SimObject(name), size(s), usedEntries(0), lastReplaced(0),
  51       cacheValid(false)
  52 {
  53     // To make this work you'll have to change the hypervisor and OS
  54     if (size > 64)
  55         fatal("SPARC T1 TLB registers don't support more than 64 TLB entries.");
  56
  57     tlb = new TlbEntry[size];
  58     std::memset(tlb, 0, sizeof(TlbEntry) * size);
  59
  60     for (int x = 0; x < size; x++)
  61         freeList.push_back(&tlb[x]);
  62 }
  63
  64 void
  65 TLB::clearUsedBits()
  66 {
  67     MapIter i;
  68     for (i = lookupTable.begin(); i != lookupTable.end(); i++) {
  69         TlbEntry *t = i->second;
  70         if (!t->pte.locked()) {
  71             t->used = false;
  72             usedEntries--;
  73         }
  74     }
  75 }
  76
  77
  78 void
  79 TLB::insert(Addr va, int partition_id, int context_id, bool real,
  80         const PageTableEntry& PTE, int entry)
  81 {
  82
  83
  84     MapIter i;
  85     TlbEntry *new_entry = NULL;
  86 //    TlbRange tr;
  87     int x;
  88
  89     cacheValid = false;
  90     va &= ~(PTE.size()-1);
  91  /*   tr.va = va;
  92     tr.size = PTE.size() - 1;
  93     tr.contextId = context_id;
  94     tr.partitionId = partition_id;
  95     tr.real = real;
  96 */
  97
  98     DPRINTF(TLB, "TLB: Inserting TLB Entry; va=%#x pa=%#x pid=%d cid=%d r=%d entryid=%d\n",
  99             va, PTE.paddr(), partition_id, context_id, (int)real, entry);
 100
 101     // Demap any entry that conflicts
 102     for (x = 0; x < size; x++) {
 103         if (tlb[x].range.real == real &&
 104             tlb[x].range.partitionId == partition_id &&
 105             tlb[x].range.va < va + PTE.size() - 1 &&
 106             tlb[x].range.va + tlb[x].range.size >= va &&
 107             (real || tlb[x].range.contextId == context_id ))
 108         {
 109             if (tlb[x].valid) {
 110                 freeList.push_front(&tlb[x]);
 111                 DPRINTF(TLB, "TLB: Conflicting entry %#X , deleting it\n", x);
 112
 113                 tlb[x].valid = false;
 114                 if (tlb[x].used) {
 115                     tlb[x].used = false;
 116                     usedEntries--;
 117                 }
 118                 lookupTable.erase(tlb[x].range);
 119             }
 120         }
 121     }
 122
 123
 124 /*
 125     i = lookupTable.find(tr);
 126     if (i != lookupTable.end()) {
 127         i->second->valid = false;
 128         if (i->second->used) {
 129             i->second->used = false;
 130             usedEntries--;
 131         }
 132         freeList.push_front(i->second);
 133         DPRINTF(TLB, "TLB: Found conflicting entry %#X , deleting it\n",
 134                 i->second);
 135         lookupTable.erase(i);
 136     }
 137 */
 138
 139     if (entry != -1) {
 140         assert(entry < size && entry >= 0);
 141         new_entry = &tlb[entry];
 142     } else {
 143         if (!freeList.empty()) {
 144             new_entry = freeList.front();
 145         } else {
 146             x = lastReplaced;
 147             do {
 148                 ++x;
 149                 if (x == size)
 150                     x = 0;
 151                 if (x == lastReplaced)
 152                     goto insertAllLocked;
 153             } while (tlb[x].pte.locked());
 154             lastReplaced = x;
 155             new_entry = &tlb[x];
 156         }
 157         /*
 158         for (x = 0; x < size; x++) {
 159             if (!tlb[x].valid || !tlb[x].used)  {
 160                 new_entry = &tlb[x];
 161                 break;
 162             }
 163         }*/
 164     }
 165
 166 insertAllLocked:
 167     // Update the last ently if their all locked
 168     if (!new_entry) {
 169         new_entry = &tlb[size-1];
 170     }
 171
 172     freeList.remove(new_entry);
 173     if (new_entry->valid && new_entry->used)
 174         usedEntries--;
 175     if (new_entry->valid)
 176         lookupTable.erase(new_entry->range);
 177
 178
 179     assert(PTE.valid());
 180     new_entry->range.va = va;
 181     new_entry->range.size = PTE.size() - 1;
 182     new_entry->range.partitionId = partition_id;
 183     new_entry->range.contextId = context_id;
 184     new_entry->range.real = real;
 185     new_entry->pte = PTE;
 186     new_entry->used = true;;
 187     new_entry->valid = true;
 188     usedEntries++;
 189
 190
 191
 192     i = lookupTable.insert(new_entry->range, new_entry);
 193     assert(i != lookupTable.end());
 194
 195     // If all entries have there used bit set, clear it on them all, but the
 196     // one we just inserted
 197     if (usedEntries == size) {
 198         clearUsedBits();
 199         new_entry->used = true;
 200         usedEntries++;
 201     }
 202
 203 }
 204
 205
 206 TlbEntry*
 207 TLB::lookup(Addr va, int partition_id, bool real, int context_id)
 208 {
 209     MapIter i;
 210     TlbRange tr;
 211     TlbEntry *t;
 212
 213     DPRINTF(TLB, "TLB: Looking up entry va=%#x pid=%d cid=%d r=%d\n",
 214             va, partition_id, context_id, real);
 215     // Assemble full address structure
 216     tr.va = va;
 217     tr.size = MachineBytes;
 218     tr.contextId = context_id;
 219     tr.partitionId = partition_id;
 220     tr.real = real;
 221
 222     // Try to find the entry
 223     i = lookupTable.find(tr);
 224     if (i == lookupTable.end()) {
 225         DPRINTF(TLB, "TLB: No valid entry found\n");
 226         return NULL;
 227     }
 228
 229     // Mark the entries used bit and clear other used bits in needed
 230     t = i->second;
 231     DPRINTF(TLB, "TLB: Valid entry found pa: %#x size: %#x\n", t->pte.paddr(),
 232             t->pte.size());
 233     if (!t->used) {
 234         t->used = true;
 235         usedEntries++;
 236         if (usedEntries == size) {
 237             clearUsedBits();
 238             t->used = true;
 239             usedEntries++;
 240         }
 241     }
 242
 243     return t;
 244 }
 245
 246 void
 247 TLB::dumpAll()
 248 {
 249     MapIter i;
 250     for (int x = 0; x < size; x++) {
 251         if (tlb[x].valid) {
 252            DPRINTFN("%4d:  %#2x:%#2x %c %#4x %#8x %#8x %#16x\n",
 253                    x, tlb[x].range.partitionId, tlb[x].range.contextId,
 254                    tlb[x].range.real ? 'R' : ' ', tlb[x].range.size,
 255                    tlb[x].range.va, tlb[x].pte.paddr(), tlb[x].pte());
 256         }
 257     }
 258 }
 259
 260 void
 261 TLB::demapPage(Addr va, int partition_id, bool real, int context_id)
 262 {
 263     TlbRange tr;
 264     MapIter i;
 265
 266     DPRINTF(IPR, "TLB: Demapping Page va=%#x pid=%#d cid=%d r=%d\n",
 267             va, partition_id, context_id, real);
 268
 269     cacheValid = false;
 270
 271     // Assemble full address structure
 272     tr.va = va;
 273     tr.size = MachineBytes;
 274     tr.contextId = context_id;
 275     tr.partitionId = partition_id;
 276     tr.real = real;
 277
 278     // Demap any entry that conflicts
 279     i = lookupTable.find(tr);
 280     if (i != lookupTable.end()) {
 281         DPRINTF(IPR, "TLB: Demapped page\n");
 282         i->second->valid = false;
 283         if (i->second->used) {
 284             i->second->used = false;
 285             usedEntries--;
 286         }
 287         freeList.push_front(i->second);
 288         lookupTable.erase(i);
 289     }
 290 }
 291
 292 void
 293 TLB::demapContext(int partition_id, int context_id)
 294 {
 295     int x;
 296     DPRINTF(IPR, "TLB: Demapping Context pid=%#d cid=%d\n",
 297             partition_id, context_id);
 298     cacheValid = false;
 299     for (x = 0; x < size; x++) {
 300         if (tlb[x].range.contextId == context_id &&
 301             tlb[x].range.partitionId == partition_id) {
 302             if (tlb[x].valid == true) {
 303                 freeList.push_front(&tlb[x]);
 304             }
 305             tlb[x].valid = false;
 306             if (tlb[x].used) {
 307                 tlb[x].used = false;
 308                 usedEntries--;
 309             }
 310             lookupTable.erase(tlb[x].range);
 311         }
 312     }
 313 }
 314
 315 void
 316 TLB::demapAll(int partition_id)
 317 {
 318     int x;
 319     DPRINTF(TLB, "TLB: Demapping All pid=%#d\n", partition_id);
 320     cacheValid = false;
 321     for (x = 0; x < size; x++) {
 322         if (!tlb[x].pte.locked() && tlb[x].range.partitionId == partition_id) {
 323             if (tlb[x].valid == true){
 324                 freeList.push_front(&tlb[x]);
 325             }
 326             tlb[x].valid = false;
 327             if (tlb[x].used) {
 328                 tlb[x].used = false;
 329                 usedEntries--;
 330             }
 331             lookupTable.erase(tlb[x].range);
 332         }
 333     }
 334 }
 335
 336 void
 337 TLB::invalidateAll()
 338 {
 339     int x;
 340     cacheValid = false;
 341
 342     freeList.clear();
 343     lookupTable.clear();
 344     for (x = 0; x < size; x++) {
 345         if (tlb[x].valid == true)
 346             freeList.push_back(&tlb[x]);
 347         tlb[x].valid = false;
 348         tlb[x].used = false;
 349     }
 350     usedEntries = 0;
 351 }
 352
 353 uint64_t
 354 TLB::TteRead(int entry) {
 355     if (entry >= size)
 356         panic("entry: %d\n", entry);
 357
 358     assert(entry < size);
 359     if (tlb[entry].valid)
 360         return tlb[entry].pte();
 361     else
 362         return (uint64_t)-1ll;
 363 }
 364
 365 uint64_t
 366 TLB::TagRead(int entry) {
 367     assert(entry < size);
 368     uint64_t tag;
 369     if (!tlb[entry].valid)
 370         return (uint64_t)-1ll;
 371
 372     tag = tlb[entry].range.contextId;
 373     tag |= tlb[entry].range.va;
 374     tag |= (uint64_t)tlb[entry].range.partitionId << 61;
 375     tag |= tlb[entry].range.real ? ULL(1) << 60 : 0;
 376     tag |= (uint64_t)~tlb[entry].pte._size() << 56;
 377     return tag;
 378 }
 379
 380 bool
 381 TLB::validVirtualAddress(Addr va, bool am)
 382 {
 383     if (am)
 384         return true;
 385     if (va >= StartVAddrHole && va <= EndVAddrHole)
 386         return false;
 387     return true;
 388 }
 389
 390 void
 391 TLB::writeSfsr(ThreadContext *tc, int reg,  bool write, ContextType ct,
 392         bool se, FaultTypes ft, int asi)
 393 {
 394     uint64_t sfsr;
 395     sfsr = tc->readMiscReg(reg);
 396
 397     if (sfsr & 0x1)
 398         sfsr = 0x3;
 399     else
 400         sfsr = 1;
 401
 402     if (write)
 403         sfsr |= 1 << 2;
 404     sfsr |= ct << 4;
 405     if (se)
 406         sfsr |= 1 << 6;
 407     sfsr |= ft << 7;
 408     sfsr |= asi << 16;
 409     tc->setMiscRegWithEffect(reg, sfsr);
 410 }
 411
 412 void
 413 TLB::writeTagAccess(ThreadContext *tc, int reg, Addr va, int context)
 414 {
 415     DPRINTF(TLB, "TLB: Writing Tag Access: va: %#X ctx: %#X value: %#X\n",
 416             va, context, mbits(va, 63,13) | mbits(context,12,0));
 417
 418     tc->setMiscRegWithEffect(reg, mbits(va, 63,13) | mbits(context,12,0));
 419 }
 420
 421 void
 422 ITB::writeSfsr(ThreadContext *tc, bool write, ContextType ct,
 423         bool se, FaultTypes ft, int asi)
 424 {
 425     DPRINTF(TLB, "TLB: ITB Fault:  w=%d ct=%d ft=%d asi=%d\n",
 426              (int)write, ct, ft, asi);
 427     TLB::writeSfsr(tc, MISCREG_MMU_ITLB_SFSR, write, ct, se, ft, asi);
 428 }
 429
 430 void
 431 ITB::writeTagAccess(ThreadContext *tc, Addr va, int context)
 432 {
 433     TLB::writeTagAccess(tc, MISCREG_MMU_ITLB_TAG_ACCESS, va, context);
 434 }
 435
 436 void
 437 DTB::writeSfr(ThreadContext *tc, Addr a, bool write, ContextType ct,
 438         bool se, FaultTypes ft, int asi)
 439 {
 440     DPRINTF(TLB, "TLB: DTB Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n",
 441             a, (int)write, ct, ft, asi);
 442     TLB::writeSfsr(tc, MISCREG_MMU_DTLB_SFSR, write, ct, se, ft, asi);
 443     tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_SFAR, a);
 444 }
 445
 446 void
 447 DTB::writeTagAccess(ThreadContext *tc, Addr va, int context)
 448 {
 449     TLB::writeTagAccess(tc, MISCREG_MMU_DTLB_TAG_ACCESS, va, context);
 450 }
 451
 452
 453
 454 Fault
 455 ITB::translate(RequestPtr &req, ThreadContext *tc)
 456 {
 457     uint64_t tlbdata = tc->readMiscReg(MISCREG_TLB_DATA);
 458
 459     Addr vaddr = req->getVaddr();
 460     TlbEntry *e;
 461
 462     assert(req->getAsi() == ASI_IMPLICIT);
 463
 464     DPRINTF(TLB, "TLB: ITB Request to translate va=%#x size=%d\n",
 465             vaddr, req->getSize());
 466
 467     // Be fast if we can!
 468     if (cacheValid && cacheState == tlbdata) {
 469         if (cacheEntry) {
 470             if (cacheEntry->range.va < vaddr + sizeof(MachInst) &&
 471                 cacheEntry->range.va + cacheEntry->range.size >= vaddr) {
 472                     req->setPaddr(cacheEntry->pte.paddr() & ~(cacheEntry->pte.size()-1) |
 473                                   vaddr & cacheEntry->pte.size()-1 );
 474                     return NoFault;
 475             }
 476         } else {
 477             req->setPaddr(vaddr & PAddrImplMask);
 478             return NoFault;
 479         }
 480     }
 481
 482     bool hpriv = bits(tlbdata,0,0);
 483     bool red = bits(tlbdata,1,1);
 484     bool priv = bits(tlbdata,2,2);
 485     bool addr_mask = bits(tlbdata,3,3);
 486     bool lsu_im = bits(tlbdata,4,4);
 487
 488     int part_id = bits(tlbdata,15,8);
 489     int tl = bits(tlbdata,18,16);
 490     int pri_context = bits(tlbdata,47,32);
 491     int context;
 492     ContextType ct;
 493     int asi;
 494     bool real = false;
 495
 496     DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsuim:%d part_id: %#X\n",
 497            priv, hpriv, red, lsu_im, part_id);
 498
 499     if (tl > 0) {
 500         asi = ASI_N;
 501         ct = Nucleus;
 502         context = 0;
 503     } else {
 504         asi = ASI_P;
 505         ct = Primary;
 506         context = pri_context;
 507     }
 508
 509     if ( hpriv || red ) {
 510         cacheValid = true;
 511         cacheState = tlbdata;
 512         cacheEntry = NULL;
 513         req->setPaddr(vaddr & PAddrImplMask);
 514         return NoFault;
 515     }
 516
 517     // If the access is unaligned trap
 518     if (vaddr & 0x3) {
 519         writeSfsr(tc, false, ct, false, OtherFault, asi);
 520         return new MemAddressNotAligned;
 521     }
 522
 523     if (addr_mask)
 524         vaddr = vaddr & VAddrAMask;
 525
 526     if (!validVirtualAddress(vaddr, addr_mask)) {
 527         writeSfsr(tc, false, ct, false, VaOutOfRange, asi);
 528         return new InstructionAccessException;
 529     }
 530
 531     if (!lsu_im) {
 532         e = lookup(vaddr, part_id, true);
 533         real = true;
 534         context = 0;
 535     } else {
 536         e = lookup(vaddr, part_id, false, context);
 537     }
 538
 539     if (e == NULL || !e->valid) {
 540         writeTagAccess(tc, vaddr, context);
 541         if (real)
 542             return new InstructionRealTranslationMiss;
 543         else
 544             return new FastInstructionAccessMMUMiss;
 545     }
 546
 547     // were not priviledged accesing priv page
 548     if (!priv && e->pte.priv()) {
 549         writeTagAccess(tc, vaddr, context);
 550         writeSfsr(tc, false, ct, false, PrivViolation, asi);
 551         return new InstructionAccessException;
 552     }
 553
 554     // cache translation date for next translation
 555     cacheValid = true;
 556     cacheState = tlbdata;
 557     cacheEntry = e;
 558
 559     req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) |
 560                   vaddr & e->pte.size()-1 );
 561     DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
 562     return NoFault;
 563 }
 564
 565
 566
 567 Fault
 568 DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
 569 {
 570     /* @todo this could really use some profiling and fixing to make it faster! */
 571     uint64_t tlbdata = tc->readMiscReg(MISCREG_TLB_DATA);
 572     Addr vaddr = req->getVaddr();
 573     Addr size = req->getSize();
 574     ASI asi;
 575     asi = (ASI)req->getAsi();
 576     bool implicit = false;
 577     bool hpriv = bits(tlbdata,0,0);
 578
 579     DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n",
 580             vaddr, size, asi);
 581
 582     if (lookupTable.size() != 64 - freeList.size())
 583        panic("Lookup table size: %d tlb size: %d\n", lookupTable.size(),
 584                freeList.size());
 585     if (asi == ASI_IMPLICIT)
 586         implicit = true;
 587
 588     if (hpriv && implicit) {
 589         req->setPaddr(vaddr & PAddrImplMask);
 590         return NoFault;
 591     }
 592
 593     // Be fast if we can!
 594     if (cacheValid &&  cacheState == tlbdata) {
 595         if (cacheEntry[0] && cacheAsi[0] == asi && cacheEntry[0]->range.va < vaddr + size &&
 596             cacheEntry[0]->range.va + cacheEntry[0]->range.size > vaddr &&
 597             (!write || cacheEntry[0]->pte.writable())) {
 598                 req->setPaddr(cacheEntry[0]->pte.paddr() & ~(cacheEntry[0]->pte.size()-1) |
 599                               vaddr & cacheEntry[0]->pte.size()-1 );
 600                 return NoFault;
 601         }
 602         if (cacheEntry[1] && cacheAsi[1] == asi && cacheEntry[1]->range.va < vaddr + size &&
 603             cacheEntry[1]->range.va + cacheEntry[1]->range.size > vaddr &&
 604             (!write || cacheEntry[1]->pte.writable())) {
 605                 req->setPaddr(cacheEntry[1]->pte.paddr() & ~(cacheEntry[1]->pte.size()-1) |
 606                               vaddr & cacheEntry[1]->pte.size()-1 );
 607                 return NoFault;
 608         }
 609     }
 610
 611     bool red = bits(tlbdata,1,1);
 612     bool priv = bits(tlbdata,2,2);
 613     bool addr_mask = bits(tlbdata,3,3);
 614     bool lsu_dm = bits(tlbdata,5,5);
 615
 616     int part_id = bits(tlbdata,15,8);
 617     int tl = bits(tlbdata,18,16);
 618     int pri_context = bits(tlbdata,47,32);
 619     int sec_context = bits(tlbdata,63,48);
 620
 621     bool real = false;
 622     ContextType ct = Primary;
 623     int context = 0;
 624
 625     TlbEntry *e;
 626
 627     DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsudm:%d part_id: %#X\n",
 628            priv, hpriv, red, lsu_dm, part_id);
 629
 630     if (implicit) {
 631         if (tl > 0) {
 632             asi = ASI_N;
 633             ct = Nucleus;
 634             context = 0;
 635         } else {
 636             asi = ASI_P;
 637             ct = Primary;
 638             context = pri_context;
 639         }
 640     } else {
 641         // We need to check for priv level/asi priv
 642         if (!priv && !hpriv && !AsiIsUnPriv(asi)) {
 643             // It appears that context should be Nucleus in these cases?
 644             writeSfr(tc, vaddr, write, Nucleus, false, IllegalAsi, asi);
 645             return new PrivilegedAction;
 646         }
 647
 648         if (!hpriv && AsiIsHPriv(asi)) {
 649             writeSfr(tc, vaddr, write, Nucleus, false, IllegalAsi, asi);
 650             return new DataAccessException;
 651         }
 652
 653         if (AsiIsPrimary(asi)) {
 654             context = pri_context;
 655             ct = Primary;
 656         } else if (AsiIsSecondary(asi)) {
 657             context = sec_context;
 658             ct = Secondary;
 659         } else if (AsiIsNucleus(asi)) {
 660             ct = Nucleus;
 661             context = 0;
 662         } else {  // ????
 663             ct = Primary;
 664             context = pri_context;
 665         }
 666     }
 667
 668     if (!implicit && asi != ASI_P && asi != ASI_S) {
 669         if (AsiIsLittle(asi))
 670             panic("Little Endian ASIs not supported\n");
 671         if (AsiIsBlock(asi))
 672             panic("Block ASIs not supported\n");
 673         if (AsiIsNoFault(asi))
 674             panic("No Fault ASIs not supported\n");
 675
 676         if (AsiIsPartialStore(asi))
 677             panic("Partial Store ASIs not supported\n");
 678         if (AsiIsInterrupt(asi))
 679             panic("Interrupt ASIs not supported\n");
 680
 681         if (AsiIsMmu(asi))
 682             goto handleMmuRegAccess;
 683         if (AsiIsScratchPad(asi))
 684             goto handleScratchRegAccess;
 685         if (AsiIsQueue(asi))
 686             goto handleQueueRegAccess;
 687         if (AsiIsSparcError(asi))
 688             goto handleSparcErrorRegAccess;
 689
 690         if (!AsiIsReal(asi) && !AsiIsNucleus(asi) && !AsiIsAsIfUser(asi) &&
 691                 !AsiIsTwin(asi))
 692             panic("Accessing ASI %#X. Should we?\n", asi);
 693     }
 694
 695     // If the asi is unaligned trap
 696     if (vaddr & size-1) {
 697         writeSfr(tc, vaddr, false, ct, false, OtherFault, asi);
 698         return new MemAddressNotAligned;
 699     }
 700
 701     if (addr_mask)
 702         vaddr = vaddr & VAddrAMask;
 703
 704     if (!validVirtualAddress(vaddr, addr_mask)) {
 705         writeSfr(tc, vaddr, false, ct, true, VaOutOfRange, asi);
 706         return new DataAccessException;
 707     }
 708
 709
 710     if ((!lsu_dm && !hpriv && !red) || AsiIsReal(asi)) {
 711         real = true;
 712         context = 0;
 713     };
 714
 715     if (hpriv && (implicit || (!AsiIsAsIfUser(asi) && !AsiIsReal(asi)))) {
 716         req->setPaddr(vaddr & PAddrImplMask);
 717         return NoFault;
 718     }
 719
 720     e = lookup(vaddr, part_id, real, context);
 721
 722     if (e == NULL || !e->valid) {
 723         writeTagAccess(tc, vaddr, context);
 724         DPRINTF(TLB, "TLB: DTB Failed to find matching TLB entry\n");
 725         if (real)
 726             return new DataRealTranslationMiss;
 727         else
 728             return new FastDataAccessMMUMiss;
 729
 730     }
 731
 732     if (!priv && e->pte.priv()) {
 733         writeTagAccess(tc, vaddr, context);
 734         writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), PrivViolation, asi);
 735         return new DataAccessException;
 736     }
 737
 738     if (write && !e->pte.writable()) {
 739         writeTagAccess(tc, vaddr, context);
 740         writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), OtherFault, asi);
 741         return new FastDataAccessProtection;
 742     }
 743
 744     if (e->pte.nofault() && !AsiIsNoFault(asi)) {
 745         writeTagAccess(tc, vaddr, context);
 746         writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), LoadFromNfo, asi);
 747         return new DataAccessException;
 748     }
 749
 750     if (e->pte.sideffect() && AsiIsNoFault(asi)) {
 751         writeTagAccess(tc, vaddr, context);
 752         writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), SideEffect, asi);
 753         return new DataAccessException;
 754     }
 755
 756
 757     if (e->pte.sideffect())
 758         req->setFlags(req->getFlags() | UNCACHEABLE);
 759
 760     // cache translation date for next translation
 761     cacheState = tlbdata;
 762     if (!cacheValid) {
 763         cacheEntry[1] = NULL;
 764         cacheEntry[0] = NULL;
 765     }
 766
 767     if (cacheEntry[0] != e && cacheEntry[1] != e) {
 768         cacheEntry[1] = cacheEntry[0];
 769         cacheEntry[0] = e;
 770         cacheAsi[1] = cacheAsi[0];
 771         cacheAsi[0] = asi;
 772         if (implicit)
 773             cacheAsi[0] = (ASI)0;
 774     }
 775     cacheValid = true;
 776     req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) |
 777                   vaddr & e->pte.size()-1);
 778     DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
 779     return NoFault;
 780     /** Normal flow ends here. */
 781
 782 handleScratchRegAccess:
 783     if (vaddr > 0x38 || (vaddr >= 0x20 && vaddr < 0x30 && !hpriv)) {
 784         writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
 785         return new DataAccessException;
 786     }
 787     goto regAccessOk;
 788
 789 handleQueueRegAccess:
 790     if (!priv  && !hpriv) {
 791         writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
 792         return new PrivilegedAction;
 793     }
 794     if (!hpriv && vaddr & 0xF || vaddr > 0x3f8 || vaddr < 0x3c0) {
 795         writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
 796         return new DataAccessException;
 797     }
 798     goto regAccessOk;
 799
 800 handleSparcErrorRegAccess:
 801     if (!hpriv) {
 802         if (priv) {
 803             writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
 804             return new DataAccessException;
 805         } else {
 806             writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
 807             return new PrivilegedAction;
 808         }
 809     }
 810     goto regAccessOk;
 811
 812
 813 regAccessOk:
 814 handleMmuRegAccess:
 815     DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n");
 816     req->setMmapedIpr(true);
 817     req->setPaddr(req->getVaddr());
 818     return NoFault;
 819 };
 820
 821 Tick
 822 DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
 823 {
 824     Addr va = pkt->getAddr();
 825     ASI asi = (ASI)pkt->req->getAsi();
 826     uint64_t temp, data;
 827     uint64_t tsbtemp, cnftemp;
 828
 829     DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n",
 830          (uint32_t)pkt->req->getAsi(), pkt->getAddr());
 831
 832     switch (asi) {
 833       case ASI_LSU_CONTROL_REG:
 834         assert(va == 0);
 835         pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_LSU_CTRL));
 836         break;
 837       case ASI_MMU:
 838         switch (va) {
 839           case 0x8:
 840             pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT));
 841             break;
 842           case 0x10:
 843             pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_S_CONTEXT));
 844             break;
 845           default:
 846             goto doMmuReadError;
 847         }
 848         break;
 849       case ASI_QUEUE:
 850         pkt->set(tc->readMiscRegWithEffect(MISCREG_QUEUE_CPU_MONDO_HEAD +
 851                     (va >> 4) - 0x3c));
 852         break;
 853       case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0:
 854         assert(va == 0);
 855         pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0));
 856         break;
 857       case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1:
 858         assert(va == 0);
 859         pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1));
 860         break;
 861       case ASI_DMMU_CTXT_ZERO_CONFIG:
 862         assert(va == 0);
 863         pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG));
 864         break;
 865       case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0:
 866         assert(va == 0);
 867         pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0));
 868         break;
 869       case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1:
 870         assert(va == 0);
 871         pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1));
 872         break;
 873       case ASI_IMMU_CTXT_ZERO_CONFIG:
 874         assert(va == 0);
 875         pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG));
 876         break;
 877       case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0:
 878         assert(va == 0);
 879         pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0));
 880         break;
 881       case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1:
 882         assert(va == 0);
 883         pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1));
 884         break;
 885       case ASI_DMMU_CTXT_NONZERO_CONFIG:
 886         assert(va == 0);
 887         pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG));
 888         break;
 889       case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0:
 890         assert(va == 0);
 891         pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0));
 892         break;
 893       case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1:
 894         assert(va == 0);
 895         pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1));
 896         break;
 897       case ASI_IMMU_CTXT_NONZERO_CONFIG:
 898         assert(va == 0);
 899         pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG));
 900         break;
 901       case ASI_SPARC_ERROR_STATUS_REG:
 902         pkt->set((uint64_t)0);
 903         break;
 904       case ASI_HYP_SCRATCHPAD:
 905       case ASI_SCRATCHPAD:
 906         pkt->set(tc->readMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3)));
 907         break;
 908       case ASI_IMMU:
 909         switch (va) {
 910           case 0x0:
 911             temp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS);
 912             pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48);
 913             break;
 914           case 0x18:
 915             pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_SFSR));
 916             break;
 917           case 0x30:
 918             pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS));
 919             break;
 920           default:
 921             goto doMmuReadError;
 922         }
 923         break;
 924       case ASI_DMMU:
 925         switch (va) {
 926           case 0x0:
 927             temp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS);
 928             pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48);
 929             break;
 930           case 0x18:
 931             pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_SFSR));
 932             break;
 933           case 0x20:
 934             pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_SFAR));
 935             break;
 936           case 0x30:
 937             pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS));
 938             break;
 939           case 0x80:
 940             pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID));
 941             break;
 942           default:
 943                 goto doMmuReadError;
 944         }
 945         break;
 946       case ASI_DMMU_TSB_PS0_PTR_REG:
 947         temp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS);
 948         if (bits(temp,12,0) == 0) {
 949             tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0);
 950             cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG);
 951         } else {
 952             tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0);
 953             cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG);
 954         }
 955         data = mbits(tsbtemp,63,13);
 956         data |= temp >> (9 + bits(cnftemp,2,0) * 3) &
 957             mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4);
 958         pkt->set(data);
 959         break;
 960       case ASI_DMMU_TSB_PS1_PTR_REG:
 961         temp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS);
 962         if (bits(temp,12,0) == 0) {
 963             tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1);
 964             cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG);
 965         } else {
 966             tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1);
 967             cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG);
 968         }
 969         data = mbits(tsbtemp,63,13);
 970         if (bits(tsbtemp,12,12))
 971             data |= ULL(1) << (13+bits(tsbtemp,3,0));
 972         data |= temp >> (9 + bits(cnftemp,10,8) * 3) &
 973             mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4);
 974         pkt->set(data);
 975         break;
 976       case ASI_IMMU_TSB_PS0_PTR_REG:
 977         temp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS);
 978         if (bits(temp,12,0) == 0) {
 979             tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0);
 980             cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG);
 981         } else {
 982             tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0);
 983             cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG);
 984         }
 985         data = mbits(tsbtemp,63,13);
 986         data |= temp >> (9 + bits(cnftemp,2,0) * 3) &
 987             mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4);
 988         pkt->set(data);
 989         break;
 990       case ASI_IMMU_TSB_PS1_PTR_REG:
 991         temp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS);
 992         if (bits(temp,12,0) == 0) {
 993             tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1);
 994             cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG);
 995         } else {
 996             tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1);
 997             cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG);
 998         }
 999         data = mbits(tsbtemp,63,13);
1000         if (bits(tsbtemp,12,12))
1001             data |= ULL(1) << (13+bits(tsbtemp,3,0));
1002         data |= temp >> (9 + bits(cnftemp,10,8) * 3) &
1003             mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4);
1004         pkt->set(data);
1005         break;
1006
1007       default:
1008 doMmuReadError:
1009         panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n",
1010             (uint32_t)asi, va);
1011     }
1012     pkt->result = Packet::Success;
1013     return tc->getCpuPtr()->cycles(1);
1014 }
1015
1016 Tick
1017 DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
1018 {
1019     uint64_t data = gtoh(pkt->get<uint64_t>());
1020     Addr va = pkt->getAddr();
1021     ASI asi = (ASI)pkt->req->getAsi();
1022
1023     Addr ta_insert;
1024     Addr va_insert;
1025     Addr ct_insert;
1026     int part_insert;
1027     int entry_insert = -1;
1028     bool real_insert;
1029     bool ignore;
1030     int part_id;
1031     int ctx_id;
1032     PageTableEntry pte;
1033
1034     DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n",
1035          (uint32_t)asi, va, data);
1036
1037     switch (asi) {
1038       case ASI_LSU_CONTROL_REG:
1039         assert(va == 0);
1040         tc->setMiscRegWithEffect(MISCREG_MMU_LSU_CTRL, data);
1041         break;
1042       case ASI_MMU:
1043         switch (va) {
1044           case 0x8:
1045             tc->setMiscRegWithEffect(MISCREG_MMU_P_CONTEXT, data);
1046             break;
1047           case 0x10:
1048             tc->setMiscRegWithEffect(MISCREG_MMU_S_CONTEXT, data);
1049             break;
1050           default:
1051             goto doMmuWriteError;
1052         }
1053         break;
1054       case ASI_QUEUE:
1055         assert(mbits(data,13,6) == data);
1056         tc->setMiscRegWithEffect(MISCREG_QUEUE_CPU_MONDO_HEAD +
1057                     (va >> 4) - 0x3c, data);
1058         break;
1059       case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0:
1060         assert(va == 0);
1061         tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0, data);
1062         break;
1063       case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1:
1064         assert(va == 0);
1065         tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1, data);
1066         break;
1067       case ASI_DMMU_CTXT_ZERO_CONFIG:
1068         assert(va == 0);
1069         tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG, data);
1070         break;
1071       case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0:
1072         assert(va == 0);
1073         tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0, data);
1074         break;
1075       case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1:
1076         assert(va == 0);
1077         tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1, data);
1078         break;
1079       case ASI_IMMU_CTXT_ZERO_CONFIG:
1080         assert(va == 0);
1081         tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG, data);
1082         break;
1083       case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0:
1084         assert(va == 0);
1085         tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0, data);
1086         break;
1087       case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1:
1088         assert(va == 0);
1089         tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1, data);
1090         break;
1091       case ASI_DMMU_CTXT_NONZERO_CONFIG:
1092         assert(va == 0);
1093         tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG, data);
1094         break;
1095       case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0:
1096         assert(va == 0);
1097         tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0, data);
1098         break;
1099       case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1:
1100         assert(va == 0);
1101         tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1, data);
1102         break;
1103       case ASI_IMMU_CTXT_NONZERO_CONFIG:
1104         assert(va == 0);
1105         tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG, data);
1106         break;
1107       case ASI_SPARC_ERROR_EN_REG:
1108       case ASI_SPARC_ERROR_STATUS_REG:
1109         warn("Ignoring write to SPARC ERROR regsiter\n");
1110         break;
1111       case ASI_HYP_SCRATCHPAD:
1112       case ASI_SCRATCHPAD:
1113         tc->setMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3), data);
1114         break;
1115       case ASI_IMMU:
1116         switch (va) {
1117           case 0x18:
1118             tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_SFSR, data);
1119             break;
1120           case 0x30:
1121             sext<59>(bits(data, 59,0));
1122             tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS, data);
1123             break;
1124           default:
1125             goto doMmuWriteError;
1126         }
1127         break;
1128       case ASI_ITLB_DATA_ACCESS_REG:
1129         entry_insert = bits(va, 8,3);
1130       case ASI_ITLB_DATA_IN_REG:
1131         assert(entry_insert != -1 || mbits(va,10,9) == va);
1132         ta_insert = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS);
1133         va_insert = mbits(ta_insert, 63,13);
1134         ct_insert = mbits(ta_insert, 12,0);
1135         part_insert = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID);
1136         real_insert = bits(va, 9,9);
1137         pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v :
1138                 PageTableEntry::sun4u);
1139         tc->getITBPtr()->insert(va_insert, part_insert, ct_insert, real_insert,
1140                 pte, entry_insert);
1141         break;
1142       case ASI_DTLB_DATA_ACCESS_REG:
1143         entry_insert = bits(va, 8,3);
1144       case ASI_DTLB_DATA_IN_REG:
1145         assert(entry_insert != -1 || mbits(va,10,9) == va);
1146         ta_insert = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS);
1147         va_insert = mbits(ta_insert, 63,13);
1148         ct_insert = mbits(ta_insert, 12,0);
1149         part_insert = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID);
1150         real_insert = bits(va, 9,9);
1151         pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v :
1152                 PageTableEntry::sun4u);
1153         insert(va_insert, part_insert, ct_insert, real_insert, pte, entry_insert);
1154         break;
1155       case ASI_IMMU_DEMAP:
1156         ignore = false;
1157         ctx_id = -1;
1158         part_id =  tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID);
1159         switch (bits(va,5,4)) {
1160           case 0:
1161             ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT);
1162             break;
1163           case 1:
1164             ignore = true;
1165             break;
1166           case 3:
1167             ctx_id = 0;
1168             break;
1169           default:
1170             ignore = true;
1171         }
1172
1173         switch(bits(va,7,6)) {
1174           case 0: // demap page
1175             if (!ignore)
1176                 tc->getITBPtr()->demapPage(mbits(va,63,13), part_id,
1177                         bits(va,9,9), ctx_id);
1178             break;
1179           case 1: //demap context
1180             if (!ignore)
1181                 tc->getITBPtr()->demapContext(part_id, ctx_id);
1182             break;
1183           case 2:
1184             tc->getITBPtr()->demapAll(part_id);
1185             break;
1186           default:
1187             panic("Invalid type for IMMU demap\n");
1188         }
1189         break;
1190       case ASI_DMMU:
1191         switch (va) {
1192           case 0x18:
1193             tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_SFSR, data);
1194             break;
1195           case 0x30:
1196             sext<59>(bits(data, 59,0));
1197             tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS, data);
1198             break;
1199           case 0x80:
1200             tc->setMiscRegWithEffect(MISCREG_MMU_PART_ID, data);
1201             break;
1202           default:
1203             goto doMmuWriteError;
1204         }
1205         break;
1206       case ASI_DMMU_DEMAP:
1207         ignore = false;
1208         ctx_id = -1;
1209         part_id =  tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID);
1210         switch (bits(va,5,4)) {
1211           case 0:
1212             ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT);
1213             break;
1214           case 1:
1215             ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_S_CONTEXT);
1216             break;
1217           case 3:
1218             ctx_id = 0;
1219             break;
1220           default:
1221             ignore = true;
1222         }
1223
1224         switch(bits(va,7,6)) {
1225           case 0: // demap page
1226             if (!ignore)
1227                 demapPage(mbits(va,63,13), part_id, bits(va,9,9), ctx_id);
1228             break;
1229           case 1: //demap context
1230             if (!ignore)
1231                 demapContext(part_id, ctx_id);
1232             break;
1233           case 2:
1234             demapAll(part_id);
1235             break;
1236           default:
1237             panic("Invalid type for IMMU demap\n");
1238         }
1239         break;
1240       default:
1241 doMmuWriteError:
1242         panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n",
1243             (uint32_t)pkt->req->getAsi(), pkt->getAddr(), data);
1244     }
1245     pkt->result = Packet::Success;
1246     return tc->getCpuPtr()->cycles(1);
1247 }
1248
1249 void
1250 TLB::serialize(std::ostream &os)
1251 {
1252     SERIALIZE_SCALAR(size);
1253     SERIALIZE_SCALAR(usedEntries);
1254     SERIALIZE_SCALAR(lastReplaced);
1255
1256     // convert the pointer based free list into an index based one
1257     int *free_list = (int*)malloc(sizeof(int) * size);
1258     int cntr = 0;
1259     std::list<TlbEntry*>::iterator i;
1260     i = freeList.begin();
1261     while (i != freeList.end()) {
1262         free_list[cntr++] = ((size_t)*i - (size_t)tlb)/ sizeof(TlbEntry);
1263         i++;
1264     }
1265     SERIALIZE_SCALAR(cntr);
1266     SERIALIZE_ARRAY(free_list,  cntr);
1267
1268     for (int x = 0; x < size; x++) {
1269         nameOut(os, csprintf("%s.PTE%d", name(), x));
1270         tlb[x].serialize(os);
1271     }
1272 }
1273
1274 void
1275 TLB::unserialize(Checkpoint *cp, const std::string &section)
1276 {
1277     int oldSize;
1278
1279     paramIn(cp, section, "size", oldSize);
1280     if (oldSize != size)
1281         panic("Don't support unserializing different sized TLBs\n");
1282     UNSERIALIZE_SCALAR(usedEntries);
1283     UNSERIALIZE_SCALAR(lastReplaced);
1284
1285     int cntr;
1286     UNSERIALIZE_SCALAR(cntr);
1287
1288     int *free_list = (int*)malloc(sizeof(int) * cntr);
1289     freeList.clear();
1290     UNSERIALIZE_ARRAY(free_list,  cntr);
1291     for (int x = 0; x < cntr; x++)
1292         freeList.push_back(&tlb[free_list[x]]);
1293
1294     lookupTable.clear();
1295     for (int x = 0; x < size; x++) {
1296         tlb[x].unserialize(cp, csprintf("%s.PTE%d", section, x));
1297         if (tlb[x].valid)
1298             lookupTable.insert(tlb[x].range, &tlb[x]);
1299
1300     }
1301 }
1302
1303
1304 DEFINE_SIM_OBJECT_CLASS_NAME("SparcTLB", TLB)
1305
1306 BEGIN_DECLARE_SIM_OBJECT_PARAMS(ITB)
1307
1308     Param<int> size;
1309
1310 END_DECLARE_SIM_OBJECT_PARAMS(ITB)
1311
1312 BEGIN_INIT_SIM_OBJECT_PARAMS(ITB)
1313
1314     INIT_PARAM_DFLT(size, "TLB size", 48)
1315
1316 END_INIT_SIM_OBJECT_PARAMS(ITB)
1317
1318
1319 CREATE_SIM_OBJECT(ITB)
1320 {
1321     return new ITB(getInstanceName(), size);
1322 }
1323
1324 REGISTER_SIM_OBJECT("SparcITB", ITB)
1325
1326 BEGIN_DECLARE_SIM_OBJECT_PARAMS(DTB)
1327
1328     Param<int> size;
1329
1330 END_DECLARE_SIM_OBJECT_PARAMS(DTB)
1331
1332 BEGIN_INIT_SIM_OBJECT_PARAMS(DTB)
1333
1334     INIT_PARAM_DFLT(size, "TLB size", 64)
1335
1336 END_INIT_SIM_OBJECT_PARAMS(DTB)
1337
1338
1339 CREATE_SIM_OBJECT(DTB)
1340 {
1341     return new DTB(getInstanceName(), size);
1342 }
1343
1344 REGISTER_SIM_OBJECT("SparcDTB", DTB)
1345 }