src/arch/sparc/tlb.cc

   1 /*
   2  * Copyright (c) 2001-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Ali Saidi
  29  */
  30
  31 #include <cstring>
  32
  33 #include "arch/sparc/asi.hh"
  34 #include "arch/sparc/miscregfile.hh"
  35 #include "arch/sparc/tlb.hh"
  36 #include "base/bitfield.hh"
  37 #include "base/trace.hh"
  38 #include "cpu/thread_context.hh"
  39 #include "cpu/base.hh"
  40 #include "mem/packet_access.hh"
  41 #include "mem/request.hh"
  42 #include "sim/builder.hh"
  43 #include "sim/system.hh"
  44
  45 /* @todo remove some of the magic constants.  -- ali
  46  * */
  47 namespace SparcISA {
  48
  49 TLB::TLB(const std::string &name, int s)
  50     : SimObject(name), size(s), usedEntries(0), lastReplaced(0),
  51       cacheValid(false)
  52 {
  53     // To make this work you'll have to change the hypervisor and OS
  54     if (size > 64)
  55         fatal("SPARC T1 TLB registers don't support more than 64 TLB entries.");
  56
  57     tlb = new TlbEntry[size];
  58     std::memset(tlb, 0, sizeof(TlbEntry) * size);
  59
  60     for (int x = 0; x < size; x++)
  61         freeList.push_back(&tlb[x]);
  62 }
  63
  64 void
  65 TLB::clearUsedBits()
  66 {
  67     MapIter i;
  68     for (i = lookupTable.begin(); i != lookupTable.end(); i++) {
  69         TlbEntry *t = i->second;
  70         if (!t->pte.locked()) {
  71             t->used = false;
  72             usedEntries--;
  73         }
  74     }
  75 }
  76
  77
  78 void
  79 TLB::insert(Addr va, int partition_id, int context_id, bool real,
  80         const PageTableEntry& PTE, int entry)
  81 {
  82
  83
  84     MapIter i;
  85     TlbEntry *new_entry = NULL;
  86 //    TlbRange tr;
  87     int x;
  88
  89     cacheValid = false;
  90     va &= ~(PTE.size()-1);
  91  /*   tr.va = va;
  92     tr.size = PTE.size() - 1;
  93     tr.contextId = context_id;
  94     tr.partitionId = partition_id;
  95     tr.real = real;
  96 */
  97
  98     DPRINTF(TLB, "TLB: Inserting TLB Entry; va=%#x pa=%#x pid=%d cid=%d r=%d entryid=%d\n",
  99             va, PTE.paddr(), partition_id, context_id, (int)real, entry);
 100
 101     // Demap any entry that conflicts
 102     for (x = 0; x < size; x++) {
 103         if (tlb[x].range.real == real &&
 104             tlb[x].range.partitionId == partition_id &&
 105             tlb[x].range.va < va + PTE.size() - 1 &&
 106             tlb[x].range.va + tlb[x].range.size >= va &&
 107             (real || tlb[x].range.contextId == context_id ))
 108         {
 109             if (tlb[x].valid) {
 110                 freeList.push_front(&tlb[x]);
 111                 DPRINTF(TLB, "TLB: Conflicting entry %#X , deleting it\n", x);
 112
 113                 tlb[x].valid = false;
 114                 if (tlb[x].used) {
 115                     tlb[x].used = false;
 116                     usedEntries--;
 117                 }
 118                 lookupTable.erase(tlb[x].range);
 119             }
 120         }
 121     }
 122
 123
 124 /*
 125     i = lookupTable.find(tr);
 126     if (i != lookupTable.end()) {
 127         i->second->valid = false;
 128         if (i->second->used) {
 129             i->second->used = false;
 130             usedEntries--;
 131         }
 132         freeList.push_front(i->second);
 133         DPRINTF(TLB, "TLB: Found conflicting entry %#X , deleting it\n",
 134                 i->second);
 135         lookupTable.erase(i);
 136     }
 137 */
 138
 139     if (entry != -1) {
 140         assert(entry < size && entry >= 0);
 141         new_entry = &tlb[entry];
 142     } else {
 143         if (!freeList.empty()) {
 144             new_entry = freeList.front();
 145         } else {
 146             x = lastReplaced;
 147             do {
 148                 ++x;
 149                 if (x == size)
 150                     x = 0;
 151                 if (x == lastReplaced)
 152                     goto insertAllLocked;
 153             } while (tlb[x].pte.locked());
 154             lastReplaced = x;
 155             new_entry = &tlb[x];
 156         }
 157         /*
 158         for (x = 0; x < size; x++) {
 159             if (!tlb[x].valid || !tlb[x].used)  {
 160                 new_entry = &tlb[x];
 161                 break;
 162             }
 163         }*/
 164     }
 165
 166 insertAllLocked:
 167     // Update the last ently if their all locked
 168     if (!new_entry) {
 169         new_entry = &tlb[size-1];
 170     }
 171
 172     freeList.remove(new_entry);
 173     if (new_entry->valid && new_entry->used)
 174         usedEntries--;
 175     if (new_entry->valid)
 176         lookupTable.erase(new_entry->range);
 177
 178
 179     assert(PTE.valid());
 180     new_entry->range.va = va;
 181     new_entry->range.size = PTE.size() - 1;
 182     new_entry->range.partitionId = partition_id;
 183     new_entry->range.contextId = context_id;
 184     new_entry->range.real = real;
 185     new_entry->pte = PTE;
 186     new_entry->used = true;;
 187     new_entry->valid = true;
 188     usedEntries++;
 189
 190
 191
 192     i = lookupTable.insert(new_entry->range, new_entry);
 193     assert(i != lookupTable.end());
 194
 195     // If all entries have there used bit set, clear it on them all, but the
 196     // one we just inserted
 197     if (usedEntries == size) {
 198         clearUsedBits();
 199         new_entry->used = true;
 200         usedEntries++;
 201     }
 202
 203 }
 204
 205
 206 TlbEntry*
 207 TLB::lookup(Addr va, int partition_id, bool real, int context_id, bool
 208         update_used)
 209 {
 210     MapIter i;
 211     TlbRange tr;
 212     TlbEntry *t;
 213
 214     DPRINTF(TLB, "TLB: Looking up entry va=%#x pid=%d cid=%d r=%d\n",
 215             va, partition_id, context_id, real);
 216     // Assemble full address structure
 217     tr.va = va;
 218     tr.size = MachineBytes;
 219     tr.contextId = context_id;
 220     tr.partitionId = partition_id;
 221     tr.real = real;
 222
 223     // Try to find the entry
 224     i = lookupTable.find(tr);
 225     if (i == lookupTable.end()) {
 226         DPRINTF(TLB, "TLB: No valid entry found\n");
 227         return NULL;
 228     }
 229
 230     // Mark the entries used bit and clear other used bits in needed
 231     t = i->second;
 232     DPRINTF(TLB, "TLB: Valid entry found pa: %#x size: %#x\n", t->pte.paddr(),
 233             t->pte.size());
 234
 235     // Update the used bits only if this is a real access (not a fake one from
 236     // virttophys()
 237     if (!t->used && update_used) {
 238         t->used = true;
 239         usedEntries++;
 240         if (usedEntries == size) {
 241             clearUsedBits();
 242             t->used = true;
 243             usedEntries++;
 244         }
 245     }
 246
 247     return t;
 248 }
 249
 250 void
 251 TLB::dumpAll()
 252 {
 253     MapIter i;
 254     for (int x = 0; x < size; x++) {
 255         if (tlb[x].valid) {
 256            DPRINTFN("%4d:  %#2x:%#2x %c %#4x %#8x %#8x %#16x\n",
 257                    x, tlb[x].range.partitionId, tlb[x].range.contextId,
 258                    tlb[x].range.real ? 'R' : ' ', tlb[x].range.size,
 259                    tlb[x].range.va, tlb[x].pte.paddr(), tlb[x].pte());
 260         }
 261     }
 262 }
 263
 264 void
 265 TLB::demapPage(Addr va, int partition_id, bool real, int context_id)
 266 {
 267     TlbRange tr;
 268     MapIter i;
 269
 270     DPRINTF(IPR, "TLB: Demapping Page va=%#x pid=%#d cid=%d r=%d\n",
 271             va, partition_id, context_id, real);
 272
 273     cacheValid = false;
 274
 275     // Assemble full address structure
 276     tr.va = va;
 277     tr.size = MachineBytes;
 278     tr.contextId = context_id;
 279     tr.partitionId = partition_id;
 280     tr.real = real;
 281
 282     // Demap any entry that conflicts
 283     i = lookupTable.find(tr);
 284     if (i != lookupTable.end()) {
 285         DPRINTF(IPR, "TLB: Demapped page\n");
 286         i->second->valid = false;
 287         if (i->second->used) {
 288             i->second->used = false;
 289             usedEntries--;
 290         }
 291         freeList.push_front(i->second);
 292         lookupTable.erase(i);
 293     }
 294 }
 295
 296 void
 297 TLB::demapContext(int partition_id, int context_id)
 298 {
 299     int x;
 300     DPRINTF(IPR, "TLB: Demapping Context pid=%#d cid=%d\n",
 301             partition_id, context_id);
 302     cacheValid = false;
 303     for (x = 0; x < size; x++) {
 304         if (tlb[x].range.contextId == context_id &&
 305             tlb[x].range.partitionId == partition_id) {
 306             if (tlb[x].valid == true) {
 307                 freeList.push_front(&tlb[x]);
 308             }
 309             tlb[x].valid = false;
 310             if (tlb[x].used) {
 311                 tlb[x].used = false;
 312                 usedEntries--;
 313             }
 314             lookupTable.erase(tlb[x].range);
 315         }
 316     }
 317 }
 318
 319 void
 320 TLB::demapAll(int partition_id)
 321 {
 322     int x;
 323     DPRINTF(TLB, "TLB: Demapping All pid=%#d\n", partition_id);
 324     cacheValid = false;
 325     for (x = 0; x < size; x++) {
 326         if (!tlb[x].pte.locked() && tlb[x].range.partitionId == partition_id) {
 327             if (tlb[x].valid == true){
 328                 freeList.push_front(&tlb[x]);
 329             }
 330             tlb[x].valid = false;
 331             if (tlb[x].used) {
 332                 tlb[x].used = false;
 333                 usedEntries--;
 334             }
 335             lookupTable.erase(tlb[x].range);
 336         }
 337     }
 338 }
 339
 340 void
 341 TLB::invalidateAll()
 342 {
 343     int x;
 344     cacheValid = false;
 345
 346     freeList.clear();
 347     lookupTable.clear();
 348     for (x = 0; x < size; x++) {
 349         if (tlb[x].valid == true)
 350             freeList.push_back(&tlb[x]);
 351         tlb[x].valid = false;
 352         tlb[x].used = false;
 353     }
 354     usedEntries = 0;
 355 }
 356
 357 uint64_t
 358 TLB::TteRead(int entry) {
 359     if (entry >= size)
 360         panic("entry: %d\n", entry);
 361
 362     assert(entry < size);
 363     if (tlb[entry].valid)
 364         return tlb[entry].pte();
 365     else
 366         return (uint64_t)-1ll;
 367 }
 368
 369 uint64_t
 370 TLB::TagRead(int entry) {
 371     assert(entry < size);
 372     uint64_t tag;
 373     if (!tlb[entry].valid)
 374         return (uint64_t)-1ll;
 375
 376     tag = tlb[entry].range.contextId;
 377     tag |= tlb[entry].range.va;
 378     tag |= (uint64_t)tlb[entry].range.partitionId << 61;
 379     tag |= tlb[entry].range.real ? ULL(1) << 60 : 0;
 380     tag |= (uint64_t)~tlb[entry].pte._size() << 56;
 381     return tag;
 382 }
 383
 384 bool
 385 TLB::validVirtualAddress(Addr va, bool am)
 386 {
 387     if (am)
 388         return true;
 389     if (va >= StartVAddrHole && va <= EndVAddrHole)
 390         return false;
 391     return true;
 392 }
 393
 394 void
 395 TLB::writeSfsr(ThreadContext *tc, int reg,  bool write, ContextType ct,
 396         bool se, FaultTypes ft, int asi)
 397 {
 398     uint64_t sfsr;
 399     sfsr = tc->readMiscRegNoEffect(reg);
 400
 401     if (sfsr & 0x1)
 402         sfsr = 0x3;
 403     else
 404         sfsr = 1;
 405
 406     if (write)
 407         sfsr |= 1 << 2;
 408     sfsr |= ct << 4;
 409     if (se)
 410         sfsr |= 1 << 6;
 411     sfsr |= ft << 7;
 412     sfsr |= asi << 16;
 413     tc->setMiscReg(reg, sfsr);
 414 }
 415
 416 void
 417 TLB::writeTagAccess(ThreadContext *tc, int reg, Addr va, int context)
 418 {
 419     DPRINTF(TLB, "TLB: Writing Tag Access: va: %#X ctx: %#X value: %#X\n",
 420             va, context, mbits(va, 63,13) | mbits(context,12,0));
 421
 422     tc->setMiscReg(reg, mbits(va, 63,13) | mbits(context,12,0));
 423 }
 424
 425 void
 426 ITB::writeSfsr(ThreadContext *tc, bool write, ContextType ct,
 427         bool se, FaultTypes ft, int asi)
 428 {
 429     DPRINTF(TLB, "TLB: ITB Fault:  w=%d ct=%d ft=%d asi=%d\n",
 430              (int)write, ct, ft, asi);
 431     TLB::writeSfsr(tc, MISCREG_MMU_ITLB_SFSR, write, ct, se, ft, asi);
 432 }
 433
 434 void
 435 ITB::writeTagAccess(ThreadContext *tc, Addr va, int context)
 436 {
 437     TLB::writeTagAccess(tc, MISCREG_MMU_ITLB_TAG_ACCESS, va, context);
 438 }
 439
 440 void
 441 DTB::writeSfr(ThreadContext *tc, Addr a, bool write, ContextType ct,
 442         bool se, FaultTypes ft, int asi)
 443 {
 444     DPRINTF(TLB, "TLB: DTB Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n",
 445             a, (int)write, ct, ft, asi);
 446     TLB::writeSfsr(tc, MISCREG_MMU_DTLB_SFSR, write, ct, se, ft, asi);
 447     tc->setMiscReg(MISCREG_MMU_DTLB_SFAR, a);
 448 }
 449
 450 void
 451 DTB::writeTagAccess(ThreadContext *tc, Addr va, int context)
 452 {
 453     TLB::writeTagAccess(tc, MISCREG_MMU_DTLB_TAG_ACCESS, va, context);
 454 }
 455
 456
 457
 458 Fault
 459 ITB::translate(RequestPtr &req, ThreadContext *tc)
 460 {
 461     uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA);
 462
 463     Addr vaddr = req->getVaddr();
 464     TlbEntry *e;
 465
 466     assert(req->getAsi() == ASI_IMPLICIT);
 467
 468     DPRINTF(TLB, "TLB: ITB Request to translate va=%#x size=%d\n",
 469             vaddr, req->getSize());
 470
 471     // Be fast if we can!
 472     if (cacheValid && cacheState == tlbdata) {
 473         if (cacheEntry) {
 474             if (cacheEntry->range.va < vaddr + sizeof(MachInst) &&
 475                 cacheEntry->range.va + cacheEntry->range.size >= vaddr) {
 476                     req->setPaddr(cacheEntry->pte.paddr() & ~(cacheEntry->pte.size()-1) |
 477                                   vaddr & cacheEntry->pte.size()-1 );
 478                     return NoFault;
 479             }
 480         } else {
 481             req->setPaddr(vaddr & PAddrImplMask);
 482             return NoFault;
 483         }
 484     }
 485
 486     bool hpriv = bits(tlbdata,0,0);
 487     bool red = bits(tlbdata,1,1);
 488     bool priv = bits(tlbdata,2,2);
 489     bool addr_mask = bits(tlbdata,3,3);
 490     bool lsu_im = bits(tlbdata,4,4);
 491
 492     int part_id = bits(tlbdata,15,8);
 493     int tl = bits(tlbdata,18,16);
 494     int pri_context = bits(tlbdata,47,32);
 495     int context;
 496     ContextType ct;
 497     int asi;
 498     bool real = false;
 499
 500     DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsuim:%d part_id: %#X\n",
 501            priv, hpriv, red, lsu_im, part_id);
 502
 503     if (tl > 0) {
 504         asi = ASI_N;
 505         ct = Nucleus;
 506         context = 0;
 507     } else {
 508         asi = ASI_P;
 509         ct = Primary;
 510         context = pri_context;
 511     }
 512
 513     if ( hpriv || red ) {
 514         cacheValid = true;
 515         cacheState = tlbdata;
 516         cacheEntry = NULL;
 517         req->setPaddr(vaddr & PAddrImplMask);
 518         return NoFault;
 519     }
 520
 521     // If the access is unaligned trap
 522     if (vaddr & 0x3) {
 523         writeSfsr(tc, false, ct, false, OtherFault, asi);
 524         return new MemAddressNotAligned;
 525     }
 526
 527     if (addr_mask)
 528         vaddr = vaddr & VAddrAMask;
 529
 530     if (!validVirtualAddress(vaddr, addr_mask)) {
 531         writeSfsr(tc, false, ct, false, VaOutOfRange, asi);
 532         return new InstructionAccessException;
 533     }
 534
 535     if (!lsu_im) {
 536         e = lookup(vaddr, part_id, true);
 537         real = true;
 538         context = 0;
 539     } else {
 540         e = lookup(vaddr, part_id, false, context);
 541     }
 542
 543     if (e == NULL || !e->valid) {
 544         writeTagAccess(tc, vaddr, context);
 545         if (real)
 546             return new InstructionRealTranslationMiss;
 547         else
 548             return new FastInstructionAccessMMUMiss;
 549     }
 550
 551     // were not priviledged accesing priv page
 552     if (!priv && e->pte.priv()) {
 553         writeTagAccess(tc, vaddr, context);
 554         writeSfsr(tc, false, ct, false, PrivViolation, asi);
 555         return new InstructionAccessException;
 556     }
 557
 558     // cache translation date for next translation
 559     cacheValid = true;
 560     cacheState = tlbdata;
 561     cacheEntry = e;
 562
 563     req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) |
 564                   vaddr & e->pte.size()-1 );
 565     DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
 566     return NoFault;
 567 }
 568
 569
 570
 571 Fault
 572 DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
 573 {
 574     /* @todo this could really use some profiling and fixing to make it faster! */
 575     uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA);
 576     Addr vaddr = req->getVaddr();
 577     Addr size = req->getSize();
 578     ASI asi;
 579     asi = (ASI)req->getAsi();
 580     bool implicit = false;
 581     bool hpriv = bits(tlbdata,0,0);
 582
 583     DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n",
 584             vaddr, size, asi);
 585
 586     if (lookupTable.size() != 64 - freeList.size())
 587        panic("Lookup table size: %d tlb size: %d\n", lookupTable.size(),
 588                freeList.size());
 589     if (asi == ASI_IMPLICIT)
 590         implicit = true;
 591
 592     if (hpriv && implicit) {
 593         req->setPaddr(vaddr & PAddrImplMask);
 594         return NoFault;
 595     }
 596
 597     // Be fast if we can!
 598     if (cacheValid &&  cacheState == tlbdata) {
 599
 600
 601
 602   if (cacheEntry[0]) {
 603             TlbEntry *ce = cacheEntry[0];
 604            Addr ce_va = ce->range.va;
 605             if (cacheAsi[0] == asi &&
 606                 ce_va < vaddr + size && ce_va + ce->range.size > vaddr &&
 607                 (!write || ce->pte.writable())) {
 608                     req->setPaddr(ce->pte.paddrMask() | vaddr & ce->pte.sizeMask());
 609                     if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1)
 610                         req->setFlags(req->getFlags() | UNCACHEABLE);
 611                     DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
 612                     return NoFault;
 613             } // if matched
 614         } // if cache entry valid
 615         if (cacheEntry[1]) {
 616             TlbEntry *ce = cacheEntry[1];
 617             Addr ce_va = ce->range.va;
 618             if (cacheAsi[1] == asi &&
 619                 ce_va < vaddr + size && ce_va + ce->range.size > vaddr &&
 620                 (!write || ce->pte.writable())) {
 621                     req->setPaddr(ce->pte.paddrMask() | vaddr & ce->pte.sizeMask());
 622                     if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1)
 623                         req->setFlags(req->getFlags() | UNCACHEABLE);
 624                     DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
 625                     return NoFault;
 626             } // if matched
 627         } // if cache entry valid
 628      }
 629
 630     bool red = bits(tlbdata,1,1);
 631     bool priv = bits(tlbdata,2,2);
 632     bool addr_mask = bits(tlbdata,3,3);
 633     bool lsu_dm = bits(tlbdata,5,5);
 634
 635     int part_id = bits(tlbdata,15,8);
 636     int tl = bits(tlbdata,18,16);
 637     int pri_context = bits(tlbdata,47,32);
 638     int sec_context = bits(tlbdata,63,48);
 639
 640     bool real = false;
 641     ContextType ct = Primary;
 642     int context = 0;
 643
 644     TlbEntry *e;
 645
 646     DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsudm:%d part_id: %#X\n",
 647            priv, hpriv, red, lsu_dm, part_id);
 648
 649     if (implicit) {
 650         if (tl > 0) {
 651             asi = ASI_N;
 652             ct = Nucleus;
 653             context = 0;
 654         } else {
 655             asi = ASI_P;
 656             ct = Primary;
 657             context = pri_context;
 658         }
 659     } else {
 660         // We need to check for priv level/asi priv
 661         if (!priv && !hpriv && !AsiIsUnPriv(asi)) {
 662             // It appears that context should be Nucleus in these cases?
 663             writeSfr(tc, vaddr, write, Nucleus, false, IllegalAsi, asi);
 664             return new PrivilegedAction;
 665         }
 666
 667         if (!hpriv && AsiIsHPriv(asi)) {
 668             writeSfr(tc, vaddr, write, Nucleus, false, IllegalAsi, asi);
 669             return new DataAccessException;
 670         }
 671
 672         if (AsiIsPrimary(asi)) {
 673             context = pri_context;
 674             ct = Primary;
 675         } else if (AsiIsSecondary(asi)) {
 676             context = sec_context;
 677             ct = Secondary;
 678         } else if (AsiIsNucleus(asi)) {
 679             ct = Nucleus;
 680             context = 0;
 681         } else {  // ????
 682             ct = Primary;
 683             context = pri_context;
 684         }
 685     }
 686
 687     if (!implicit && asi != ASI_P && asi != ASI_S) {
 688         if (AsiIsLittle(asi))
 689             panic("Little Endian ASIs not supported\n");
 690         if (AsiIsNoFault(asi))
 691             panic("No Fault ASIs not supported\n");
 692
 693         if (AsiIsPartialStore(asi))
 694             panic("Partial Store ASIs not supported\n");
 695
 696         if (AsiIsCmt(asi))
 697             panic("Cmt ASI registers not implmented\n");
 698
 699         if (AsiIsInterrupt(asi))
 700             goto handleIntRegAccess;
 701         if (AsiIsMmu(asi))
 702             goto handleMmuRegAccess;
 703         if (AsiIsScratchPad(asi))
 704             goto handleScratchRegAccess;
 705         if (AsiIsQueue(asi))
 706             goto handleQueueRegAccess;
 707         if (AsiIsSparcError(asi))
 708             goto handleSparcErrorRegAccess;
 709
 710         if (!AsiIsReal(asi) && !AsiIsNucleus(asi) && !AsiIsAsIfUser(asi) &&
 711                 !AsiIsTwin(asi) && !AsiIsBlock(asi))
 712             panic("Accessing ASI %#X. Should we?\n", asi);
 713     }
 714
 715     // If the asi is unaligned trap
 716     if (vaddr & size-1) {
 717         writeSfr(tc, vaddr, false, ct, false, OtherFault, asi);
 718         return new MemAddressNotAligned;
 719     }
 720
 721     if (addr_mask)
 722         vaddr = vaddr & VAddrAMask;
 723
 724     if (!validVirtualAddress(vaddr, addr_mask)) {
 725         writeSfr(tc, vaddr, false, ct, true, VaOutOfRange, asi);
 726         return new DataAccessException;
 727     }
 728
 729
 730     if ((!lsu_dm && !hpriv && !red) || AsiIsReal(asi)) {
 731         real = true;
 732         context = 0;
 733     };
 734
 735     if (hpriv && (implicit || (!AsiIsAsIfUser(asi) && !AsiIsReal(asi)))) {
 736         req->setPaddr(vaddr & PAddrImplMask);
 737         return NoFault;
 738     }
 739
 740     e = lookup(vaddr, part_id, real, context);
 741
 742     if (e == NULL || !e->valid) {
 743         writeTagAccess(tc, vaddr, context);
 744         DPRINTF(TLB, "TLB: DTB Failed to find matching TLB entry\n");
 745         if (real)
 746             return new DataRealTranslationMiss;
 747         else
 748             return new FastDataAccessMMUMiss;
 749
 750     }
 751
 752     if (!priv && e->pte.priv()) {
 753         writeTagAccess(tc, vaddr, context);
 754         writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), PrivViolation, asi);
 755         return new DataAccessException;
 756     }
 757
 758     if (write && !e->pte.writable()) {
 759         writeTagAccess(tc, vaddr, context);
 760         writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), OtherFault, asi);
 761         return new FastDataAccessProtection;
 762     }
 763
 764     if (e->pte.nofault() && !AsiIsNoFault(asi)) {
 765         writeTagAccess(tc, vaddr, context);
 766         writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), LoadFromNfo, asi);
 767         return new DataAccessException;
 768     }
 769
 770     if (e->pte.sideffect() && AsiIsNoFault(asi)) {
 771         writeTagAccess(tc, vaddr, context);
 772         writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), SideEffect, asi);
 773         return new DataAccessException;
 774     }
 775
 776
 777     if (e->pte.sideffect() || (e->pte.paddr() >> 39) & 1)
 778         req->setFlags(req->getFlags() | UNCACHEABLE);
 779
 780     // cache translation date for next translation
 781     cacheState = tlbdata;
 782     if (!cacheValid) {
 783         cacheEntry[1] = NULL;
 784         cacheEntry[0] = NULL;
 785     }
 786
 787     if (cacheEntry[0] != e && cacheEntry[1] != e) {
 788         cacheEntry[1] = cacheEntry[0];
 789         cacheEntry[0] = e;
 790         cacheAsi[1] = cacheAsi[0];
 791         cacheAsi[0] = asi;
 792         if (implicit)
 793             cacheAsi[0] = (ASI)0;
 794     }
 795     cacheValid = true;
 796     req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) |
 797                   vaddr & e->pte.size()-1);
 798     DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
 799     return NoFault;
 800
 801     /** Normal flow ends here. */
 802 handleIntRegAccess:
 803     if (!hpriv) {
 804         writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
 805         if (priv)
 806             return new DataAccessException;
 807          else
 808             return new PrivilegedAction;
 809     }
 810
 811     if (asi == ASI_SWVR_UDB_INTR_W && !write ||
 812                     asi == ASI_SWVR_UDB_INTR_R && write) {
 813         writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
 814         return new DataAccessException;
 815     }
 816
 817     goto regAccessOk;
 818
 819
 820 handleScratchRegAccess:
 821     if (vaddr > 0x38 || (vaddr >= 0x20 && vaddr < 0x30 && !hpriv)) {
 822         writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
 823         return new DataAccessException;
 824     }
 825     goto regAccessOk;
 826
 827 handleQueueRegAccess:
 828     if (!priv  && !hpriv) {
 829         writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
 830         return new PrivilegedAction;
 831     }
 832     if (!hpriv && vaddr & 0xF || vaddr > 0x3f8 || vaddr < 0x3c0) {
 833         writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
 834         return new DataAccessException;
 835     }
 836     goto regAccessOk;
 837
 838 handleSparcErrorRegAccess:
 839     if (!hpriv) {
 840         writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
 841         if (priv)
 842             return new DataAccessException;
 843          else
 844             return new PrivilegedAction;
 845     }
 846     goto regAccessOk;
 847
 848
 849 regAccessOk:
 850 handleMmuRegAccess:
 851     DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n");
 852     req->setMmapedIpr(true);
 853     req->setPaddr(req->getVaddr());
 854     return NoFault;
 855 };
 856
 857 Tick
 858 DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
 859 {
 860     Addr va = pkt->getAddr();
 861     ASI asi = (ASI)pkt->req->getAsi();
 862     uint64_t temp;
 863
 864     DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n",
 865          (uint32_t)pkt->req->getAsi(), pkt->getAddr());
 866
 867     switch (asi) {
 868       case ASI_LSU_CONTROL_REG:
 869         assert(va == 0);
 870         pkt->set(tc->readMiscReg(MISCREG_MMU_LSU_CTRL));
 871         break;
 872       case ASI_MMU:
 873         switch (va) {
 874           case 0x8:
 875             pkt->set(tc->readMiscReg(MISCREG_MMU_P_CONTEXT));
 876             break;
 877           case 0x10:
 878             pkt->set(tc->readMiscReg(MISCREG_MMU_S_CONTEXT));
 879             break;
 880           default:
 881             goto doMmuReadError;
 882         }
 883         break;
 884       case ASI_QUEUE:
 885         pkt->set(tc->readMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD +
 886                     (va >> 4) - 0x3c));
 887         break;
 888       case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0:
 889         assert(va == 0);
 890         pkt->set(tc->readMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS0));
 891         break;
 892       case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1:
 893         assert(va == 0);
 894         pkt->set(tc->readMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS1));
 895         break;
 896       case ASI_DMMU_CTXT_ZERO_CONFIG:
 897         assert(va == 0);
 898         pkt->set(tc->readMiscReg(MISCREG_MMU_DTLB_C0_CONFIG));
 899         break;
 900       case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0:
 901         assert(va == 0);
 902         pkt->set(tc->readMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS0));
 903         break;
 904       case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1:
 905         assert(va == 0);
 906         pkt->set(tc->readMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS1));
 907         break;
 908       case ASI_IMMU_CTXT_ZERO_CONFIG:
 909         assert(va == 0);
 910         pkt->set(tc->readMiscReg(MISCREG_MMU_ITLB_C0_CONFIG));
 911         break;
 912       case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0:
 913         assert(va == 0);
 914         pkt->set(tc->readMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS0));
 915         break;
 916       case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1:
 917         assert(va == 0);
 918         pkt->set(tc->readMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS1));
 919         break;
 920       case ASI_DMMU_CTXT_NONZERO_CONFIG:
 921         assert(va == 0);
 922         pkt->set(tc->readMiscReg(MISCREG_MMU_DTLB_CX_CONFIG));
 923         break;
 924       case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0:
 925         assert(va == 0);
 926         pkt->set(tc->readMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS0));
 927         break;
 928       case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1:
 929         assert(va == 0);
 930         pkt->set(tc->readMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS1));
 931         break;
 932       case ASI_IMMU_CTXT_NONZERO_CONFIG:
 933         assert(va == 0);
 934         pkt->set(tc->readMiscReg(MISCREG_MMU_ITLB_CX_CONFIG));
 935         break;
 936       case ASI_SPARC_ERROR_STATUS_REG:
 937         pkt->set((uint64_t)0);
 938         break;
 939       case ASI_HYP_SCRATCHPAD:
 940       case ASI_SCRATCHPAD:
 941         pkt->set(tc->readMiscReg(MISCREG_SCRATCHPAD_R0 + (va >> 3)));
 942         break;
 943       case ASI_IMMU:
 944         switch (va) {
 945           case 0x0:
 946             temp = tc->readMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS);
 947             pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48);
 948             break;
 949           case 0x18:
 950             pkt->set(tc->readMiscReg(MISCREG_MMU_ITLB_SFSR));
 951             break;
 952           case 0x30:
 953             pkt->set(tc->readMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS));
 954             break;
 955           default:
 956             goto doMmuReadError;
 957         }
 958         break;
 959       case ASI_DMMU:
 960         switch (va) {
 961           case 0x0:
 962             temp = tc->readMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS);
 963             pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48);
 964             break;
 965           case 0x18:
 966             pkt->set(tc->readMiscReg(MISCREG_MMU_DTLB_SFSR));
 967             break;
 968           case 0x20:
 969             pkt->set(tc->readMiscReg(MISCREG_MMU_DTLB_SFAR));
 970             break;
 971           case 0x30:
 972             pkt->set(tc->readMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS));
 973             break;
 974           case 0x80:
 975             pkt->set(tc->readMiscReg(MISCREG_MMU_PART_ID));
 976             break;
 977           default:
 978                 goto doMmuReadError;
 979         }
 980         break;
 981       case ASI_DMMU_TSB_PS0_PTR_REG:
 982         pkt->set(MakeTsbPtr(Ps0,
 983             tc->readMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS),
 984             tc->readMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS0),
 985             tc->readMiscReg(MISCREG_MMU_DTLB_C0_CONFIG),
 986             tc->readMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS0),
 987             tc->readMiscReg(MISCREG_MMU_DTLB_CX_CONFIG)));
 988         break;
 989       case ASI_DMMU_TSB_PS1_PTR_REG:
 990         pkt->set(MakeTsbPtr(Ps1,
 991                 tc->readMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS),
 992                 tc->readMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS1),
 993                 tc->readMiscReg(MISCREG_MMU_DTLB_C0_CONFIG),
 994                 tc->readMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS1),
 995                 tc->readMiscReg(MISCREG_MMU_DTLB_CX_CONFIG)));
 996         break;
 997       case ASI_IMMU_TSB_PS0_PTR_REG:
 998           pkt->set(MakeTsbPtr(Ps0,
 999                 tc->readMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS),
1000                 tc->readMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS0),
1001                 tc->readMiscReg(MISCREG_MMU_ITLB_C0_CONFIG),
1002                 tc->readMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS0),
1003                 tc->readMiscReg(MISCREG_MMU_ITLB_CX_CONFIG)));
1004         break;
1005       case ASI_IMMU_TSB_PS1_PTR_REG:
1006           pkt->set(MakeTsbPtr(Ps1,
1007                 tc->readMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS),
1008                 tc->readMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS1),
1009                 tc->readMiscReg(MISCREG_MMU_ITLB_C0_CONFIG),
1010                 tc->readMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS1),
1011                 tc->readMiscReg(MISCREG_MMU_ITLB_CX_CONFIG)));
1012         break;
1013       case ASI_SWVR_INTR_RECEIVE:
1014         pkt->set(tc->getCpuPtr()->get_interrupts(IT_INT_VEC));
1015         break;
1016       case ASI_SWVR_UDB_INTR_R:
1017         temp = findMsbSet(tc->getCpuPtr()->get_interrupts(IT_INT_VEC));
1018         tc->getCpuPtr()->clear_interrupt(IT_INT_VEC, temp);
1019         pkt->set(temp);
1020         break;
1021       default:
1022 doMmuReadError:
1023         panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n",
1024             (uint32_t)asi, va);
1025     }
1026     pkt->makeAtomicResponse();
1027     return tc->getCpuPtr()->cycles(1);
1028 }
1029
1030 Tick
1031 DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
1032 {
1033     uint64_t data = gtoh(pkt->get<uint64_t>());
1034     Addr va = pkt->getAddr();
1035     ASI asi = (ASI)pkt->req->getAsi();
1036
1037     Addr ta_insert;
1038     Addr va_insert;
1039     Addr ct_insert;
1040     int part_insert;
1041     int entry_insert = -1;
1042     bool real_insert;
1043     bool ignore;
1044     int part_id;
1045     int ctx_id;
1046     PageTableEntry pte;
1047
1048     DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n",
1049          (uint32_t)asi, va, data);
1050
1051     switch (asi) {
1052       case ASI_LSU_CONTROL_REG:
1053         assert(va == 0);
1054         tc->setMiscReg(MISCREG_MMU_LSU_CTRL, data);
1055         break;
1056       case ASI_MMU:
1057         switch (va) {
1058           case 0x8:
1059             tc->setMiscReg(MISCREG_MMU_P_CONTEXT, data);
1060             break;
1061           case 0x10:
1062             tc->setMiscReg(MISCREG_MMU_S_CONTEXT, data);
1063             break;
1064           default:
1065             goto doMmuWriteError;
1066         }
1067         break;
1068       case ASI_QUEUE:
1069         assert(mbits(data,13,6) == data);
1070         tc->setMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD +
1071                     (va >> 4) - 0x3c, data);
1072         break;
1073       case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0:
1074         assert(va == 0);
1075         tc->setMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS0, data);
1076         break;
1077       case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1:
1078         assert(va == 0);
1079         tc->setMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS1, data);
1080         break;
1081       case ASI_DMMU_CTXT_ZERO_CONFIG:
1082         assert(va == 0);
1083         tc->setMiscReg(MISCREG_MMU_DTLB_C0_CONFIG, data);
1084         break;
1085       case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0:
1086         assert(va == 0);
1087         tc->setMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS0, data);
1088         break;
1089       case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1:
1090         assert(va == 0);
1091         tc->setMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS1, data);
1092         break;
1093       case ASI_IMMU_CTXT_ZERO_CONFIG:
1094         assert(va == 0);
1095         tc->setMiscReg(MISCREG_MMU_ITLB_C0_CONFIG, data);
1096         break;
1097       case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0:
1098         assert(va == 0);
1099         tc->setMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS0, data);
1100         break;
1101       case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1:
1102         assert(va == 0);
1103         tc->setMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS1, data);
1104         break;
1105       case ASI_DMMU_CTXT_NONZERO_CONFIG:
1106         assert(va == 0);
1107         tc->setMiscReg(MISCREG_MMU_DTLB_CX_CONFIG, data);
1108         break;
1109       case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0:
1110         assert(va == 0);
1111         tc->setMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS0, data);
1112         break;
1113       case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1:
1114         assert(va == 0);
1115         tc->setMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS1, data);
1116         break;
1117       case ASI_IMMU_CTXT_NONZERO_CONFIG:
1118         assert(va == 0);
1119         tc->setMiscReg(MISCREG_MMU_ITLB_CX_CONFIG, data);
1120         break;
1121       case ASI_SPARC_ERROR_EN_REG:
1122       case ASI_SPARC_ERROR_STATUS_REG:
1123         warn("Ignoring write to SPARC ERROR regsiter\n");
1124         break;
1125       case ASI_HYP_SCRATCHPAD:
1126       case ASI_SCRATCHPAD:
1127         tc->setMiscReg(MISCREG_SCRATCHPAD_R0 + (va >> 3), data);
1128         break;
1129       case ASI_IMMU:
1130         switch (va) {
1131           case 0x18:
1132             tc->setMiscReg(MISCREG_MMU_ITLB_SFSR, data);
1133             break;
1134           case 0x30:
1135             sext<59>(bits(data, 59,0));
1136             tc->setMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS, data);
1137             break;
1138           default:
1139             goto doMmuWriteError;
1140         }
1141         break;
1142       case ASI_ITLB_DATA_ACCESS_REG:
1143         entry_insert = bits(va, 8,3);
1144       case ASI_ITLB_DATA_IN_REG:
1145         assert(entry_insert != -1 || mbits(va,10,9) == va);
1146         ta_insert = tc->readMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS);
1147         va_insert = mbits(ta_insert, 63,13);
1148         ct_insert = mbits(ta_insert, 12,0);
1149         part_insert = tc->readMiscReg(MISCREG_MMU_PART_ID);
1150         real_insert = bits(va, 9,9);
1151         pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v :
1152                 PageTableEntry::sun4u);
1153         tc->getITBPtr()->insert(va_insert, part_insert, ct_insert, real_insert,
1154                 pte, entry_insert);
1155         break;
1156       case ASI_DTLB_DATA_ACCESS_REG:
1157         entry_insert = bits(va, 8,3);
1158       case ASI_DTLB_DATA_IN_REG:
1159         assert(entry_insert != -1 || mbits(va,10,9) == va);
1160         ta_insert = tc->readMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS);
1161         va_insert = mbits(ta_insert, 63,13);
1162         ct_insert = mbits(ta_insert, 12,0);
1163         part_insert = tc->readMiscReg(MISCREG_MMU_PART_ID);
1164         real_insert = bits(va, 9,9);
1165         pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v :
1166                 PageTableEntry::sun4u);
1167         insert(va_insert, part_insert, ct_insert, real_insert, pte, entry_insert);
1168         break;
1169       case ASI_IMMU_DEMAP:
1170         ignore = false;
1171         ctx_id = -1;
1172         part_id =  tc->readMiscReg(MISCREG_MMU_PART_ID);
1173         switch (bits(va,5,4)) {
1174           case 0:
1175             ctx_id = tc->readMiscReg(MISCREG_MMU_P_CONTEXT);
1176             break;
1177           case 1:
1178             ignore = true;
1179             break;
1180           case 3:
1181             ctx_id = 0;
1182             break;
1183           default:
1184             ignore = true;
1185         }
1186
1187         switch(bits(va,7,6)) {
1188           case 0: // demap page
1189             if (!ignore)
1190                 tc->getITBPtr()->demapPage(mbits(va,63,13), part_id,
1191                         bits(va,9,9), ctx_id);
1192             break;
1193           case 1: //demap context
1194             if (!ignore)
1195                 tc->getITBPtr()->demapContext(part_id, ctx_id);
1196             break;
1197           case 2:
1198             tc->getITBPtr()->demapAll(part_id);
1199             break;
1200           default:
1201             panic("Invalid type for IMMU demap\n");
1202         }
1203         break;
1204       case ASI_DMMU:
1205         switch (va) {
1206           case 0x18:
1207             tc->setMiscReg(MISCREG_MMU_DTLB_SFSR, data);
1208             break;
1209           case 0x30:
1210             sext<59>(bits(data, 59,0));
1211             tc->setMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS, data);
1212             break;
1213           case 0x80:
1214             tc->setMiscReg(MISCREG_MMU_PART_ID, data);
1215             break;
1216           default:
1217             goto doMmuWriteError;
1218         }
1219         break;
1220       case ASI_DMMU_DEMAP:
1221         ignore = false;
1222         ctx_id = -1;
1223         part_id =  tc->readMiscReg(MISCREG_MMU_PART_ID);
1224         switch (bits(va,5,4)) {
1225           case 0:
1226             ctx_id = tc->readMiscReg(MISCREG_MMU_P_CONTEXT);
1227             break;
1228           case 1:
1229             ctx_id = tc->readMiscReg(MISCREG_MMU_S_CONTEXT);
1230             break;
1231           case 3:
1232             ctx_id = 0;
1233             break;
1234           default:
1235             ignore = true;
1236         }
1237
1238         switch(bits(va,7,6)) {
1239           case 0: // demap page
1240             if (!ignore)
1241                 demapPage(mbits(va,63,13), part_id, bits(va,9,9), ctx_id);
1242             break;
1243           case 1: //demap context
1244             if (!ignore)
1245                 demapContext(part_id, ctx_id);
1246             break;
1247           case 2:
1248             demapAll(part_id);
1249             break;
1250           default:
1251             panic("Invalid type for IMMU demap\n");
1252         }
1253         break;
1254        case ASI_SWVR_INTR_RECEIVE:
1255         int msb;
1256         // clear all the interrupts that aren't set in the write
1257         while(tc->getCpuPtr()->get_interrupts(IT_INT_VEC) & data) {
1258             msb = findMsbSet(tc->getCpuPtr()->get_interrupts(IT_INT_VEC) & data);
1259             tc->getCpuPtr()->clear_interrupt(IT_INT_VEC, msb);
1260         }
1261         break;
1262       case ASI_SWVR_UDB_INTR_W:
1263             tc->getSystemPtr()->threadContexts[bits(data,12,8)]->getCpuPtr()->
1264             post_interrupt(bits(data,5,0),0);
1265         break;
1266  default:
1267 doMmuWriteError:
1268         panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n",
1269             (uint32_t)pkt->req->getAsi(), pkt->getAddr(), data);
1270     }
1271     pkt->makeAtomicResponse();
1272     return tc->getCpuPtr()->cycles(1);
1273 }
1274
1275 void
1276 DTB::GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs)
1277 {
1278     uint64_t tag_access = mbits(addr,63,13) | mbits(ctx,12,0);
1279     ptrs[0] = MakeTsbPtr(Ps0, tag_access,
1280                 tc->readMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS0),
1281                 tc->readMiscReg(MISCREG_MMU_DTLB_C0_CONFIG),
1282                 tc->readMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS0),
1283                 tc->readMiscReg(MISCREG_MMU_DTLB_CX_CONFIG));
1284     ptrs[1] = MakeTsbPtr(Ps1, tag_access,
1285                 tc->readMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS1),
1286                 tc->readMiscReg(MISCREG_MMU_DTLB_C0_CONFIG),
1287                 tc->readMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS1),
1288                 tc->readMiscReg(MISCREG_MMU_DTLB_CX_CONFIG));
1289     ptrs[2] = MakeTsbPtr(Ps0, tag_access,
1290                 tc->readMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS0),
1291                 tc->readMiscReg(MISCREG_MMU_ITLB_C0_CONFIG),
1292                 tc->readMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS0),
1293                 tc->readMiscReg(MISCREG_MMU_ITLB_CX_CONFIG));
1294     ptrs[3] = MakeTsbPtr(Ps1, tag_access,
1295                 tc->readMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS1),
1296                 tc->readMiscReg(MISCREG_MMU_ITLB_C0_CONFIG),
1297                 tc->readMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS1),
1298                 tc->readMiscReg(MISCREG_MMU_ITLB_CX_CONFIG));
1299 }
1300
1301
1302
1303
1304
1305 uint64_t
1306 DTB::MakeTsbPtr(TsbPageSize ps, uint64_t tag_access, uint64_t c0_tsb,
1307         uint64_t c0_config, uint64_t cX_tsb, uint64_t cX_config)
1308 {
1309     uint64_t tsb;
1310     uint64_t config;
1311
1312     if (bits(tag_access, 12,0) == 0) {
1313         tsb = c0_tsb;
1314         config = c0_config;
1315     } else {
1316         tsb = cX_tsb;
1317         config = cX_config;
1318     }
1319
1320     uint64_t ptr = mbits(tsb,63,13);
1321     bool split = bits(tsb,12,12);
1322     int tsb_size = bits(tsb,3,0);
1323     int page_size = (ps == Ps0) ? bits(config, 2,0) : bits(config,10,8);
1324
1325     if (ps == Ps1  && split)
1326         ptr |= ULL(1) << (13 + tsb_size);
1327     ptr |= (tag_access >> (9 + page_size * 3)) & mask(12+tsb_size, 4);
1328
1329     return ptr;
1330 }
1331
1332
1333 void
1334 TLB::serialize(std::ostream &os)
1335 {
1336     SERIALIZE_SCALAR(size);
1337     SERIALIZE_SCALAR(usedEntries);
1338     SERIALIZE_SCALAR(lastReplaced);
1339
1340     // convert the pointer based free list into an index based one
1341     int *free_list = (int*)malloc(sizeof(int) * size);
1342     int cntr = 0;
1343     std::list<TlbEntry*>::iterator i;
1344     i = freeList.begin();
1345     while (i != freeList.end()) {
1346         free_list[cntr++] = ((size_t)*i - (size_t)tlb)/ sizeof(TlbEntry);
1347         i++;
1348     }
1349     SERIALIZE_SCALAR(cntr);
1350     SERIALIZE_ARRAY(free_list,  cntr);
1351
1352     for (int x = 0; x < size; x++) {
1353         nameOut(os, csprintf("%s.PTE%d", name(), x));
1354         tlb[x].serialize(os);
1355     }
1356 }
1357
1358 void
1359 TLB::unserialize(Checkpoint *cp, const std::string &section)
1360 {
1361     int oldSize;
1362
1363     paramIn(cp, section, "size", oldSize);
1364     if (oldSize != size)
1365         panic("Don't support unserializing different sized TLBs\n");
1366     UNSERIALIZE_SCALAR(usedEntries);
1367     UNSERIALIZE_SCALAR(lastReplaced);
1368
1369     int cntr;
1370     UNSERIALIZE_SCALAR(cntr);
1371
1372     int *free_list = (int*)malloc(sizeof(int) * cntr);
1373     freeList.clear();
1374     UNSERIALIZE_ARRAY(free_list,  cntr);
1375     for (int x = 0; x < cntr; x++)
1376         freeList.push_back(&tlb[free_list[x]]);
1377
1378     lookupTable.clear();
1379     for (int x = 0; x < size; x++) {
1380         tlb[x].unserialize(cp, csprintf("%s.PTE%d", section, x));
1381         if (tlb[x].valid)
1382             lookupTable.insert(tlb[x].range, &tlb[x]);
1383
1384     }
1385 }
1386
1387 /* end namespace SparcISA */ }
1388
1389 using namespace SparcISA;
1390
1391 DEFINE_SIM_OBJECT_CLASS_NAME("SparcTLB", TLB)
1392
1393 BEGIN_DECLARE_SIM_OBJECT_PARAMS(ITB)
1394
1395     Param<int> size;
1396
1397 END_DECLARE_SIM_OBJECT_PARAMS(ITB)
1398
1399 BEGIN_INIT_SIM_OBJECT_PARAMS(ITB)
1400
1401     INIT_PARAM_DFLT(size, "TLB size", 48)
1402
1403 END_INIT_SIM_OBJECT_PARAMS(ITB)
1404
1405
1406 CREATE_SIM_OBJECT(ITB)
1407 {
1408     return new ITB(getInstanceName(), size);
1409 }
1410
1411 REGISTER_SIM_OBJECT("SparcITB", ITB)
1412
1413 BEGIN_DECLARE_SIM_OBJECT_PARAMS(DTB)
1414
1415     Param<int> size;
1416
1417 END_DECLARE_SIM_OBJECT_PARAMS(DTB)
1418
1419 BEGIN_INIT_SIM_OBJECT_PARAMS(DTB)
1420
1421     INIT_PARAM_DFLT(size, "TLB size", 64)
1422
1423 END_INIT_SIM_OBJECT_PARAMS(DTB)
1424
1425
1426 CREATE_SIM_OBJECT(DTB)
1427 {
1428     return new DTB(getInstanceName(), size);
1429 }
1430
1431 REGISTER_SIM_OBJECT("SparcDTB", DTB)