src/arch/sparc/tlb.cc

   1 /*
   2  * Copyright (c) 2001-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Ali Saidi
  29  */
  30
  31 #include <cstring>
  32
  33 #include "arch/sparc/asi.hh"
  34 #include "arch/sparc/miscregfile.hh"
  35 #include "arch/sparc/tlb.hh"
  36 #include "base/bitfield.hh"
  37 #include "base/trace.hh"
  38 #include "cpu/thread_context.hh"
  39 #include "cpu/base.hh"
  40 #include "mem/packet_access.hh"
  41 #include "mem/request.hh"
  42 #include "sim/builder.hh"
  43
  44 /* @todo remove some of the magic constants.  -- ali
  45  * */
  46 namespace SparcISA
  47 {
  48
  49 TLB::TLB(const std::string &name, int s)
  50     : SimObject(name), size(s), usedEntries(0), lastReplaced(0),
  51       cacheValid(false)
  52 {
  53     // To make this work you'll have to change the hypervisor and OS
  54     if (size > 64)
  55         fatal("SPARC T1 TLB registers don't support more than 64 TLB entries.");
  56
  57     tlb = new TlbEntry[size];
  58     std::memset(tlb, 0, sizeof(TlbEntry) * size);
  59
  60     for (int x = 0; x < size; x++)
  61         freeList.push_back(&tlb[x]);
  62 }
  63
  64 void
  65 TLB::clearUsedBits()
  66 {
  67     MapIter i;
  68     for (i = lookupTable.begin(); i != lookupTable.end(); i++) {
  69         TlbEntry *t = i->second;
  70         if (!t->pte.locked()) {
  71             t->used = false;
  72             usedEntries--;
  73         }
  74     }
  75 }
  76
  77
  78 void
  79 TLB::insert(Addr va, int partition_id, int context_id, bool real,
  80         const PageTableEntry& PTE, int entry)
  81 {
  82
  83
  84     MapIter i;
  85     TlbEntry *new_entry = NULL;
  86 //    TlbRange tr;
  87     int x;
  88
  89     cacheValid = false;
  90     va &= ~(PTE.size()-1);
  91  /*   tr.va = va;
  92     tr.size = PTE.size() - 1;
  93     tr.contextId = context_id;
  94     tr.partitionId = partition_id;
  95     tr.real = real;
  96 */
  97
  98     DPRINTF(TLB, "TLB: Inserting TLB Entry; va=%#x pa=%#x pid=%d cid=%d r=%d entryid=%d\n",
  99             va, PTE.paddr(), partition_id, context_id, (int)real, entry);
 100
 101     // Demap any entry that conflicts
 102     for (x = 0; x < size; x++) {
 103         if (tlb[x].range.real == real &&
 104             tlb[x].range.partitionId == partition_id &&
 105             tlb[x].range.va < va + PTE.size() - 1 &&
 106             tlb[x].range.va + tlb[x].range.size >= va &&
 107             (real || tlb[x].range.contextId == context_id ))
 108         {
 109             if (tlb[x].valid) {
 110                 freeList.push_front(&tlb[x]);
 111                 DPRINTF(TLB, "TLB: Conflicting entry %#X , deleting it\n", x);
 112
 113                 tlb[x].valid = false;
 114                 if (tlb[x].used) {
 115                     tlb[x].used = false;
 116                     usedEntries--;
 117                 }
 118                 lookupTable.erase(tlb[x].range);
 119             }
 120         }
 121     }
 122
 123
 124 /*
 125     i = lookupTable.find(tr);
 126     if (i != lookupTable.end()) {
 127         i->second->valid = false;
 128         if (i->second->used) {
 129             i->second->used = false;
 130             usedEntries--;
 131         }
 132         freeList.push_front(i->second);
 133         DPRINTF(TLB, "TLB: Found conflicting entry %#X , deleting it\n",
 134                 i->second);
 135         lookupTable.erase(i);
 136     }
 137 */
 138
 139     if (entry != -1) {
 140         assert(entry < size && entry >= 0);
 141         new_entry = &tlb[entry];
 142     } else {
 143         if (!freeList.empty()) {
 144             new_entry = freeList.front();
 145         } else {
 146             x = lastReplaced;
 147             do {
 148                 ++x;
 149                 if (x == size)
 150                     x = 0;
 151                 if (x == lastReplaced)
 152                     goto insertAllLocked;
 153             } while (tlb[x].pte.locked());
 154             lastReplaced = x;
 155             new_entry = &tlb[x];
 156         }
 157         /*
 158         for (x = 0; x < size; x++) {
 159             if (!tlb[x].valid || !tlb[x].used)  {
 160                 new_entry = &tlb[x];
 161                 break;
 162             }
 163         }*/
 164     }
 165
 166 insertAllLocked:
 167     // Update the last ently if their all locked
 168     if (!new_entry) {
 169         new_entry = &tlb[size-1];
 170     }
 171
 172     freeList.remove(new_entry);
 173     if (new_entry->valid && new_entry->used)
 174         usedEntries--;
 175     if (new_entry->valid)
 176         lookupTable.erase(new_entry->range);
 177
 178
 179     DPRINTF(TLB, "Using entry: %#X\n", new_entry);
 180
 181     assert(PTE.valid());
 182     new_entry->range.va = va;
 183     new_entry->range.size = PTE.size() - 1;
 184     new_entry->range.partitionId = partition_id;
 185     new_entry->range.contextId = context_id;
 186     new_entry->range.real = real;
 187     new_entry->pte = PTE;
 188     new_entry->used = true;;
 189     new_entry->valid = true;
 190     usedEntries++;
 191
 192
 193
 194     i = lookupTable.insert(new_entry->range, new_entry);
 195     assert(i != lookupTable.end());
 196
 197     // If all entries have there used bit set, clear it on them all, but the
 198     // one we just inserted
 199     if (usedEntries == size) {
 200         clearUsedBits();
 201         new_entry->used = true;
 202         usedEntries++;
 203     }
 204
 205 }
 206
 207
 208 TlbEntry*
 209 TLB::lookup(Addr va, int partition_id, bool real, int context_id)
 210 {
 211     MapIter i;
 212     TlbRange tr;
 213     TlbEntry *t;
 214
 215     DPRINTF(TLB, "TLB: Looking up entry va=%#x pid=%d cid=%d r=%d\n",
 216             va, partition_id, context_id, real);
 217     // Assemble full address structure
 218     tr.va = va;
 219     tr.size = MachineBytes;
 220     tr.contextId = context_id;
 221     tr.partitionId = partition_id;
 222     tr.real = real;
 223
 224     // Try to find the entry
 225     i = lookupTable.find(tr);
 226     if (i == lookupTable.end()) {
 227         DPRINTF(TLB, "TLB: No valid entry found\n");
 228         return NULL;
 229     }
 230
 231     // Mark the entries used bit and clear other used bits in needed
 232     t = i->second;
 233     DPRINTF(TLB, "TLB: Valid entry found pa: %#x size: %#x\n", t->pte.paddr(),
 234             t->pte.size());
 235     if (!t->used) {
 236         t->used = true;
 237         usedEntries++;
 238         if (usedEntries == size) {
 239             clearUsedBits();
 240             t->used = true;
 241             usedEntries++;
 242         }
 243     }
 244
 245     return t;
 246 }
 247
 248 void
 249 TLB::dumpAll()
 250 {
 251     MapIter i;
 252     for (int x = 0; x < size; x++) {
 253         if (tlb[x].valid) {
 254            DPRINTFN("%4d:  %#2x:%#2x %c %#4x %#8x %#8x %#16x\n",
 255                    x, tlb[x].range.partitionId, tlb[x].range.contextId,
 256                    tlb[x].range.real ? 'R' : ' ', tlb[x].range.size,
 257                    tlb[x].range.va, tlb[x].pte.paddr(), tlb[x].pte());
 258         }
 259     }
 260 }
 261
 262 void
 263 TLB::demapPage(Addr va, int partition_id, bool real, int context_id)
 264 {
 265     TlbRange tr;
 266     MapIter i;
 267
 268     DPRINTF(IPR, "TLB: Demapping Page va=%#x pid=%#d cid=%d r=%d\n",
 269             va, partition_id, context_id, real);
 270
 271     cacheValid = false;
 272
 273     // Assemble full address structure
 274     tr.va = va;
 275     tr.size = MachineBytes;
 276     tr.contextId = context_id;
 277     tr.partitionId = partition_id;
 278     tr.real = real;
 279
 280     // Demap any entry that conflicts
 281     i = lookupTable.find(tr);
 282     if (i != lookupTable.end()) {
 283         DPRINTF(IPR, "TLB: Demapped page\n");
 284         i->second->valid = false;
 285         if (i->second->used) {
 286             i->second->used = false;
 287             usedEntries--;
 288         }
 289         freeList.push_front(i->second);
 290         DPRINTF(TLB, "Freeing TLB entry : %#X\n", i->second);
 291         lookupTable.erase(i);
 292     }
 293 }
 294
 295 void
 296 TLB::demapContext(int partition_id, int context_id)
 297 {
 298     int x;
 299     DPRINTF(IPR, "TLB: Demapping Context pid=%#d cid=%d\n",
 300             partition_id, context_id);
 301     cacheValid = false;
 302     for (x = 0; x < size; x++) {
 303         if (tlb[x].range.contextId == context_id &&
 304             tlb[x].range.partitionId == partition_id) {
 305             if (tlb[x].valid == true) {
 306                 freeList.push_front(&tlb[x]);
 307                 DPRINTF(TLB, "Freeing TLB entry : %#X\n", &tlb[x]);
 308             }
 309             tlb[x].valid = false;
 310             if (tlb[x].used) {
 311                 tlb[x].used = false;
 312                 usedEntries--;
 313             }
 314             lookupTable.erase(tlb[x].range);
 315         }
 316     }
 317 }
 318
 319 void
 320 TLB::demapAll(int partition_id)
 321 {
 322     int x;
 323     DPRINTF(TLB, "TLB: Demapping All pid=%#d\n", partition_id);
 324     cacheValid = false;
 325     for (x = 0; x < size; x++) {
 326         if (!tlb[x].pte.locked() && tlb[x].range.partitionId == partition_id) {
 327             if (tlb[x].valid == true){
 328                 freeList.push_front(&tlb[x]);
 329                 DPRINTF(TLB, "Freeing TLB entry : %#X\n", &tlb[x]);
 330             }
 331             tlb[x].valid = false;
 332             if (tlb[x].used) {
 333                 tlb[x].used = false;
 334                 usedEntries--;
 335             }
 336             lookupTable.erase(tlb[x].range);
 337         }
 338     }
 339 }
 340
 341 void
 342 TLB::invalidateAll()
 343 {
 344     int x;
 345     cacheValid = false;
 346
 347     freeList.clear();
 348     lookupTable.clear();
 349     for (x = 0; x < size; x++) {
 350         if (tlb[x].valid == true)
 351             freeList.push_back(&tlb[x]);
 352         tlb[x].valid = false;
 353         tlb[x].used = false;
 354     }
 355     usedEntries = 0;
 356 }
 357
 358 uint64_t
 359 TLB::TteRead(int entry) {
 360     if (entry >= size)
 361         panic("entry: %d\n", entry);
 362
 363     assert(entry < size);
 364     if (tlb[entry].valid)
 365         return tlb[entry].pte();
 366     else
 367         return (uint64_t)-1ll;
 368 }
 369
 370 uint64_t
 371 TLB::TagRead(int entry) {
 372     assert(entry < size);
 373     uint64_t tag;
 374     if (!tlb[entry].valid)
 375         return (uint64_t)-1ll;
 376
 377     tag = tlb[entry].range.contextId;
 378     tag |= tlb[entry].range.va;
 379     tag |= (uint64_t)tlb[entry].range.partitionId << 61;
 380     tag |= tlb[entry].range.real ? ULL(1) << 60 : 0;
 381     tag |= (uint64_t)~tlb[entry].pte._size() << 56;
 382     return tag;
 383 }
 384
 385 bool
 386 TLB::validVirtualAddress(Addr va, bool am)
 387 {
 388     if (am)
 389         return true;
 390     if (va >= StartVAddrHole && va <= EndVAddrHole)
 391         return false;
 392     return true;
 393 }
 394
 395 void
 396 TLB::writeSfsr(ThreadContext *tc, int reg,  bool write, ContextType ct,
 397         bool se, FaultTypes ft, int asi)
 398 {
 399     uint64_t sfsr;
 400     sfsr = tc->readMiscReg(reg);
 401
 402     if (sfsr & 0x1)
 403         sfsr = 0x3;
 404     else
 405         sfsr = 1;
 406
 407     if (write)
 408         sfsr |= 1 << 2;
 409     sfsr |= ct << 4;
 410     if (se)
 411         sfsr |= 1 << 6;
 412     sfsr |= ft << 7;
 413     sfsr |= asi << 16;
 414     tc->setMiscRegWithEffect(reg, sfsr);
 415 }
 416
 417 void
 418 TLB::writeTagAccess(ThreadContext *tc, int reg, Addr va, int context)
 419 {
 420     DPRINTF(TLB, "TLB: Writing Tag Access: va: %#X ctx: %#X value: %#X\n",
 421             va, context, mbits(va, 63,13) | mbits(context,12,0));
 422
 423     tc->setMiscRegWithEffect(reg, mbits(va, 63,13) | mbits(context,12,0));
 424 }
 425
 426 void
 427 ITB::writeSfsr(ThreadContext *tc, bool write, ContextType ct,
 428         bool se, FaultTypes ft, int asi)
 429 {
 430     DPRINTF(TLB, "TLB: ITB Fault:  w=%d ct=%d ft=%d asi=%d\n",
 431              (int)write, ct, ft, asi);
 432     TLB::writeSfsr(tc, MISCREG_MMU_ITLB_SFSR, write, ct, se, ft, asi);
 433 }
 434
 435 void
 436 ITB::writeTagAccess(ThreadContext *tc, Addr va, int context)
 437 {
 438     TLB::writeTagAccess(tc, MISCREG_MMU_ITLB_TAG_ACCESS, va, context);
 439 }
 440
 441 void
 442 DTB::writeSfr(ThreadContext *tc, Addr a, bool write, ContextType ct,
 443         bool se, FaultTypes ft, int asi)
 444 {
 445     DPRINTF(TLB, "TLB: DTB Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n",
 446             a, (int)write, ct, ft, asi);
 447     TLB::writeSfsr(tc, MISCREG_MMU_DTLB_SFSR, write, ct, se, ft, asi);
 448     tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_SFAR, a);
 449 }
 450
 451 void
 452 DTB::writeTagAccess(ThreadContext *tc, Addr va, int context)
 453 {
 454     TLB::writeTagAccess(tc, MISCREG_MMU_DTLB_TAG_ACCESS, va, context);
 455 }
 456
 457
 458
 459 Fault
 460 ITB::translate(RequestPtr &req, ThreadContext *tc)
 461 {
 462     uint64_t tlbdata = tc->readMiscReg(MISCREG_TLB_DATA);
 463
 464     Addr vaddr = req->getVaddr();
 465     TlbEntry *e;
 466
 467     assert(req->getAsi() == ASI_IMPLICIT);
 468
 469     DPRINTF(TLB, "TLB: ITB Request to translate va=%#x size=%d\n",
 470             vaddr, req->getSize());
 471
 472     // Be fast if we can!
 473     if (cacheValid && cacheState == tlbdata) {
 474         if (cacheEntry) {
 475             if (cacheEntry->range.va < vaddr + sizeof(MachInst) &&
 476                 cacheEntry->range.va + cacheEntry->range.size >= vaddr) {
 477                     req->setPaddr(cacheEntry->pte.paddr() & ~(cacheEntry->pte.size()-1) |
 478                                   vaddr & cacheEntry->pte.size()-1 );
 479                     return NoFault;
 480             }
 481         } else {
 482             req->setPaddr(vaddr & PAddrImplMask);
 483             return NoFault;
 484         }
 485     }
 486
 487     bool hpriv = bits(tlbdata,0,0);
 488     bool red = bits(tlbdata,1,1);
 489     bool priv = bits(tlbdata,2,2);
 490     bool addr_mask = bits(tlbdata,3,3);
 491     bool lsu_im = bits(tlbdata,4,4);
 492
 493     int part_id = bits(tlbdata,15,8);
 494     int tl = bits(tlbdata,18,16);
 495     int pri_context = bits(tlbdata,47,32);
 496     int context;
 497     ContextType ct;
 498     int asi;
 499     bool real = false;
 500
 501     DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsuim:%d part_id: %#X\n",
 502            priv, hpriv, red, lsu_im, part_id);
 503
 504     if (tl > 0) {
 505         asi = ASI_N;
 506         ct = Nucleus;
 507         context = 0;
 508     } else {
 509         asi = ASI_P;
 510         ct = Primary;
 511         context = pri_context;
 512     }
 513
 514     if ( hpriv || red ) {
 515         cacheValid = true;
 516         cacheState = tlbdata;
 517         cacheEntry = NULL;
 518         req->setPaddr(vaddr & PAddrImplMask);
 519         return NoFault;
 520     }
 521
 522     // If the access is unaligned trap
 523     if (vaddr & 0x3) {
 524         writeSfsr(tc, false, ct, false, OtherFault, asi);
 525         return new MemAddressNotAligned;
 526     }
 527
 528     if (addr_mask)
 529         vaddr = vaddr & VAddrAMask;
 530
 531     if (!validVirtualAddress(vaddr, addr_mask)) {
 532         writeSfsr(tc, false, ct, false, VaOutOfRange, asi);
 533         return new InstructionAccessException;
 534     }
 535
 536     if (!lsu_im) {
 537         e = lookup(vaddr, part_id, true);
 538         real = true;
 539         context = 0;
 540     } else {
 541         e = lookup(vaddr, part_id, false, context);
 542     }
 543
 544     if (e == NULL || !e->valid) {
 545         writeTagAccess(tc, vaddr, context);
 546         if (real)
 547             return new InstructionRealTranslationMiss;
 548         else
 549             return new FastInstructionAccessMMUMiss;
 550     }
 551
 552     // were not priviledged accesing priv page
 553     if (!priv && e->pte.priv()) {
 554         writeTagAccess(tc, vaddr, context);
 555         writeSfsr(tc, false, ct, false, PrivViolation, asi);
 556         return new InstructionAccessException;
 557     }
 558
 559     // cache translation date for next translation
 560     cacheValid = true;
 561     cacheState = tlbdata;
 562     cacheEntry = e;
 563
 564     req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) |
 565                   vaddr & e->pte.size()-1 );
 566     DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
 567     return NoFault;
 568 }
 569
 570
 571
 572 Fault
 573 DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
 574 {
 575     /* @todo this could really use some profiling and fixing to make it faster! */
 576     uint64_t tlbdata = tc->readMiscReg(MISCREG_TLB_DATA);
 577     Addr vaddr = req->getVaddr();
 578     Addr size = req->getSize();
 579     ASI asi;
 580     asi = (ASI)req->getAsi();
 581     bool implicit = false;
 582     bool hpriv = bits(tlbdata,0,0);
 583
 584     DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n",
 585             vaddr, size, asi);
 586
 587     if (lookupTable.size() != 64 - freeList.size())
 588        panic("Lookup table size: %d tlb size: %d\n", lookupTable.size(),
 589                freeList.size());
 590     if (asi == ASI_IMPLICIT)
 591         implicit = true;
 592
 593     if (hpriv && implicit) {
 594         req->setPaddr(vaddr & PAddrImplMask);
 595         return NoFault;
 596     }
 597
 598     // Be fast if we can!
 599     if (cacheValid &&  cacheState == tlbdata) {
 600         if (cacheEntry[0] && cacheAsi[0] == asi && cacheEntry[0]->range.va < vaddr + size &&
 601             cacheEntry[0]->range.va + cacheEntry[0]->range.size > vaddr &&
 602             (!write || cacheEntry[0]->pte.writable())) {
 603                 req->setPaddr(cacheEntry[0]->pte.paddr() & ~(cacheEntry[0]->pte.size()-1) |
 604                               vaddr & cacheEntry[0]->pte.size()-1 );
 605                 return NoFault;
 606         }
 607         if (cacheEntry[1] && cacheAsi[1] == asi && cacheEntry[1]->range.va < vaddr + size &&
 608             cacheEntry[1]->range.va + cacheEntry[1]->range.size > vaddr &&
 609             (!write || cacheEntry[1]->pte.writable())) {
 610                 req->setPaddr(cacheEntry[1]->pte.paddr() & ~(cacheEntry[1]->pte.size()-1) |
 611                               vaddr & cacheEntry[1]->pte.size()-1 );
 612                 return NoFault;
 613         }
 614     }
 615
 616     bool red = bits(tlbdata,1,1);
 617     bool priv = bits(tlbdata,2,2);
 618     bool addr_mask = bits(tlbdata,3,3);
 619     bool lsu_dm = bits(tlbdata,5,5);
 620
 621     int part_id = bits(tlbdata,15,8);
 622     int tl = bits(tlbdata,18,16);
 623     int pri_context = bits(tlbdata,47,32);
 624     int sec_context = bits(tlbdata,63,48);
 625
 626     bool real = false;
 627     ContextType ct = Primary;
 628     int context = 0;
 629
 630     TlbEntry *e;
 631
 632     DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsudm:%d part_id: %#X\n",
 633            priv, hpriv, red, lsu_dm, part_id);
 634
 635     if (implicit) {
 636         if (tl > 0) {
 637             asi = ASI_N;
 638             ct = Nucleus;
 639             context = 0;
 640         } else {
 641             asi = ASI_P;
 642             ct = Primary;
 643             context = pri_context;
 644         }
 645     } else {
 646         // We need to check for priv level/asi priv
 647         if (!priv && !hpriv && !AsiIsUnPriv(asi)) {
 648             // It appears that context should be Nucleus in these cases?
 649             writeSfr(tc, vaddr, write, Nucleus, false, IllegalAsi, asi);
 650             return new PrivilegedAction;
 651         }
 652
 653         if (!hpriv && AsiIsHPriv(asi)) {
 654             writeSfr(tc, vaddr, write, Nucleus, false, IllegalAsi, asi);
 655             return new DataAccessException;
 656         }
 657
 658         if (AsiIsPrimary(asi)) {
 659             context = pri_context;
 660             ct = Primary;
 661         } else if (AsiIsSecondary(asi)) {
 662             context = sec_context;
 663             ct = Secondary;
 664         } else if (AsiIsNucleus(asi)) {
 665             ct = Nucleus;
 666             context = 0;
 667         } else {  // ????
 668             ct = Primary;
 669             context = pri_context;
 670         }
 671     }
 672
 673     if (!implicit && asi != ASI_P && asi != ASI_S) {
 674         if (AsiIsLittle(asi))
 675             panic("Little Endian ASIs not supported\n");
 676         if (AsiIsBlock(asi))
 677             panic("Block ASIs not supported\n");
 678         if (AsiIsNoFault(asi))
 679             panic("No Fault ASIs not supported\n");
 680
 681         if (AsiIsPartialStore(asi))
 682             panic("Partial Store ASIs not supported\n");
 683         if (AsiIsInterrupt(asi))
 684             panic("Interrupt ASIs not supported\n");
 685
 686         if (AsiIsMmu(asi))
 687             goto handleMmuRegAccess;
 688         if (AsiIsScratchPad(asi))
 689             goto handleScratchRegAccess;
 690         if (AsiIsQueue(asi))
 691             goto handleQueueRegAccess;
 692         if (AsiIsSparcError(asi))
 693             goto handleSparcErrorRegAccess;
 694
 695         if (!AsiIsReal(asi) && !AsiIsNucleus(asi) && !AsiIsAsIfUser(asi) &&
 696                 !AsiIsTwin(asi))
 697             panic("Accessing ASI %#X. Should we?\n", asi);
 698     }
 699
 700     // If the asi is unaligned trap
 701     if (vaddr & size-1) {
 702         writeSfr(tc, vaddr, false, ct, false, OtherFault, asi);
 703         return new MemAddressNotAligned;
 704     }
 705
 706     if (addr_mask)
 707         vaddr = vaddr & VAddrAMask;
 708
 709     if (!validVirtualAddress(vaddr, addr_mask)) {
 710         writeSfr(tc, vaddr, false, ct, true, VaOutOfRange, asi);
 711         return new DataAccessException;
 712     }
 713
 714
 715     if ((!lsu_dm && !hpriv && !red) || AsiIsReal(asi)) {
 716         real = true;
 717         context = 0;
 718     };
 719
 720     if (hpriv && (implicit || (!AsiIsAsIfUser(asi) && !AsiIsReal(asi)))) {
 721         req->setPaddr(vaddr & PAddrImplMask);
 722         return NoFault;
 723     }
 724
 725     e = lookup(vaddr, part_id, real, context);
 726
 727     if (e == NULL || !e->valid) {
 728         writeTagAccess(tc, vaddr, context);
 729         DPRINTF(TLB, "TLB: DTB Failed to find matching TLB entry\n");
 730         if (real)
 731             return new DataRealTranslationMiss;
 732         else
 733             return new FastDataAccessMMUMiss;
 734
 735     }
 736
 737     if (!priv && e->pte.priv()) {
 738         writeTagAccess(tc, vaddr, context);
 739         writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), PrivViolation, asi);
 740         return new DataAccessException;
 741     }
 742
 743     if (write && !e->pte.writable()) {
 744         writeTagAccess(tc, vaddr, context);
 745         writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), OtherFault, asi);
 746         return new FastDataAccessProtection;
 747     }
 748
 749     if (e->pte.nofault() && !AsiIsNoFault(asi)) {
 750         writeTagAccess(tc, vaddr, context);
 751         writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), LoadFromNfo, asi);
 752         return new DataAccessException;
 753     }
 754
 755     if (e->pte.sideffect() && AsiIsNoFault(asi)) {
 756         writeTagAccess(tc, vaddr, context);
 757         writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), SideEffect, asi);
 758         return new DataAccessException;
 759     }
 760
 761
 762     if (e->pte.sideffect())
 763         req->setFlags(req->getFlags() | UNCACHEABLE);
 764
 765     // cache translation date for next translation
 766     cacheState = tlbdata;
 767     if (!cacheValid) {
 768         cacheEntry[1] = NULL;
 769         cacheEntry[0] = NULL;
 770     }
 771
 772     if (cacheEntry[0] != e && cacheEntry[1] != e) {
 773         cacheEntry[1] = cacheEntry[0];
 774         cacheEntry[0] = e;
 775         cacheAsi[1] = cacheAsi[0];
 776         cacheAsi[0] = asi;
 777         if (implicit)
 778             cacheAsi[0] = (ASI)0;
 779     }
 780     cacheValid = true;
 781     req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) |
 782                   vaddr & e->pte.size()-1);
 783     DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
 784     return NoFault;
 785     /** Normal flow ends here. */
 786
 787 handleScratchRegAccess:
 788     if (vaddr > 0x38 || (vaddr >= 0x20 && vaddr < 0x30 && !hpriv)) {
 789         writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
 790         return new DataAccessException;
 791     }
 792     goto regAccessOk;
 793
 794 handleQueueRegAccess:
 795     if (!priv  && !hpriv) {
 796         writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
 797         return new PrivilegedAction;
 798     }
 799     if (!hpriv && vaddr & 0xF || vaddr > 0x3f8 || vaddr < 0x3c0) {
 800         writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
 801         return new DataAccessException;
 802     }
 803     goto regAccessOk;
 804
 805 handleSparcErrorRegAccess:
 806     if (!hpriv) {
 807         if (priv) {
 808             writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
 809             return new DataAccessException;
 810         } else {
 811             writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
 812             return new PrivilegedAction;
 813         }
 814     }
 815     goto regAccessOk;
 816
 817
 818 regAccessOk:
 819 handleMmuRegAccess:
 820     DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n");
 821     req->setMmapedIpr(true);
 822     req->setPaddr(req->getVaddr());
 823     return NoFault;
 824 };
 825
 826 Tick
 827 DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
 828 {
 829     Addr va = pkt->getAddr();
 830     ASI asi = (ASI)pkt->req->getAsi();
 831     uint64_t temp, data;
 832     uint64_t tsbtemp, cnftemp;
 833
 834     DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n",
 835          (uint32_t)pkt->req->getAsi(), pkt->getAddr());
 836
 837     switch (asi) {
 838       case ASI_LSU_CONTROL_REG:
 839         assert(va == 0);
 840         pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_LSU_CTRL));
 841         break;
 842       case ASI_MMU:
 843         switch (va) {
 844           case 0x8:
 845             pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT));
 846             break;
 847           case 0x10:
 848             pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_S_CONTEXT));
 849             break;
 850           default:
 851             goto doMmuReadError;
 852         }
 853         break;
 854       case ASI_QUEUE:
 855         pkt->set(tc->readMiscRegWithEffect(MISCREG_QUEUE_CPU_MONDO_HEAD +
 856                     (va >> 4) - 0x3c));
 857         break;
 858       case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0:
 859         assert(va == 0);
 860         pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0));
 861         break;
 862       case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1:
 863         assert(va == 0);
 864         pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1));
 865         break;
 866       case ASI_DMMU_CTXT_ZERO_CONFIG:
 867         assert(va == 0);
 868         pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG));
 869         break;
 870       case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0:
 871         assert(va == 0);
 872         pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0));
 873         break;
 874       case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1:
 875         assert(va == 0);
 876         pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1));
 877         break;
 878       case ASI_IMMU_CTXT_ZERO_CONFIG:
 879         assert(va == 0);
 880         pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG));
 881         break;
 882       case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0:
 883         assert(va == 0);
 884         pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0));
 885         break;
 886       case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1:
 887         assert(va == 0);
 888         pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1));
 889         break;
 890       case ASI_DMMU_CTXT_NONZERO_CONFIG:
 891         assert(va == 0);
 892         pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG));
 893         break;
 894       case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0:
 895         assert(va == 0);
 896         pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0));
 897         break;
 898       case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1:
 899         assert(va == 0);
 900         pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1));
 901         break;
 902       case ASI_IMMU_CTXT_NONZERO_CONFIG:
 903         assert(va == 0);
 904         pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG));
 905         break;
 906       case ASI_SPARC_ERROR_STATUS_REG:
 907         warn("returning 0 for  SPARC ERROR regsiter read\n");
 908         pkt->set((uint64_t)0);
 909         break;
 910       case ASI_HYP_SCRATCHPAD:
 911       case ASI_SCRATCHPAD:
 912         pkt->set(tc->readMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3)));
 913         break;
 914       case ASI_IMMU:
 915         switch (va) {
 916           case 0x0:
 917             temp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS);
 918             pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48);
 919             break;
 920           case 0x18:
 921             pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_SFSR));
 922             break;
 923           case 0x30:
 924             pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS));
 925             break;
 926           default:
 927             goto doMmuReadError;
 928         }
 929         break;
 930       case ASI_DMMU:
 931         switch (va) {
 932           case 0x0:
 933             temp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS);
 934             pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48);
 935             break;
 936           case 0x18:
 937             pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_SFSR));
 938             break;
 939           case 0x20:
 940             pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_SFAR));
 941             break;
 942           case 0x30:
 943             pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS));
 944             break;
 945           case 0x80:
 946             pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID));
 947             break;
 948           default:
 949                 goto doMmuReadError;
 950         }
 951         break;
 952       case ASI_DMMU_TSB_PS0_PTR_REG:
 953         temp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS);
 954         if (bits(temp,12,0) == 0) {
 955             tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0);
 956             cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG);
 957         } else {
 958             tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0);
 959             cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG);
 960         }
 961         data = mbits(tsbtemp,63,13);
 962         data |= temp >> (9 + bits(cnftemp,2,0) * 3) &
 963             mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4);
 964         pkt->set(data);
 965         break;
 966       case ASI_DMMU_TSB_PS1_PTR_REG:
 967         temp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS);
 968         if (bits(temp,12,0) == 0) {
 969             tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1);
 970             cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG);
 971         } else {
 972             tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1);
 973             cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG);
 974         }
 975         data = mbits(tsbtemp,63,13);
 976         if (bits(tsbtemp,12,12))
 977             data |= ULL(1) << (13+bits(tsbtemp,3,0));
 978         data |= temp >> (9 + bits(cnftemp,10,8) * 3) &
 979             mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4);
 980         pkt->set(data);
 981         break;
 982       case ASI_IMMU_TSB_PS0_PTR_REG:
 983         temp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS);
 984         if (bits(temp,12,0) == 0) {
 985             tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0);
 986             cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG);
 987         } else {
 988             tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0);
 989             cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG);
 990         }
 991         data = mbits(tsbtemp,63,13);
 992         data |= temp >> (9 + bits(cnftemp,2,0) * 3) &
 993             mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4);
 994         pkt->set(data);
 995         break;
 996       case ASI_IMMU_TSB_PS1_PTR_REG:
 997         temp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS);
 998         if (bits(temp,12,0) == 0) {
 999             tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1);
1000             cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG);
1001         } else {
1002             tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1);
1003             cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG);
1004         }
1005         data = mbits(tsbtemp,63,13);
1006         if (bits(tsbtemp,12,12))
1007             data |= ULL(1) << (13+bits(tsbtemp,3,0));
1008         data |= temp >> (9 + bits(cnftemp,10,8) * 3) &
1009             mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4);
1010         pkt->set(data);
1011         break;
1012
1013       default:
1014 doMmuReadError:
1015         panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n",
1016             (uint32_t)asi, va);
1017     }
1018     pkt->result = Packet::Success;
1019     return tc->getCpuPtr()->cycles(1);
1020 }
1021
1022 Tick
1023 DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
1024 {
1025     uint64_t data = gtoh(pkt->get<uint64_t>());
1026     Addr va = pkt->getAddr();
1027     ASI asi = (ASI)pkt->req->getAsi();
1028
1029     Addr ta_insert;
1030     Addr va_insert;
1031     Addr ct_insert;
1032     int part_insert;
1033     int entry_insert = -1;
1034     bool real_insert;
1035     bool ignore;
1036     int part_id;
1037     int ctx_id;
1038     PageTableEntry pte;
1039
1040     DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n",
1041          (uint32_t)asi, va, data);
1042
1043     switch (asi) {
1044       case ASI_LSU_CONTROL_REG:
1045         assert(va == 0);
1046         tc->setMiscRegWithEffect(MISCREG_MMU_LSU_CTRL, data);
1047         break;
1048       case ASI_MMU:
1049         switch (va) {
1050           case 0x8:
1051             tc->setMiscRegWithEffect(MISCREG_MMU_P_CONTEXT, data);
1052             break;
1053           case 0x10:
1054             tc->setMiscRegWithEffect(MISCREG_MMU_S_CONTEXT, data);
1055             break;
1056           default:
1057             goto doMmuWriteError;
1058         }
1059         break;
1060       case ASI_QUEUE:
1061         assert(mbits(data,13,6) == data);
1062         tc->setMiscRegWithEffect(MISCREG_QUEUE_CPU_MONDO_HEAD +
1063                     (va >> 4) - 0x3c, data);
1064         break;
1065       case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0:
1066         assert(va == 0);
1067         tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0, data);
1068         break;
1069       case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1:
1070         assert(va == 0);
1071         tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1, data);
1072         break;
1073       case ASI_DMMU_CTXT_ZERO_CONFIG:
1074         assert(va == 0);
1075         tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG, data);
1076         break;
1077       case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0:
1078         assert(va == 0);
1079         tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0, data);
1080         break;
1081       case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1:
1082         assert(va == 0);
1083         tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1, data);
1084         break;
1085       case ASI_IMMU_CTXT_ZERO_CONFIG:
1086         assert(va == 0);
1087         tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG, data);
1088         break;
1089       case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0:
1090         assert(va == 0);
1091         tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0, data);
1092         break;
1093       case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1:
1094         assert(va == 0);
1095         tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1, data);
1096         break;
1097       case ASI_DMMU_CTXT_NONZERO_CONFIG:
1098         assert(va == 0);
1099         tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG, data);
1100         break;
1101       case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0:
1102         assert(va == 0);
1103         tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0, data);
1104         break;
1105       case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1:
1106         assert(va == 0);
1107         tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1, data);
1108         break;
1109       case ASI_IMMU_CTXT_NONZERO_CONFIG:
1110         assert(va == 0);
1111         tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG, data);
1112         break;
1113       case ASI_SPARC_ERROR_EN_REG:
1114       case ASI_SPARC_ERROR_STATUS_REG:
1115         warn("Ignoring write to SPARC ERROR regsiter\n");
1116         break;
1117       case ASI_HYP_SCRATCHPAD:
1118       case ASI_SCRATCHPAD:
1119         tc->setMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3), data);
1120         break;
1121       case ASI_IMMU:
1122         switch (va) {
1123           case 0x18:
1124             tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_SFSR, data);
1125             break;
1126           case 0x30:
1127             sext<59>(bits(data, 59,0));
1128             tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS, data);
1129             break;
1130           default:
1131             goto doMmuWriteError;
1132         }
1133         break;
1134       case ASI_ITLB_DATA_ACCESS_REG:
1135         entry_insert = bits(va, 8,3);
1136       case ASI_ITLB_DATA_IN_REG:
1137         assert(entry_insert != -1 || mbits(va,10,9) == va);
1138         ta_insert = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS);
1139         va_insert = mbits(ta_insert, 63,13);
1140         ct_insert = mbits(ta_insert, 12,0);
1141         part_insert = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID);
1142         real_insert = bits(va, 9,9);
1143         pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v :
1144                 PageTableEntry::sun4u);
1145         tc->getITBPtr()->insert(va_insert, part_insert, ct_insert, real_insert,
1146                 pte, entry_insert);
1147         break;
1148       case ASI_DTLB_DATA_ACCESS_REG:
1149         entry_insert = bits(va, 8,3);
1150       case ASI_DTLB_DATA_IN_REG:
1151         assert(entry_insert != -1 || mbits(va,10,9) == va);
1152         ta_insert = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS);
1153         va_insert = mbits(ta_insert, 63,13);
1154         ct_insert = mbits(ta_insert, 12,0);
1155         part_insert = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID);
1156         real_insert = bits(va, 9,9);
1157         pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v :
1158                 PageTableEntry::sun4u);
1159         insert(va_insert, part_insert, ct_insert, real_insert, pte, entry_insert);
1160         break;
1161       case ASI_IMMU_DEMAP:
1162         ignore = false;
1163         ctx_id = -1;
1164         part_id =  tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID);
1165         switch (bits(va,5,4)) {
1166           case 0:
1167             ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT);
1168             break;
1169           case 1:
1170             ignore = true;
1171             break;
1172           case 3:
1173             ctx_id = 0;
1174             break;
1175           default:
1176             ignore = true;
1177         }
1178
1179         switch(bits(va,7,6)) {
1180           case 0: // demap page
1181             if (!ignore)
1182                 tc->getITBPtr()->demapPage(mbits(va,63,13), part_id,
1183                         bits(va,9,9), ctx_id);
1184             break;
1185           case 1: //demap context
1186             if (!ignore)
1187                 tc->getITBPtr()->demapContext(part_id, ctx_id);
1188             break;
1189           case 2:
1190             tc->getITBPtr()->demapAll(part_id);
1191             break;
1192           default:
1193             panic("Invalid type for IMMU demap\n");
1194         }
1195         break;
1196       case ASI_DMMU:
1197         switch (va) {
1198           case 0x18:
1199             tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_SFSR, data);
1200             break;
1201           case 0x30:
1202             sext<59>(bits(data, 59,0));
1203             tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS, data);
1204             break;
1205           case 0x80:
1206             tc->setMiscRegWithEffect(MISCREG_MMU_PART_ID, data);
1207             break;
1208           default:
1209             goto doMmuWriteError;
1210         }
1211         break;
1212       case ASI_DMMU_DEMAP:
1213         ignore = false;
1214         ctx_id = -1;
1215         part_id =  tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID);
1216         switch (bits(va,5,4)) {
1217           case 0:
1218             ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT);
1219             break;
1220           case 1:
1221             ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_S_CONTEXT);
1222             break;
1223           case 3:
1224             ctx_id = 0;
1225             break;
1226           default:
1227             ignore = true;
1228         }
1229
1230         switch(bits(va,7,6)) {
1231           case 0: // demap page
1232             if (!ignore)
1233                 demapPage(mbits(va,63,13), part_id, bits(va,9,9), ctx_id);
1234             break;
1235           case 1: //demap context
1236             if (!ignore)
1237                 demapContext(part_id, ctx_id);
1238             break;
1239           case 2:
1240             demapAll(part_id);
1241             break;
1242           default:
1243             panic("Invalid type for IMMU demap\n");
1244         }
1245         break;
1246       default:
1247 doMmuWriteError:
1248         panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n",
1249             (uint32_t)pkt->req->getAsi(), pkt->getAddr(), data);
1250     }
1251     pkt->result = Packet::Success;
1252     return tc->getCpuPtr()->cycles(1);
1253 }
1254
1255 void
1256 TLB::serialize(std::ostream &os)
1257 {
1258     panic("Need to implement serialize tlb for SPARC\n");
1259 }
1260
1261 void
1262 TLB::unserialize(Checkpoint *cp, const std::string &section)
1263 {
1264     panic("Need to implement unserialize tlb for SPARC\n");
1265 }
1266
1267
1268 DEFINE_SIM_OBJECT_CLASS_NAME("SparcTLB", TLB)
1269
1270 BEGIN_DECLARE_SIM_OBJECT_PARAMS(ITB)
1271
1272     Param<int> size;
1273
1274 END_DECLARE_SIM_OBJECT_PARAMS(ITB)
1275
1276 BEGIN_INIT_SIM_OBJECT_PARAMS(ITB)
1277
1278     INIT_PARAM_DFLT(size, "TLB size", 48)
1279
1280 END_INIT_SIM_OBJECT_PARAMS(ITB)
1281
1282
1283 CREATE_SIM_OBJECT(ITB)
1284 {
1285     return new ITB(getInstanceName(), size);
1286 }
1287
1288 REGISTER_SIM_OBJECT("SparcITB", ITB)
1289
1290 BEGIN_DECLARE_SIM_OBJECT_PARAMS(DTB)
1291
1292     Param<int> size;
1293
1294 END_DECLARE_SIM_OBJECT_PARAMS(DTB)
1295
1296 BEGIN_INIT_SIM_OBJECT_PARAMS(DTB)
1297
1298     INIT_PARAM_DFLT(size, "TLB size", 64)
1299
1300 END_INIT_SIM_OBJECT_PARAMS(DTB)
1301
1302
1303 CREATE_SIM_OBJECT(DTB)
1304 {
1305     return new DTB(getInstanceName(), size);
1306 }
1307
1308 REGISTER_SIM_OBJECT("SparcDTB", DTB)
1309 }