src/arch/sparc/tlb.hh

   1 /*
   2  * Copyright (c) 2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Ali Saidi
  29  */
  30
  31 #ifndef __ARCH_SPARC_TLB_HH__
  32 #define __ARCH_SPARC_TLB_HH__
  33
  34 #include "arch/sparc/asi.hh"
  35 #include "arch/sparc/tlb_map.hh"
  36 #include "base/misc.hh"
  37 #include "mem/request.hh"
  38 #include "params/SparcTLB.hh"
  39 #include "sim/fault_fwd.hh"
  40 #include "sim/tlb.hh"
  41
  42 class ThreadContext;
  43 class Packet;
  44
  45 namespace SparcISA
  46 {
  47
  48 class TLB : public BaseTLB
  49 {
  50     // These faults need to be able to populate the tlb in SE mode.
  51     friend class FastInstructionAccessMMUMiss;
  52     friend class FastDataAccessMMUMiss;
  53
  54     // TLB state
  55   protected:
  56     // Only used when this is the data TLB.
  57     uint64_t sfar;
  58     uint64_t c0_tsb_ps0;
  59     uint64_t c0_tsb_ps1;
  60     uint64_t c0_config;
  61     uint64_t cx_tsb_ps0;
  62     uint64_t cx_tsb_ps1;
  63     uint64_t cx_config;
  64     uint64_t sfsr;
  65     uint64_t tag_access;
  66
  67   protected:
  68     TlbMap lookupTable;;
  69     typedef TlbMap::iterator MapIter;
  70
  71     TlbEntry *tlb;
  72
  73     int size;
  74     int usedEntries;
  75     int lastReplaced;
  76
  77     uint64_t cacheState;
  78     bool cacheValid;
  79
  80     std::list<TlbEntry*> freeList;
  81
  82     enum FaultTypes {
  83         OtherFault = 0,
  84         PrivViolation = 0x1,
  85         SideEffect = 0x2,
  86         AtomicToIo = 0x4,
  87         IllegalAsi = 0x8,
  88         LoadFromNfo = 0x10,
  89         VaOutOfRange = 0x20,
  90         VaOutOfRangeJmp = 0x40
  91     };
  92
  93     enum ContextType {
  94         Primary = 0,
  95         Secondary = 1,
  96         Nucleus = 2
  97     };
  98
  99     enum TsbPageSize {
 100         Ps0,
 101         Ps1
 102     };
 103   public:
 104     /** lookup an entry in the TLB based on the partition id, and real bit if
 105      * real is true or the partition id, and context id if real is false.
 106      * @param va the virtual address not shifted (e.g. bottom 13 bits are 0)
 107      * @param paritition_id partition this entry is for
 108      * @param real is this a real->phys or virt->phys translation
 109      * @param context_id if this is virt->phys what context
 110      * @param update_used should ew update the used bits in the
 111      * entries on not useful if we are trying to do a va->pa without
 112      * mucking with any state for a debug read for example.
 113      * @return A pointer to a tlb entry
 114      */
 115     TlbEntry *lookup(Addr va, int partition_id, bool real, int context_id = 0,
 116             bool update_used = true);
 117
 118     /** Remove all entries from the TLB */
 119     void flushAll();
 120
 121   protected:
 122     /** Insert a PTE into the TLB. */
 123     void insert(Addr vpn, int partition_id, int context_id, bool real,
 124             const PageTableEntry& PTE, int entry = -1);
 125
 126     /** Given an entry id, read that tlb entries' tag. */
 127     uint64_t TagRead(int entry);
 128
 129     /** Remove all non-locked entries from the tlb that match partition id. */
 130     void demapAll(int partition_id);
 131
 132     /** Remove all entries that match a given context/partition id. */
 133     void demapContext(int partition_id, int context_id);
 134
 135     /** Remve all entries that match a certain partition id, (contextid), and
 136      * va). */
 137     void demapPage(Addr va, int partition_id, bool real, int context_id);
 138
 139     /** Checks if the virtual address provided is a valid one. */
 140     bool validVirtualAddress(Addr va, bool am);
 141
 142     void writeSfsr(bool write, ContextType ct,
 143             bool se, FaultTypes ft, int asi);
 144
 145     void clearUsedBits();
 146
 147
 148     void writeTagAccess(Addr va, int context);
 149
 150     Fault translateInst(RequestPtr req, ThreadContext *tc);
 151     Fault translateData(RequestPtr req, ThreadContext *tc, bool write);
 152
 153   public:
 154     typedef SparcTLBParams Params;
 155     TLB(const Params *p);
 156
 157     void
 158     demapPage(Addr vaddr, uint64_t asn)
 159     {
 160         panic("demapPage(Addr) is not implemented.\n");
 161     }
 162
 163     void dumpAll();
 164
 165     Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
 166     void translateTiming(RequestPtr req, ThreadContext *tc,
 167             Translation *translation, Mode mode);
 168     /** Stub function for compilation support with CheckerCPU. SPARC ISA
 169      *  does not support the Checker model at the moment
 170      */
 171     Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode);
 172     Cycles doMmuRegRead(ThreadContext *tc, Packet *pkt);
 173     Cycles doMmuRegWrite(ThreadContext *tc, Packet *pkt);
 174     void GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs);
 175
 176     // Checkpointing
 177     virtual void serialize(std::ostream &os);
 178     virtual void unserialize(Checkpoint *cp, const std::string &section);
 179
 180     /** Give an entry id, read that tlb entries' tte */
 181     uint64_t TteRead(int entry);
 182
 183   private:
 184     void writeSfsr(Addr a, bool write, ContextType ct,
 185             bool se, FaultTypes ft, int asi);
 186
 187     uint64_t MakeTsbPtr(TsbPageSize ps, uint64_t tag_access, uint64_t c0_tsb,
 188         uint64_t c0_config, uint64_t cX_tsb, uint64_t cX_config);
 189
 190
 191     TlbEntry *cacheEntry[2];
 192     ASI cacheAsi[2];
 193 };
 194
 195 }
 196
 197 #endif // __ARCH_SPARC_TLB_HH__