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31 #ifndef __ARCH_SPARC_TLB_HH__
32 #define __ARCH_SPARC_TLB_HH__
34 #include "arch/sparc/asi.hh"
35 #include "arch/sparc/tlb_map.hh"
36 #include "base/misc.hh"
37 #include "mem/request.hh"
38 #include "params/SparcTLB.hh"
39 #include "sim/fault_fwd.hh"
48 class TLB : public BaseTLB
50 // These faults need to be able to populate the tlb in SE mode.
51 friend class FastInstructionAccessMMUMiss;
52 friend class FastDataAccessMMUMiss;
56 // Only used when this is the data TLB.
69 typedef TlbMap::iterator MapIter;
80 std::list<TlbEntry*> freeList;
90 VaOutOfRangeJmp = 0x40
104 /** lookup an entry in the TLB based on the partition id, and real bit if
105 * real is true or the partition id, and context id if real is false.
106 * @param va the virtual address not shifted (e.g. bottom 13 bits are 0)
107 * @param paritition_id partition this entry is for
108 * @param real is this a real->phys or virt->phys translation
109 * @param context_id if this is virt->phys what context
110 * @param update_used should ew update the used bits in the
111 * entries on not useful if we are trying to do a va->pa without
112 * mucking with any state for a debug read for example.
113 * @return A pointer to a tlb entry
115 TlbEntry *lookup(Addr va, int partition_id, bool real, int context_id = 0,
116 bool update_used = true);
118 /** Remove all entries from the TLB */
122 /** Insert a PTE into the TLB. */
123 void insert(Addr vpn, int partition_id, int context_id, bool real,
124 const PageTableEntry& PTE, int entry = -1);
126 /** Given an entry id, read that tlb entries' tag. */
127 uint64_t TagRead(int entry);
129 /** Remove all non-locked entries from the tlb that match partition id. */
130 void demapAll(int partition_id);
132 /** Remove all entries that match a given context/partition id. */
133 void demapContext(int partition_id, int context_id);
135 /** Remve all entries that match a certain partition id, (contextid), and
137 void demapPage(Addr va, int partition_id, bool real, int context_id);
139 /** Checks if the virtual address provided is a valid one. */
140 bool validVirtualAddress(Addr va, bool am);
142 void writeSfsr(bool write, ContextType ct,
143 bool se, FaultTypes ft, int asi);
145 void clearUsedBits();
148 void writeTagAccess(Addr va, int context);
150 Fault translateInst(RequestPtr req, ThreadContext *tc);
151 Fault translateData(RequestPtr req, ThreadContext *tc, bool write);
154 typedef SparcTLBParams Params;
155 TLB(const Params *p);
158 demapPage(Addr vaddr, uint64_t asn)
160 panic("demapPage(Addr) is not implemented.\n");
165 Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
166 void translateTiming(RequestPtr req, ThreadContext *tc,
167 Translation *translation, Mode mode);
168 /** Stub function for compilation support with CheckerCPU. SPARC ISA
169 * does not support the Checker model at the moment
171 Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode);
172 Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const;
173 Cycles doMmuRegRead(ThreadContext *tc, Packet *pkt);
174 Cycles doMmuRegWrite(ThreadContext *tc, Packet *pkt);
175 void GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs);
178 virtual void serialize(std::ostream &os);
179 virtual void unserialize(Checkpoint *cp, const std::string §ion);
181 /** Give an entry id, read that tlb entries' tte */
182 uint64_t TteRead(int entry);
185 void writeSfsr(Addr a, bool write, ContextType ct,
186 bool se, FaultTypes ft, int asi);
188 uint64_t MakeTsbPtr(TsbPageSize ps, uint64_t tag_access, uint64_t c0_tsb,
189 uint64_t c0_config, uint64_t cX_tsb, uint64_t cX_config);
192 TlbEntry *cacheEntry[2];
198 #endif // __ARCH_SPARC_TLB_HH__