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31 #ifndef __ARCH_SPARC_TLB_HH__
32 #define __ARCH_SPARC_TLB_HH__
34 #include "arch/sparc/asi.hh"
35 #include "arch/sparc/tlb_map.hh"
36 #include "base/misc.hh"
37 #include "config/full_system.hh"
38 #include "mem/request.hh"
39 #include "params/SparcDTB.hh"
40 #include "params/SparcITB.hh"
41 #include "sim/faults.hh"
50 class TLB : public BaseTLB
53 //These faults need to be able to populate the tlb in SE mode.
54 friend class FastInstructionAccessMMUMiss;
55 friend class FastDataAccessMMUMiss;
71 typedef TlbMap::iterator MapIter;
82 std::list<TlbEntry*> freeList;
92 VaOutOfRangeJmp = 0x40
106 /** lookup an entry in the TLB based on the partition id, and real bit if
107 * real is true or the partition id, and context id if real is false.
108 * @param va the virtual address not shifted (e.g. bottom 13 bits are 0)
109 * @param paritition_id partition this entry is for
110 * @param real is this a real->phys or virt->phys translation
111 * @param context_id if this is virt->phys what context
112 * @param update_used should ew update the used bits in the
113 * entries on not useful if we are trying to do a va->pa without
114 * mucking with any state for a debug read for example.
115 * @return A pointer to a tlb entry
117 TlbEntry *lookup(Addr va, int partition_id, bool real, int context_id = 0,
118 bool update_used = true);
120 /** Insert a PTE into the TLB. */
121 void insert(Addr vpn, int partition_id, int context_id, bool real,
122 const PageTableEntry& PTE, int entry = -1);
124 /** Given an entry id, read that tlb entries' tag. */
125 uint64_t TagRead(int entry);
127 /** Remove all entries from the TLB */
128 void invalidateAll();
130 /** Remove all non-locked entries from the tlb that match partition id. */
131 void demapAll(int partition_id);
133 /** Remove all entries that match a given context/partition id. */
134 void demapContext(int partition_id, int context_id);
136 /** Remve all entries that match a certain partition id, (contextid), and
138 void demapPage(Addr va, int partition_id, bool real, int context_id);
140 /** Checks if the virtual address provided is a valid one. */
141 bool validVirtualAddress(Addr va, bool am);
143 void writeSfsr(bool write, ContextType ct,
144 bool se, FaultTypes ft, int asi);
146 void clearUsedBits();
149 void writeTagAccess(Addr va, int context);
152 typedef SparcTLBParams Params;
153 TLB(const Params *p);
155 void demapPage(Addr vaddr, uint64_t asn)
157 panic("demapPage(Addr) is not implemented.\n");
163 virtual void serialize(std::ostream &os);
164 virtual void unserialize(Checkpoint *cp, const std::string §ion);
166 /** Give an entry id, read that tlb entries' tte */
167 uint64_t TteRead(int entry);
171 class ITB : public TLB
174 typedef SparcITBParams Params;
175 ITB(const Params *p) : TLB(p)
180 Fault translateAtomic(RequestPtr req, ThreadContext *tc);
181 void translateTiming(RequestPtr req, ThreadContext *tc,
182 Translation *translation);
184 void writeSfsr(bool write, ContextType ct,
185 bool se, FaultTypes ft, int asi);
186 TlbEntry *cacheEntry;
190 class DTB : public TLB
192 //DTLB specific state
196 typedef SparcDTBParams Params;
197 DTB(const Params *p) : TLB(p)
200 cacheEntry[0] = NULL;
201 cacheEntry[1] = NULL;
204 Fault translateAtomic(RequestPtr req,
205 ThreadContext *tc, bool write=false);
206 void translateTiming(RequestPtr req, ThreadContext *tc,
207 Translation *translation, bool write=false);
209 Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
210 Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);
212 void GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs);
215 virtual void serialize(std::ostream &os);
216 virtual void unserialize(Checkpoint *cp, const std::string §ion);
219 void writeSfsr(Addr a, bool write, ContextType ct,
220 bool se, FaultTypes ft, int asi);
222 uint64_t MakeTsbPtr(TsbPageSize ps, uint64_t tag_access, uint64_t c0_tsb,
223 uint64_t c0_config, uint64_t cX_tsb, uint64_t cX_config);
226 TlbEntry *cacheEntry[2];
232 #endif // __ARCH_SPARC_TLB_HH__