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31 #ifndef __ARCH_SPARC_TLB_HH__
32 #define __ARCH_SPARC_TLB_HH__
34 #include "arch/sparc/asi.hh"
35 #include "arch/sparc/tlb_map.hh"
36 #include "base/misc.hh"
37 #include "mem/request.hh"
38 #include "sim/faults.hh"
39 #include "sim/sim_object.hh"
47 class TLB : public SimObject
51 typedef TlbMap::iterator MapIter;
69 VaOutOfRangeJmp = 0x40
79 /** lookup an entry in the TLB based on the partition id, and real bit if
80 * real is true or the partition id, and context id if real is false.
81 * @param va the virtual address not shifted (e.g. bottom 13 bits are 0)
82 * @param paritition_id partition this entry is for
83 * @param real is this a real->phys or virt->phys translation
84 * @param context_id if this is virt->phys what context
85 * @return A pointer to a tlb entry
87 TlbEntry *lookup(Addr va, int partition_id, bool real, int context_id = 0);
89 /** Insert a PTE into the TLB. */
90 void insert(Addr vpn, int partition_id, int context_id, bool real,
91 const PageTableEntry& PTE, int entry = -1);
93 /** Given an entry id, read that tlb entries' tag. */
94 uint64_t TagRead(int entry);
96 /** Give an entry id, read that tlb entries' tte */
97 uint64_t TteRead(int entry);
99 /** Remove all entries from the TLB */
100 void invalidateAll();
102 /** Remove all non-locked entries from the tlb that match partition id. */
103 void demapAll(int partition_id);
105 /** Remove all entries that match a given context/partition id. */
106 void demapContext(int partition_id, int context_id);
108 /** Remve all entries that match a certain partition id, (contextid), and
110 void demapPage(Addr va, int partition_id, bool real, int context_id);
112 /** Checks if the virtual address provided is a valid one. */
113 bool validVirtualAddress(Addr va, bool am);
115 void writeSfsr(ThreadContext *tc, int reg, bool write, ContextType ct,
116 bool se, FaultTypes ft, int asi);
118 void clearUsedBits();
121 void writeTagAccess(ThreadContext *tc, int reg, Addr va, int context);
124 TLB(const std::string &name, int size);
129 virtual void serialize(std::ostream &os);
130 virtual void unserialize(Checkpoint *cp, const std::string §ion);
133 class ITB : public TLB
136 ITB(const std::string &name, int size) : TLB(name, size)
141 Fault translate(RequestPtr &req, ThreadContext *tc);
143 void writeSfsr(ThreadContext *tc, bool write, ContextType ct,
144 bool se, FaultTypes ft, int asi);
145 void writeTagAccess(ThreadContext *tc, Addr va, int context);
146 TlbEntry *cacheEntry;
150 class DTB : public TLB
153 DTB(const std::string &name, int size) : TLB(name, size)
155 cacheEntry[0] = NULL;
156 cacheEntry[1] = NULL;
159 Fault translate(RequestPtr &req, ThreadContext *tc, bool write);
160 Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
161 Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);
164 void writeSfr(ThreadContext *tc, Addr a, bool write, ContextType ct,
165 bool se, FaultTypes ft, int asi);
166 void writeTagAccess(ThreadContext *tc, Addr va, int context);
168 TlbEntry *cacheEntry[2];
174 #endif // __ARCH_SPARC_TLB_HH__