CPU: Create a microcode ROM object in the CPU which is defined by the ISA.
[gem5.git] / src / arch / sparc / types.hh
1 /*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31 #ifndef __ARCH_SPARC_TYPES_HH__
32 #define __ARCH_SPARC_TYPES_HH__
33
34 #include <inttypes.h>
35 #include "base/bigint.hh"
36
37 namespace SparcISA
38 {
39 typedef uint32_t MachInst;
40 typedef uint64_t ExtMachInst;
41
42 typedef uint64_t IntReg;
43 typedef Twin64_t LargestRead;
44 typedef uint64_t MiscReg;
45 typedef double FloatReg;
46 typedef uint64_t FloatRegBits;
47 typedef union
48 {
49 IntReg intReg;
50 FloatReg fpreg;
51 MiscReg ctrlreg;
52 } AnyReg;
53
54 enum RegContextParam
55 {
56 CONTEXT_CWP,
57 CONTEXT_GLOBALS
58 };
59
60 typedef int RegContextVal;
61
62 typedef uint16_t RegIndex;
63
64 struct CoreSpecific {
65 int core_type;
66 };
67 }
68
69 #endif