2 * Copyright (c) 2006 The Regents of The University of Michigan
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29 #include "arch/sparc/kernel_stats.hh"
30 #include "arch/sparc/miscregfile.hh"
31 #include "base/bitfield.hh"
32 #include "base/trace.hh"
33 #include "cpu/base.hh"
34 #include "cpu/thread_context.hh"
35 #include "sim/system.hh"
37 using namespace SparcISA
;
41 MiscRegFile::checkSoftInt(ThreadContext
*tc
)
43 BaseCPU
*cpu
= tc
->getCpuPtr();
45 // If PIL < 14, copy over the tm and sm bits
46 if (pil
< 14 && softint
& 0x10000)
47 cpu
->postInterrupt(IT_SOFT_INT
, 16);
49 cpu
->clearInterrupt(IT_SOFT_INT
, 16);
50 if (pil
< 14 && softint
& 0x1)
51 cpu
->postInterrupt(IT_SOFT_INT
, 0);
53 cpu
->clearInterrupt(IT_SOFT_INT
, 0);
55 // Copy over any of the other bits that are set
56 for (int bit
= 15; bit
> 0; --bit
) {
57 if (1 << bit
& softint
&& bit
> pil
)
58 cpu
->postInterrupt(IT_SOFT_INT
, bit
);
60 cpu
->clearInterrupt(IT_SOFT_INT
, bit
);
66 MiscRegFile::setFSReg(int miscReg
, const MiscReg
&val
, ThreadContext
*tc
)
68 BaseCPU
*cpu
= tc
->getCpuPtr();
72 /* Full system only ASRs */
74 setRegNoEffect(miscReg
, val
);;
77 case MISCREG_SOFTINT_CLR
:
78 return setReg(MISCREG_SOFTINT
, ~val
& softint
, tc
);
79 case MISCREG_SOFTINT_SET
:
80 return setReg(MISCREG_SOFTINT
, val
| softint
, tc
);
82 case MISCREG_TICK_CMPR
:
83 if (tickCompare
== NULL
)
84 tickCompare
= new TickCompareEvent(this, tc
);
85 setRegNoEffect(miscReg
, val
);
86 if ((tick_cmpr
& ~mask(63)) && tickCompare
->scheduled())
87 cpu
->deschedule(tickCompare
);
88 time
= (tick_cmpr
& mask(63)) - (tick
& mask(63));
89 if (!(tick_cmpr
& ~mask(63)) && time
> 0) {
90 if (tickCompare
->scheduled())
91 cpu
->deschedule(tickCompare
);
92 cpu
->schedule(tickCompare
, curTick
+ time
* cpu
->ticks(1));
94 panic("writing to TICK compare register %#X\n", val
);
97 case MISCREG_STICK_CMPR
:
98 if (sTickCompare
== NULL
)
99 sTickCompare
= new STickCompareEvent(this, tc
);
100 setRegNoEffect(miscReg
, val
);
101 if ((stick_cmpr
& ~mask(63)) && sTickCompare
->scheduled())
102 cpu
->deschedule(sTickCompare
);
103 time
= ((int64_t)(stick_cmpr
& mask(63)) - (int64_t)stick
) -
105 if (!(stick_cmpr
& ~mask(63)) && time
> 0) {
106 if (sTickCompare
->scheduled())
107 cpu
->deschedule(sTickCompare
);
108 cpu
->schedule(sTickCompare
, curTick
+ time
* cpu
->ticks(1));
110 DPRINTF(Timer
, "writing to sTICK compare register value %#X\n", val
);
114 setRegNoEffect(miscReg
, val
);
117 setRegNoEffect(miscReg
, val
);
122 panic("Shouldn't be writing HVER\n");
125 setRegNoEffect(miscReg
, val
);
127 cpu
->postInterrupt(IT_HINTP
, 0);
129 cpu
->clearInterrupt(IT_HINTP
, 0);
133 // clear lower 7 bits on writes.
134 setRegNoEffect(miscReg
, val
& ULL(~0x7FFF));
137 case MISCREG_QUEUE_CPU_MONDO_HEAD
:
138 case MISCREG_QUEUE_CPU_MONDO_TAIL
:
139 setRegNoEffect(miscReg
, val
);
140 if (cpu_mondo_head
!= cpu_mondo_tail
)
141 cpu
->postInterrupt(IT_CPU_MONDO
, 0);
143 cpu
->clearInterrupt(IT_CPU_MONDO
, 0);
145 case MISCREG_QUEUE_DEV_MONDO_HEAD
:
146 case MISCREG_QUEUE_DEV_MONDO_TAIL
:
147 setRegNoEffect(miscReg
, val
);
148 if (dev_mondo_head
!= dev_mondo_tail
)
149 cpu
->postInterrupt(IT_DEV_MONDO
, 0);
151 cpu
->clearInterrupt(IT_DEV_MONDO
, 0);
153 case MISCREG_QUEUE_RES_ERROR_HEAD
:
154 case MISCREG_QUEUE_RES_ERROR_TAIL
:
155 setRegNoEffect(miscReg
, val
);
156 if (res_error_head
!= res_error_tail
)
157 cpu
->postInterrupt(IT_RES_ERROR
, 0);
159 cpu
->clearInterrupt(IT_RES_ERROR
, 0);
161 case MISCREG_QUEUE_NRES_ERROR_HEAD
:
162 case MISCREG_QUEUE_NRES_ERROR_TAIL
:
163 setRegNoEffect(miscReg
, val
);
164 // This one doesn't have an interrupt to report to the guest OS
167 case MISCREG_HSTICK_CMPR
:
168 if (hSTickCompare
== NULL
)
169 hSTickCompare
= new HSTickCompareEvent(this, tc
);
170 setRegNoEffect(miscReg
, val
);
171 if ((hstick_cmpr
& ~mask(63)) && hSTickCompare
->scheduled())
172 cpu
->deschedule(hSTickCompare
);
173 time
= ((int64_t)(hstick_cmpr
& mask(63)) - (int64_t)stick
) -
175 if (!(hstick_cmpr
& ~mask(63)) && time
> 0) {
176 if (hSTickCompare
->scheduled())
177 cpu
->deschedule(hSTickCompare
);
178 cpu
->schedule(hSTickCompare
, curTick
+ time
* cpu
->ticks(1));
180 DPRINTF(Timer
, "writing to hsTICK compare register value %#X\n", val
);
183 case MISCREG_HPSTATE
:
184 // T1000 spec says impl. dependent val must always be 1
185 setRegNoEffect(miscReg
, val
| HPSTATE::id
);
187 if (hpstate
& HPSTATE::tlz
&& tl
== 0 && !(hpstate
& HPSTATE::hpriv
))
188 cpu
->postInterrupt(IT_TRAP_LEVEL_ZERO
, 0);
190 cpu
->clearInterrupt(IT_TRAP_LEVEL_ZERO
, 0);
193 case MISCREG_HTSTATE
:
194 setRegNoEffect(miscReg
, val
);
197 case MISCREG_STRAND_STS_REG
:
199 panic("No support for setting spec_en bit\n");
200 setRegNoEffect(miscReg
, bits(val
,0,0));
201 if (!bits(val
,0,0)) {
202 DPRINTF(Quiesce
, "Cpu executed quiescing instruction\n");
203 // Time to go to sleep
205 if (tc
->getKernelStats())
206 tc
->getKernelStats()->quiesce();
211 panic("Invalid write to FS misc register %s\n",
212 getMiscRegName(miscReg
));
217 MiscRegFile::readFSReg(int miscReg
, ThreadContext
* tc
)
222 /* Privileged registers. */
223 case MISCREG_QUEUE_CPU_MONDO_HEAD
:
224 case MISCREG_QUEUE_CPU_MONDO_TAIL
:
225 case MISCREG_QUEUE_DEV_MONDO_HEAD
:
226 case MISCREG_QUEUE_DEV_MONDO_TAIL
:
227 case MISCREG_QUEUE_RES_ERROR_HEAD
:
228 case MISCREG_QUEUE_RES_ERROR_TAIL
:
229 case MISCREG_QUEUE_NRES_ERROR_HEAD
:
230 case MISCREG_QUEUE_NRES_ERROR_TAIL
:
231 case MISCREG_SOFTINT
:
232 case MISCREG_TICK_CMPR
:
233 case MISCREG_STICK_CMPR
:
235 case MISCREG_HPSTATE
:
237 case MISCREG_HTSTATE
:
238 case MISCREG_HSTICK_CMPR
:
239 return readRegNoEffect(miscReg
) ;
242 return readRegNoEffect(miscReg
) & ULL(~0x7FFF);
244 // XXX set to match Legion
245 return ULL(0x3e) << 48 |
248 //MaxGL << 16 | XXX For some reason legion doesn't set GL
252 case MISCREG_STRAND_STS_REG
:
255 sys
= tc
->getSystemPtr();
257 temp
= readRegNoEffect(miscReg
) & (STS::active
| STS::speculative
);
258 // Check that the CPU array is fully populated
259 // (by calling getNumCPus())
260 assert(sys
->numContexts() > tc
->contextId());
262 temp
|= tc
->contextId() << STS::shft_id
;
264 for (x
= tc
->contextId() & ~3; x
< sys
->threadContexts
.size(); x
++) {
265 switch (sys
->threadContexts
[x
]->status()) {
266 case ThreadContext::Active
:
267 temp
|= STS::st_run
<< (STS::shft_fsm0
-
268 ((x
& 0x3) * (STS::shft_fsm0
-STS::shft_fsm1
)));
270 case ThreadContext::Suspended
:
271 // should this be idle?
272 temp
|= STS::st_idle
<< (STS::shft_fsm0
-
273 ((x
& 0x3) * (STS::shft_fsm0
-STS::shft_fsm1
)));
275 case ThreadContext::Halted
:
276 temp
|= STS::st_halt
<< (STS::shft_fsm0
-
277 ((x
& 0x3) * (STS::shft_fsm0
-STS::shft_fsm1
)));
280 panic("What state are we in?!\n");
286 panic("Invalid read to FS misc register\n");
291 MiscRegFile::processTickCompare(ThreadContext
*tc
)
293 panic("tick compare not implemented\n");
297 MiscRegFile::processSTickCompare(ThreadContext
*tc
)
299 BaseCPU
*cpu
= tc
->getCpuPtr();
301 // since our microcode instructions take two cycles we need to check if
302 // we're actually at the correct cycle or we need to wait a little while
305 ticks
= ((int64_t)(stick_cmpr
& mask(63)) - (int64_t)stick
) -
307 assert(ticks
>= 0 && "stick compare missed interrupt cycle");
309 if (ticks
== 0 || tc
->status() == ThreadContext::Suspended
) {
310 DPRINTF(Timer
, "STick compare cycle reached at %#x\n",
311 (stick_cmpr
& mask(63)));
312 if (!(tc
->readMiscRegNoEffect(MISCREG_STICK_CMPR
) & (ULL(1) << 63))) {
313 setReg(MISCREG_SOFTINT
, softint
| (ULL(1) << 16), tc
);
316 cpu
->schedule(sTickCompare
, curTick
+ ticks
* cpu
->ticks(1));
320 MiscRegFile::processHSTickCompare(ThreadContext
*tc
)
322 BaseCPU
*cpu
= tc
->getCpuPtr();
324 // since our microcode instructions take two cycles we need to check if
325 // we're actually at the correct cycle or we need to wait a little while
328 if ( tc
->status() == ThreadContext::Halted
||
329 tc
->status() == ThreadContext::Unallocated
)
332 ticks
= ((int64_t)(hstick_cmpr
& mask(63)) - (int64_t)stick
) -
334 assert(ticks
>= 0 && "hstick compare missed interrupt cycle");
336 if (ticks
== 0 || tc
->status() == ThreadContext::Suspended
) {
337 DPRINTF(Timer
, "HSTick compare cycle reached at %#x\n",
338 (stick_cmpr
& mask(63)));
339 if (!(tc
->readMiscRegNoEffect(MISCREG_HSTICK_CMPR
) & (ULL(1) << 63))) {
340 setReg(MISCREG_HINTP
, 1, tc
);
342 // Need to do something to cause interrupt to happen here !!! @todo
344 cpu
->schedule(hSTickCompare
, curTick
+ ticks
* cpu
->ticks(1));