2 * Copyright (c) 2006 The Regents of The University of Michigan
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29 #include "arch/sparc/isa.hh"
30 #include "arch/sparc/kernel_stats.hh"
31 #include "arch/sparc/registers.hh"
32 #include "base/bitfield.hh"
33 #include "base/trace.hh"
34 #include "cpu/base.hh"
35 #include "cpu/thread_context.hh"
36 #include "sim/system.hh"
38 using namespace SparcISA
;
43 ISA::checkSoftInt(ThreadContext
*tc
)
45 BaseCPU
*cpu
= tc
->getCpuPtr();
47 // If PIL < 14, copy over the tm and sm bits
48 if (pil
< 14 && softint
& 0x10000)
49 cpu
->postInterrupt(IT_SOFT_INT
, 16);
51 cpu
->clearInterrupt(IT_SOFT_INT
, 16);
52 if (pil
< 14 && softint
& 0x1)
53 cpu
->postInterrupt(IT_SOFT_INT
, 0);
55 cpu
->clearInterrupt(IT_SOFT_INT
, 0);
57 // Copy over any of the other bits that are set
58 for (int bit
= 15; bit
> 0; --bit
) {
59 if (1 << bit
& softint
&& bit
> pil
)
60 cpu
->postInterrupt(IT_SOFT_INT
, bit
);
62 cpu
->clearInterrupt(IT_SOFT_INT
, bit
);
66 //These functions map register indices to names
68 getMiscRegName(RegIndex index
)
70 static string miscRegName
[NumMiscRegs
] =
71 {/*"y", "ccr",*/ "asi", "tick", "fprs", "pcr", "pic",
72 "gsr", "softint_set", "softint_clr", "softint", "tick_cmpr",
73 "stick", "stick_cmpr",
74 "tpc", "tnpc", "tstate", "tt", "privtick", "tba", "pstate", "tl",
75 "pil", "cwp", /*"cansave", "canrestore", "cleanwin", "otherwin",
77 "hpstate", "htstate", "hintp", "htba", "hver", "strand_sts_reg",
79 "fsr", "prictx", "secctx", "partId", "lsuCtrlReg",
80 "scratch0", "scratch1", "scratch2", "scratch3", "scratch4",
81 "scratch5", "scratch6", "scratch7", "cpuMondoHead", "cpuMondoTail",
82 "devMondoHead", "devMondoTail", "resErrorHead", "resErrorTail",
83 "nresErrorHead", "nresErrorTail", "TlbData" };
84 return miscRegName
[index
];
88 ISA::setFSReg(int miscReg
, const MiscReg
&val
, ThreadContext
*tc
)
90 BaseCPU
*cpu
= tc
->getCpuPtr();
94 /* Full system only ASRs */
96 setMiscRegNoEffect(miscReg
, val
);;
99 case MISCREG_SOFTINT_CLR
:
100 return setMiscReg(MISCREG_SOFTINT
, ~val
& softint
, tc
);
101 case MISCREG_SOFTINT_SET
:
102 return setMiscReg(MISCREG_SOFTINT
, val
| softint
, tc
);
104 case MISCREG_TICK_CMPR
:
105 if (tickCompare
== NULL
)
106 tickCompare
= new TickCompareEvent(this, tc
);
107 setMiscRegNoEffect(miscReg
, val
);
108 if ((tick_cmpr
& ~mask(63)) && tickCompare
->scheduled())
109 cpu
->deschedule(tickCompare
);
110 time
= (tick_cmpr
& mask(63)) - (tick
& mask(63));
111 if (!(tick_cmpr
& ~mask(63)) && time
> 0) {
112 if (tickCompare
->scheduled())
113 cpu
->deschedule(tickCompare
);
114 cpu
->schedule(tickCompare
, curTick
+ time
* cpu
->ticks(1));
116 panic("writing to TICK compare register %#X\n", val
);
119 case MISCREG_STICK_CMPR
:
120 if (sTickCompare
== NULL
)
121 sTickCompare
= new STickCompareEvent(this, tc
);
122 setMiscRegNoEffect(miscReg
, val
);
123 if ((stick_cmpr
& ~mask(63)) && sTickCompare
->scheduled())
124 cpu
->deschedule(sTickCompare
);
125 time
= ((int64_t)(stick_cmpr
& mask(63)) - (int64_t)stick
) -
127 if (!(stick_cmpr
& ~mask(63)) && time
> 0) {
128 if (sTickCompare
->scheduled())
129 cpu
->deschedule(sTickCompare
);
130 cpu
->schedule(sTickCompare
, curTick
+ time
* cpu
->ticks(1));
132 DPRINTF(Timer
, "writing to sTICK compare register value %#X\n", val
);
136 setMiscRegNoEffect(miscReg
, val
);
139 setMiscRegNoEffect(miscReg
, val
);
144 panic("Shouldn't be writing HVER\n");
147 setMiscRegNoEffect(miscReg
, val
);
149 cpu
->postInterrupt(IT_HINTP
, 0);
151 cpu
->clearInterrupt(IT_HINTP
, 0);
155 // clear lower 7 bits on writes.
156 setMiscRegNoEffect(miscReg
, val
& ULL(~0x7FFF));
159 case MISCREG_QUEUE_CPU_MONDO_HEAD
:
160 case MISCREG_QUEUE_CPU_MONDO_TAIL
:
161 setMiscRegNoEffect(miscReg
, val
);
162 if (cpu_mondo_head
!= cpu_mondo_tail
)
163 cpu
->postInterrupt(IT_CPU_MONDO
, 0);
165 cpu
->clearInterrupt(IT_CPU_MONDO
, 0);
167 case MISCREG_QUEUE_DEV_MONDO_HEAD
:
168 case MISCREG_QUEUE_DEV_MONDO_TAIL
:
169 setMiscRegNoEffect(miscReg
, val
);
170 if (dev_mondo_head
!= dev_mondo_tail
)
171 cpu
->postInterrupt(IT_DEV_MONDO
, 0);
173 cpu
->clearInterrupt(IT_DEV_MONDO
, 0);
175 case MISCREG_QUEUE_RES_ERROR_HEAD
:
176 case MISCREG_QUEUE_RES_ERROR_TAIL
:
177 setMiscRegNoEffect(miscReg
, val
);
178 if (res_error_head
!= res_error_tail
)
179 cpu
->postInterrupt(IT_RES_ERROR
, 0);
181 cpu
->clearInterrupt(IT_RES_ERROR
, 0);
183 case MISCREG_QUEUE_NRES_ERROR_HEAD
:
184 case MISCREG_QUEUE_NRES_ERROR_TAIL
:
185 setMiscRegNoEffect(miscReg
, val
);
186 // This one doesn't have an interrupt to report to the guest OS
189 case MISCREG_HSTICK_CMPR
:
190 if (hSTickCompare
== NULL
)
191 hSTickCompare
= new HSTickCompareEvent(this, tc
);
192 setMiscRegNoEffect(miscReg
, val
);
193 if ((hstick_cmpr
& ~mask(63)) && hSTickCompare
->scheduled())
194 cpu
->deschedule(hSTickCompare
);
195 time
= ((int64_t)(hstick_cmpr
& mask(63)) - (int64_t)stick
) -
197 if (!(hstick_cmpr
& ~mask(63)) && time
> 0) {
198 if (hSTickCompare
->scheduled())
199 cpu
->deschedule(hSTickCompare
);
200 cpu
->schedule(hSTickCompare
, curTick
+ time
* cpu
->ticks(1));
202 DPRINTF(Timer
, "writing to hsTICK compare register value %#X\n", val
);
205 case MISCREG_HPSTATE
:
206 // T1000 spec says impl. dependent val must always be 1
207 setMiscRegNoEffect(miscReg
, val
| HPSTATE::id
);
209 if (hpstate
& HPSTATE::tlz
&& tl
== 0 && !(hpstate
& HPSTATE::hpriv
))
210 cpu
->postInterrupt(IT_TRAP_LEVEL_ZERO
, 0);
212 cpu
->clearInterrupt(IT_TRAP_LEVEL_ZERO
, 0);
215 case MISCREG_HTSTATE
:
216 setMiscRegNoEffect(miscReg
, val
);
219 case MISCREG_STRAND_STS_REG
:
221 panic("No support for setting spec_en bit\n");
222 setMiscRegNoEffect(miscReg
, bits(val
,0,0));
223 if (!bits(val
,0,0)) {
224 DPRINTF(Quiesce
, "Cpu executed quiescing instruction\n");
225 // Time to go to sleep
227 if (tc
->getKernelStats())
228 tc
->getKernelStats()->quiesce();
233 panic("Invalid write to FS misc register %s\n",
234 getMiscRegName(miscReg
));
239 ISA::readFSReg(int miscReg
, ThreadContext
* tc
)
244 /* Privileged registers. */
245 case MISCREG_QUEUE_CPU_MONDO_HEAD
:
246 case MISCREG_QUEUE_CPU_MONDO_TAIL
:
247 case MISCREG_QUEUE_DEV_MONDO_HEAD
:
248 case MISCREG_QUEUE_DEV_MONDO_TAIL
:
249 case MISCREG_QUEUE_RES_ERROR_HEAD
:
250 case MISCREG_QUEUE_RES_ERROR_TAIL
:
251 case MISCREG_QUEUE_NRES_ERROR_HEAD
:
252 case MISCREG_QUEUE_NRES_ERROR_TAIL
:
253 case MISCREG_SOFTINT
:
254 case MISCREG_TICK_CMPR
:
255 case MISCREG_STICK_CMPR
:
257 case MISCREG_HPSTATE
:
259 case MISCREG_HTSTATE
:
260 case MISCREG_HSTICK_CMPR
:
261 return readMiscRegNoEffect(miscReg
) ;
264 return readMiscRegNoEffect(miscReg
) & ULL(~0x7FFF);
266 // XXX set to match Legion
267 return ULL(0x3e) << 48 |
270 //MaxGL << 16 | XXX For some reason legion doesn't set GL
274 case MISCREG_STRAND_STS_REG
:
277 sys
= tc
->getSystemPtr();
279 temp
= readMiscRegNoEffect(miscReg
) & (STS::active
| STS::speculative
);
280 // Check that the CPU array is fully populated
281 // (by calling getNumCPus())
282 assert(sys
->numContexts() > tc
->contextId());
284 temp
|= tc
->contextId() << STS::shft_id
;
286 for (x
= tc
->contextId() & ~3; x
< sys
->threadContexts
.size(); x
++) {
287 switch (sys
->threadContexts
[x
]->status()) {
288 case ThreadContext::Active
:
289 temp
|= STS::st_run
<< (STS::shft_fsm0
-
290 ((x
& 0x3) * (STS::shft_fsm0
-STS::shft_fsm1
)));
292 case ThreadContext::Suspended
:
293 // should this be idle?
294 temp
|= STS::st_idle
<< (STS::shft_fsm0
-
295 ((x
& 0x3) * (STS::shft_fsm0
-STS::shft_fsm1
)));
297 case ThreadContext::Halted
:
298 temp
|= STS::st_halt
<< (STS::shft_fsm0
-
299 ((x
& 0x3) * (STS::shft_fsm0
-STS::shft_fsm1
)));
302 panic("What state are we in?!\n");
308 panic("Invalid read to FS misc register\n");
313 ISA::processTickCompare(ThreadContext
*tc
)
315 panic("tick compare not implemented\n");
319 ISA::processSTickCompare(ThreadContext
*tc
)
321 BaseCPU
*cpu
= tc
->getCpuPtr();
323 // since our microcode instructions take two cycles we need to check if
324 // we're actually at the correct cycle or we need to wait a little while
327 ticks
= ((int64_t)(stick_cmpr
& mask(63)) - (int64_t)stick
) -
329 assert(ticks
>= 0 && "stick compare missed interrupt cycle");
331 if (ticks
== 0 || tc
->status() == ThreadContext::Suspended
) {
332 DPRINTF(Timer
, "STick compare cycle reached at %#x\n",
333 (stick_cmpr
& mask(63)));
334 if (!(tc
->readMiscRegNoEffect(MISCREG_STICK_CMPR
) & (ULL(1) << 63))) {
335 setMiscReg(MISCREG_SOFTINT
, softint
| (ULL(1) << 16), tc
);
338 cpu
->schedule(sTickCompare
, curTick
+ ticks
* cpu
->ticks(1));
342 ISA::processHSTickCompare(ThreadContext
*tc
)
344 BaseCPU
*cpu
= tc
->getCpuPtr();
346 // since our microcode instructions take two cycles we need to check if
347 // we're actually at the correct cycle or we need to wait a little while
350 if ( tc
->status() == ThreadContext::Halted
)
353 ticks
= ((int64_t)(hstick_cmpr
& mask(63)) - (int64_t)stick
) -
355 assert(ticks
>= 0 && "hstick compare missed interrupt cycle");
357 if (ticks
== 0 || tc
->status() == ThreadContext::Suspended
) {
358 DPRINTF(Timer
, "HSTick compare cycle reached at %#x\n",
359 (stick_cmpr
& mask(63)));
360 if (!(tc
->readMiscRegNoEffect(MISCREG_HSTICK_CMPR
) & (ULL(1) << 63))) {
361 setMiscReg(MISCREG_HINTP
, 1, tc
);
363 // Need to do something to cause interrupt to happen here !!! @todo
365 cpu
->schedule(hSTickCompare
, curTick
+ ticks
* cpu
->ticks(1));