src/arch/sparc/ua2005.cc

   1 /*
   2  * Copyright (c) 2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #include "arch/sparc/kernel_stats.hh"
  30 #include "arch/sparc/miscregfile.hh"
  31 #include "base/bitfield.hh"
  32 #include "base/trace.hh"
  33 #include "cpu/base.hh"
  34 #include "cpu/thread_context.hh"
  35 #include "sim/system.hh"
  36
  37 using namespace SparcISA;
  38 using namespace std;
  39
  40
  41 void
  42 MiscRegFile::checkSoftInt(ThreadContext *tc)
  43 {
  44     BaseCPU *cpu = tc->getCpuPtr();
  45
  46     // If PIL < 14, copy over the tm and sm bits
  47     if (pil < 14 && softint & 0x10000)
  48         cpu->postInterrupt(IT_SOFT_INT, 16);
  49     else
  50         cpu->clearInterrupt(IT_SOFT_INT, 16);
  51     if (pil < 14 && softint & 0x1)
  52         cpu->postInterrupt(IT_SOFT_INT, 0);
  53     else
  54         cpu->clearInterrupt(IT_SOFT_INT, 0);
  55
  56     // Copy over any of the other bits that are set
  57     for (int bit = 15; bit > 0; --bit) {
  58         if (1 << bit & softint && bit > pil)
  59             cpu->postInterrupt(IT_SOFT_INT, bit);
  60         else
  61             cpu->clearInterrupt(IT_SOFT_INT, bit);
  62     }
  63 }
  64
  65 //These functions map register indices to names
  66 static inline string
  67 getMiscRegName(RegIndex index)
  68 {
  69     static string miscRegName[NumMiscRegs] =
  70         {/*"y", "ccr",*/ "asi", "tick", "fprs", "pcr", "pic",
  71          "gsr", "softint_set", "softint_clr", "softint", "tick_cmpr",
  72          "stick", "stick_cmpr",
  73          "tpc", "tnpc", "tstate", "tt", "privtick", "tba", "pstate", "tl",
  74          "pil", "cwp", /*"cansave", "canrestore", "cleanwin", "otherwin",
  75          "wstate",*/ "gl",
  76          "hpstate", "htstate", "hintp", "htba", "hver", "strand_sts_reg",
  77          "hstick_cmpr",
  78          "fsr", "prictx", "secctx", "partId", "lsuCtrlReg",
  79          "scratch0", "scratch1", "scratch2", "scratch3", "scratch4",
  80          "scratch5", "scratch6", "scratch7", "cpuMondoHead", "cpuMondoTail",
  81          "devMondoHead", "devMondoTail", "resErrorHead", "resErrorTail",
  82          "nresErrorHead", "nresErrorTail", "TlbData" };
  83     return miscRegName[index];
  84 }
  85
  86 void
  87 MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
  88 {
  89     BaseCPU *cpu = tc->getCpuPtr();
  90
  91     int64_t time;
  92     switch (miscReg) {
  93         /* Full system only ASRs */
  94       case MISCREG_SOFTINT:
  95         setRegNoEffect(miscReg, val);;
  96         checkSoftInt(tc);
  97         break;
  98       case MISCREG_SOFTINT_CLR:
  99         return setReg(MISCREG_SOFTINT, ~val & softint, tc);
 100       case MISCREG_SOFTINT_SET:
 101         return setReg(MISCREG_SOFTINT, val | softint, tc);
 102
 103       case MISCREG_TICK_CMPR:
 104         if (tickCompare == NULL)
 105             tickCompare = new TickCompareEvent(this, tc);
 106         setRegNoEffect(miscReg, val);
 107         if ((tick_cmpr & ~mask(63)) && tickCompare->scheduled())
 108             cpu->deschedule(tickCompare);
 109         time = (tick_cmpr & mask(63)) - (tick & mask(63));
 110         if (!(tick_cmpr & ~mask(63)) && time > 0) {
 111             if (tickCompare->scheduled())
 112                 cpu->deschedule(tickCompare);
 113             cpu->schedule(tickCompare, curTick + time * cpu->ticks(1));
 114         }
 115         panic("writing to TICK compare register %#X\n", val);
 116         break;
 117
 118       case MISCREG_STICK_CMPR:
 119         if (sTickCompare == NULL)
 120             sTickCompare = new STickCompareEvent(this, tc);
 121         setRegNoEffect(miscReg, val);
 122         if ((stick_cmpr & ~mask(63)) && sTickCompare->scheduled())
 123             cpu->deschedule(sTickCompare);
 124         time = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) -
 125             cpu->instCount();
 126         if (!(stick_cmpr & ~mask(63)) && time > 0) {
 127             if (sTickCompare->scheduled())
 128                 cpu->deschedule(sTickCompare);
 129             cpu->schedule(sTickCompare, curTick + time * cpu->ticks(1));
 130         }
 131         DPRINTF(Timer, "writing to sTICK compare register value %#X\n", val);
 132         break;
 133
 134       case MISCREG_PSTATE:
 135         setRegNoEffect(miscReg, val);
 136
 137       case MISCREG_PIL:
 138         setRegNoEffect(miscReg, val);
 139         checkSoftInt(tc);
 140         break;
 141
 142       case MISCREG_HVER:
 143         panic("Shouldn't be writing HVER\n");
 144
 145       case MISCREG_HINTP:
 146         setRegNoEffect(miscReg, val);
 147         if (hintp)
 148             cpu->postInterrupt(IT_HINTP, 0);
 149         else
 150             cpu->clearInterrupt(IT_HINTP, 0);
 151         break;
 152
 153       case MISCREG_HTBA:
 154         // clear lower 7 bits on writes.
 155         setRegNoEffect(miscReg, val & ULL(~0x7FFF));
 156         break;
 157
 158       case MISCREG_QUEUE_CPU_MONDO_HEAD:
 159       case MISCREG_QUEUE_CPU_MONDO_TAIL:
 160         setRegNoEffect(miscReg, val);
 161         if (cpu_mondo_head != cpu_mondo_tail)
 162             cpu->postInterrupt(IT_CPU_MONDO, 0);
 163         else
 164             cpu->clearInterrupt(IT_CPU_MONDO, 0);
 165         break;
 166       case MISCREG_QUEUE_DEV_MONDO_HEAD:
 167       case MISCREG_QUEUE_DEV_MONDO_TAIL:
 168         setRegNoEffect(miscReg, val);
 169         if (dev_mondo_head != dev_mondo_tail)
 170             cpu->postInterrupt(IT_DEV_MONDO, 0);
 171         else
 172             cpu->clearInterrupt(IT_DEV_MONDO, 0);
 173         break;
 174       case MISCREG_QUEUE_RES_ERROR_HEAD:
 175       case MISCREG_QUEUE_RES_ERROR_TAIL:
 176         setRegNoEffect(miscReg, val);
 177         if (res_error_head != res_error_tail)
 178             cpu->postInterrupt(IT_RES_ERROR, 0);
 179         else
 180             cpu->clearInterrupt(IT_RES_ERROR, 0);
 181         break;
 182       case MISCREG_QUEUE_NRES_ERROR_HEAD:
 183       case MISCREG_QUEUE_NRES_ERROR_TAIL:
 184         setRegNoEffect(miscReg, val);
 185         // This one doesn't have an interrupt to report to the guest OS
 186         break;
 187
 188       case MISCREG_HSTICK_CMPR:
 189         if (hSTickCompare == NULL)
 190             hSTickCompare = new HSTickCompareEvent(this, tc);
 191         setRegNoEffect(miscReg, val);
 192         if ((hstick_cmpr & ~mask(63)) && hSTickCompare->scheduled())
 193             cpu->deschedule(hSTickCompare);
 194         time = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) -
 195             cpu->instCount();
 196         if (!(hstick_cmpr & ~mask(63)) && time > 0) {
 197             if (hSTickCompare->scheduled())
 198                 cpu->deschedule(hSTickCompare);
 199             cpu->schedule(hSTickCompare, curTick + time * cpu->ticks(1));
 200         }
 201         DPRINTF(Timer, "writing to hsTICK compare register value %#X\n", val);
 202         break;
 203
 204       case MISCREG_HPSTATE:
 205         // T1000 spec says impl. dependent val must always be 1
 206         setRegNoEffect(miscReg, val | HPSTATE::id);
 207 #if FULL_SYSTEM
 208         if (hpstate & HPSTATE::tlz && tl == 0 && !(hpstate & HPSTATE::hpriv))
 209             cpu->postInterrupt(IT_TRAP_LEVEL_ZERO, 0);
 210         else
 211             cpu->clearInterrupt(IT_TRAP_LEVEL_ZERO, 0);
 212 #endif
 213         break;
 214       case MISCREG_HTSTATE:
 215         setRegNoEffect(miscReg, val);
 216         break;
 217
 218       case MISCREG_STRAND_STS_REG:
 219         if (bits(val,2,2))
 220             panic("No support for setting spec_en bit\n");
 221         setRegNoEffect(miscReg, bits(val,0,0));
 222         if (!bits(val,0,0)) {
 223             DPRINTF(Quiesce, "Cpu executed quiescing instruction\n");
 224             // Time to go to sleep
 225             tc->suspend();
 226             if (tc->getKernelStats())
 227                 tc->getKernelStats()->quiesce();
 228         }
 229         break;
 230
 231       default:
 232         panic("Invalid write to FS misc register %s\n",
 233               getMiscRegName(miscReg));
 234     }
 235 }
 236
 237 MiscReg
 238 MiscRegFile::readFSReg(int miscReg, ThreadContext * tc)
 239 {
 240     uint64_t temp;
 241
 242     switch (miscReg) {
 243         /* Privileged registers. */
 244       case MISCREG_QUEUE_CPU_MONDO_HEAD:
 245       case MISCREG_QUEUE_CPU_MONDO_TAIL:
 246       case MISCREG_QUEUE_DEV_MONDO_HEAD:
 247       case MISCREG_QUEUE_DEV_MONDO_TAIL:
 248       case MISCREG_QUEUE_RES_ERROR_HEAD:
 249       case MISCREG_QUEUE_RES_ERROR_TAIL:
 250       case MISCREG_QUEUE_NRES_ERROR_HEAD:
 251       case MISCREG_QUEUE_NRES_ERROR_TAIL:
 252       case MISCREG_SOFTINT:
 253       case MISCREG_TICK_CMPR:
 254       case MISCREG_STICK_CMPR:
 255       case MISCREG_PIL:
 256       case MISCREG_HPSTATE:
 257       case MISCREG_HINTP:
 258       case MISCREG_HTSTATE:
 259       case MISCREG_HSTICK_CMPR:
 260         return readRegNoEffect(miscReg) ;
 261
 262       case MISCREG_HTBA:
 263         return readRegNoEffect(miscReg) & ULL(~0x7FFF);
 264       case MISCREG_HVER:
 265         // XXX set to match Legion
 266         return ULL(0x3e) << 48 |
 267                ULL(0x23) << 32 |
 268                ULL(0x20) << 24 |
 269                    //MaxGL << 16 | XXX For some reason legion doesn't set GL
 270                    MaxTL << 8  |
 271            (NWindows -1) << 0;
 272
 273       case MISCREG_STRAND_STS_REG:
 274         System *sys;
 275         int x;
 276         sys = tc->getSystemPtr();
 277
 278         temp = readRegNoEffect(miscReg) & (STS::active | STS::speculative);
 279         // Check that the CPU array is fully populated
 280         // (by calling getNumCPus())
 281         assert(sys->numContexts() > tc->contextId());
 282
 283         temp |= tc->contextId()  << STS::shft_id;
 284
 285         for (x = tc->contextId() & ~3; x < sys->threadContexts.size(); x++) {
 286             switch (sys->threadContexts[x]->status()) {
 287               case ThreadContext::Active:
 288                 temp |= STS::st_run << (STS::shft_fsm0 -
 289                         ((x & 0x3) * (STS::shft_fsm0-STS::shft_fsm1)));
 290                 break;
 291               case ThreadContext::Suspended:
 292                 // should this be idle?
 293                 temp |= STS::st_idle << (STS::shft_fsm0 -
 294                         ((x & 0x3) * (STS::shft_fsm0-STS::shft_fsm1)));
 295                 break;
 296               case ThreadContext::Halted:
 297                 temp |= STS::st_halt << (STS::shft_fsm0 -
 298                         ((x & 0x3) * (STS::shft_fsm0-STS::shft_fsm1)));
 299                 break;
 300               default:
 301                 panic("What state are we in?!\n");
 302             } // switch
 303         } // for
 304
 305         return temp;
 306       default:
 307         panic("Invalid read to FS misc register\n");
 308     }
 309 }
 310
 311 void
 312 MiscRegFile::processTickCompare(ThreadContext *tc)
 313 {
 314     panic("tick compare not implemented\n");
 315 }
 316
 317 void
 318 MiscRegFile::processSTickCompare(ThreadContext *tc)
 319 {
 320     BaseCPU *cpu = tc->getCpuPtr();
 321
 322     // since our microcode instructions take two cycles we need to check if
 323     // we're actually at the correct cycle or we need to wait a little while
 324     // more
 325     int ticks;
 326     ticks = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) -
 327         cpu->instCount();
 328     assert(ticks >= 0 && "stick compare missed interrupt cycle");
 329
 330     if (ticks == 0 || tc->status() == ThreadContext::Suspended) {
 331         DPRINTF(Timer, "STick compare cycle reached at %#x\n",
 332                 (stick_cmpr & mask(63)));
 333         if (!(tc->readMiscRegNoEffect(MISCREG_STICK_CMPR) & (ULL(1) << 63))) {
 334             setReg(MISCREG_SOFTINT, softint | (ULL(1) << 16), tc);
 335         }
 336     } else
 337         cpu->schedule(sTickCompare, curTick + ticks * cpu->ticks(1));
 338 }
 339
 340 void
 341 MiscRegFile::processHSTickCompare(ThreadContext *tc)
 342 {
 343     BaseCPU *cpu = tc->getCpuPtr();
 344
 345     // since our microcode instructions take two cycles we need to check if
 346     // we're actually at the correct cycle or we need to wait a little while
 347     // more
 348     int ticks;
 349     if ( tc->status() == ThreadContext::Halted)
 350        return;
 351
 352     ticks = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) -
 353         cpu->instCount();
 354     assert(ticks >= 0 && "hstick compare missed interrupt cycle");
 355
 356     if (ticks == 0 || tc->status() == ThreadContext::Suspended) {
 357         DPRINTF(Timer, "HSTick compare cycle reached at %#x\n",
 358                 (stick_cmpr & mask(63)));
 359         if (!(tc->readMiscRegNoEffect(MISCREG_HSTICK_CMPR) & (ULL(1) << 63))) {
 360             setReg(MISCREG_HINTP, 1, tc);
 361         }
 362         // Need to do something to cause interrupt to happen here !!! @todo
 363     } else
 364         cpu->schedule(hSTickCompare, curTick + ticks * cpu->ticks(1));
 365 }
 366