2 * Copyright (c) 2006 The Regents of The University of Michigan
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29 #include "arch/sparc/isa.hh"
30 #include "arch/sparc/kernel_stats.hh"
31 #include "arch/sparc/registers.hh"
32 #include "base/bitfield.hh"
33 #include "base/trace.hh"
34 #include "cpu/base.hh"
35 #include "cpu/thread_context.hh"
36 #include "debug/Quiesce.hh"
37 #include "debug/Timer.hh"
38 #include "sim/full_system.hh"
39 #include "sim/system.hh"
41 using namespace SparcISA
;
46 ISA::checkSoftInt(ThreadContext
*tc
)
48 BaseCPU
*cpu
= tc
->getCpuPtr();
50 // If PIL < 14, copy over the tm and sm bits
51 if (pil
< 14 && softint
& 0x10000)
52 cpu
->postInterrupt(0, IT_SOFT_INT
, 16);
54 cpu
->clearInterrupt(0, IT_SOFT_INT
, 16);
55 if (pil
< 14 && softint
& 0x1)
56 cpu
->postInterrupt(0, IT_SOFT_INT
, 0);
58 cpu
->clearInterrupt(0, IT_SOFT_INT
, 0);
60 // Copy over any of the other bits that are set
61 for (int bit
= 15; bit
> 0; --bit
) {
62 if (1 << bit
& softint
&& bit
> pil
)
63 cpu
->postInterrupt(0, IT_SOFT_INT
, bit
);
65 cpu
->clearInterrupt(0, IT_SOFT_INT
, bit
);
69 // These functions map register indices to names
71 getMiscRegName(RegIndex index
)
73 static string miscRegName
[NumMiscRegs
] =
74 {/*"y", "ccr",*/ "asi", "tick", "fprs", "pcr", "pic",
75 "gsr", "softint_set", "softint_clr", "softint", "tick_cmpr",
76 "stick", "stick_cmpr",
77 "tpc", "tnpc", "tstate", "tt", "privtick", "tba", "pstate", "tl",
78 "pil", "cwp", /*"cansave", "canrestore", "cleanwin", "otherwin",
80 "hpstate", "htstate", "hintp", "htba", "hver", "strand_sts_reg",
82 "fsr", "prictx", "secctx", "partId", "lsuCtrlReg",
83 "scratch0", "scratch1", "scratch2", "scratch3", "scratch4",
84 "scratch5", "scratch6", "scratch7", "cpuMondoHead", "cpuMondoTail",
85 "devMondoHead", "devMondoTail", "resErrorHead", "resErrorTail",
86 "nresErrorHead", "nresErrorTail", "TlbData" };
87 return miscRegName
[index
];
91 ISA::setFSReg(int miscReg
, const MiscReg
&val
, ThreadContext
*tc
)
93 BaseCPU
*cpu
= tc
->getCpuPtr();
97 /* Full system only ASRs */
99 setMiscRegNoEffect(miscReg
, val
);;
102 case MISCREG_SOFTINT_CLR
:
103 return setMiscReg(MISCREG_SOFTINT
, ~val
& softint
, tc
);
104 case MISCREG_SOFTINT_SET
:
105 return setMiscReg(MISCREG_SOFTINT
, val
| softint
, tc
);
107 case MISCREG_TICK_CMPR
:
108 if (tickCompare
== NULL
)
109 tickCompare
= new TickCompareEvent(this, tc
);
110 setMiscRegNoEffect(miscReg
, val
);
111 if ((tick_cmpr
& ~mask(63)) && tickCompare
->scheduled())
112 cpu
->deschedule(tickCompare
);
113 time
= (tick_cmpr
& mask(63)) - (tick
& mask(63));
114 if (!(tick_cmpr
& ~mask(63)) && time
> 0) {
115 if (tickCompare
->scheduled())
116 cpu
->deschedule(tickCompare
);
117 cpu
->schedule(tickCompare
, cpu
->clockEdge(Cycles(time
)));
119 DPRINTF(Timer
, "writing to TICK compare register value %#X\n", val
);
122 case MISCREG_STICK_CMPR
:
123 if (sTickCompare
== NULL
)
124 sTickCompare
= new STickCompareEvent(this, tc
);
125 setMiscRegNoEffect(miscReg
, val
);
126 if ((stick_cmpr
& ~mask(63)) && sTickCompare
->scheduled())
127 cpu
->deschedule(sTickCompare
);
128 time
= ((int64_t)(stick_cmpr
& mask(63)) - (int64_t)stick
) -
130 if (!(stick_cmpr
& ~mask(63)) && time
> 0) {
131 if (sTickCompare
->scheduled())
132 cpu
->deschedule(sTickCompare
);
133 cpu
->schedule(sTickCompare
, cpu
->clockEdge(Cycles(time
)));
135 DPRINTF(Timer
, "writing to sTICK compare register value %#X\n", val
);
139 setMiscRegNoEffect(miscReg
, val
);
143 setMiscRegNoEffect(miscReg
, val
);
148 panic("Shouldn't be writing HVER\n");
151 setMiscRegNoEffect(miscReg
, val
);
153 cpu
->postInterrupt(0, IT_HINTP
, 0);
155 cpu
->clearInterrupt(0, IT_HINTP
, 0);
159 // clear lower 7 bits on writes.
160 setMiscRegNoEffect(miscReg
, val
& ULL(~0x7FFF));
163 case MISCREG_QUEUE_CPU_MONDO_HEAD
:
164 case MISCREG_QUEUE_CPU_MONDO_TAIL
:
165 setMiscRegNoEffect(miscReg
, val
);
166 if (cpu_mondo_head
!= cpu_mondo_tail
)
167 cpu
->postInterrupt(0, IT_CPU_MONDO
, 0);
169 cpu
->clearInterrupt(0, IT_CPU_MONDO
, 0);
171 case MISCREG_QUEUE_DEV_MONDO_HEAD
:
172 case MISCREG_QUEUE_DEV_MONDO_TAIL
:
173 setMiscRegNoEffect(miscReg
, val
);
174 if (dev_mondo_head
!= dev_mondo_tail
)
175 cpu
->postInterrupt(0, IT_DEV_MONDO
, 0);
177 cpu
->clearInterrupt(0, IT_DEV_MONDO
, 0);
179 case MISCREG_QUEUE_RES_ERROR_HEAD
:
180 case MISCREG_QUEUE_RES_ERROR_TAIL
:
181 setMiscRegNoEffect(miscReg
, val
);
182 if (res_error_head
!= res_error_tail
)
183 cpu
->postInterrupt(0, IT_RES_ERROR
, 0);
185 cpu
->clearInterrupt(0, IT_RES_ERROR
, 0);
187 case MISCREG_QUEUE_NRES_ERROR_HEAD
:
188 case MISCREG_QUEUE_NRES_ERROR_TAIL
:
189 setMiscRegNoEffect(miscReg
, val
);
190 // This one doesn't have an interrupt to report to the guest OS
193 case MISCREG_HSTICK_CMPR
:
194 if (hSTickCompare
== NULL
)
195 hSTickCompare
= new HSTickCompareEvent(this, tc
);
196 setMiscRegNoEffect(miscReg
, val
);
197 if ((hstick_cmpr
& ~mask(63)) && hSTickCompare
->scheduled())
198 cpu
->deschedule(hSTickCompare
);
199 time
= ((int64_t)(hstick_cmpr
& mask(63)) - (int64_t)stick
) -
201 if (!(hstick_cmpr
& ~mask(63)) && time
> 0) {
202 if (hSTickCompare
->scheduled())
203 cpu
->deschedule(hSTickCompare
);
204 cpu
->schedule(hSTickCompare
, cpu
->clockEdge(Cycles(time
)));
206 DPRINTF(Timer
, "writing to hsTICK compare register value %#X\n", val
);
209 case MISCREG_HPSTATE
:
211 HPSTATE newVal
= val
;
213 // T1000 spec says impl. dependent val must always be 1
214 setMiscRegNoEffect(miscReg
, newVal
);
216 if (newVal
.tlz
&& tl
== 0 && !newVal
.hpriv
)
217 cpu
->postInterrupt(0, IT_TRAP_LEVEL_ZERO
, 0);
219 cpu
->clearInterrupt(0, IT_TRAP_LEVEL_ZERO
, 0);
222 case MISCREG_HTSTATE
:
223 setMiscRegNoEffect(miscReg
, val
);
226 case MISCREG_STRAND_STS_REG
:
228 panic("No support for setting spec_en bit\n");
229 setMiscRegNoEffect(miscReg
, bits(val
,0,0));
230 if (!bits(val
,0,0)) {
231 DPRINTF(Quiesce
, "Cpu executed quiescing instruction\n");
232 // Time to go to sleep
234 if (FullSystem
&& tc
->getKernelStats())
235 tc
->getKernelStats()->quiesce();
240 panic("Invalid write to FS misc register %s\n",
241 getMiscRegName(miscReg
));
246 ISA::readFSReg(int miscReg
, ThreadContext
* tc
)
251 /* Privileged registers. */
252 case MISCREG_QUEUE_CPU_MONDO_HEAD
:
253 case MISCREG_QUEUE_CPU_MONDO_TAIL
:
254 case MISCREG_QUEUE_DEV_MONDO_HEAD
:
255 case MISCREG_QUEUE_DEV_MONDO_TAIL
:
256 case MISCREG_QUEUE_RES_ERROR_HEAD
:
257 case MISCREG_QUEUE_RES_ERROR_TAIL
:
258 case MISCREG_QUEUE_NRES_ERROR_HEAD
:
259 case MISCREG_QUEUE_NRES_ERROR_TAIL
:
260 case MISCREG_SOFTINT
:
261 case MISCREG_TICK_CMPR
:
262 case MISCREG_STICK_CMPR
:
264 case MISCREG_HPSTATE
:
266 case MISCREG_HTSTATE
:
267 case MISCREG_HSTICK_CMPR
:
268 return readMiscRegNoEffect(miscReg
) ;
271 return readMiscRegNoEffect(miscReg
) & ULL(~0x7FFF);
273 // XXX set to match Legion
274 return ULL(0x3e) << 48 |
277 // MaxGL << 16 | XXX For some reason legion doesn't set GL
281 case MISCREG_STRAND_STS_REG
:
284 sys
= tc
->getSystemPtr();
286 temp
= readMiscRegNoEffect(miscReg
) & (STS::active
| STS::speculative
);
287 // Check that the CPU array is fully populated
288 // (by calling getNumCPus())
289 assert(sys
->numContexts() > tc
->contextId());
291 temp
|= tc
->contextId() << STS::shft_id
;
293 for (x
= tc
->contextId() & ~3; x
< sys
->threadContexts
.size(); x
++) {
294 switch (sys
->threadContexts
[x
]->status()) {
295 case ThreadContext::Active
:
296 temp
|= STS::st_run
<< (STS::shft_fsm0
-
297 ((x
& 0x3) * (STS::shft_fsm0
-STS::shft_fsm1
)));
299 case ThreadContext::Suspended
:
300 // should this be idle?
301 temp
|= STS::st_idle
<< (STS::shft_fsm0
-
302 ((x
& 0x3) * (STS::shft_fsm0
-STS::shft_fsm1
)));
304 case ThreadContext::Halted
:
305 temp
|= STS::st_halt
<< (STS::shft_fsm0
-
306 ((x
& 0x3) * (STS::shft_fsm0
-STS::shft_fsm1
)));
309 panic("What state are we in?!\n");
315 panic("Invalid read to FS misc register\n");
320 ISA::processTickCompare(ThreadContext
*tc
)
322 panic("tick compare not implemented\n");
326 ISA::processSTickCompare(ThreadContext
*tc
)
328 BaseCPU
*cpu
= tc
->getCpuPtr();
330 // since our microcode instructions take two cycles we need to check if
331 // we're actually at the correct cycle or we need to wait a little while
334 delay
= ((int64_t)(stick_cmpr
& mask(63)) - (int64_t)stick
) -
336 assert(delay
>= 0 && "stick compare missed interrupt cycle");
338 if (delay
== 0 || tc
->status() == ThreadContext::Suspended
) {
339 DPRINTF(Timer
, "STick compare cycle reached at %#x\n",
340 (stick_cmpr
& mask(63)));
341 if (!(tc
->readMiscRegNoEffect(MISCREG_STICK_CMPR
) & (ULL(1) << 63))) {
342 setMiscReg(MISCREG_SOFTINT
, softint
| (ULL(1) << 16), tc
);
345 cpu
->schedule(sTickCompare
, cpu
->clockEdge(Cycles(delay
)));
350 ISA::processHSTickCompare(ThreadContext
*tc
)
352 BaseCPU
*cpu
= tc
->getCpuPtr();
354 // since our microcode instructions take two cycles we need to check if
355 // we're actually at the correct cycle or we need to wait a little while
358 if ( tc
->status() == ThreadContext::Halted
)
361 delay
= ((int64_t)(hstick_cmpr
& mask(63)) - (int64_t)stick
) -
363 assert(delay
>= 0 && "hstick compare missed interrupt cycle");
365 if (delay
== 0 || tc
->status() == ThreadContext::Suspended
) {
366 DPRINTF(Timer
, "HSTick compare cycle reached at %#x\n",
367 (stick_cmpr
& mask(63)));
368 if (!(tc
->readMiscRegNoEffect(MISCREG_HSTICK_CMPR
) & (ULL(1) << 63))) {
369 setMiscReg(MISCREG_HINTP
, 1, tc
);
371 // Need to do something to cause interrupt to happen here !!! @todo
373 cpu
->schedule(hSTickCompare
, cpu
->clockEdge(Cycles(delay
)));