2 * Copyright (c) 2006 The Regents of The University of Michigan
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29 #include "arch/sparc/isa.hh"
30 #include "arch/sparc/kernel_stats.hh"
31 #include "arch/sparc/registers.hh"
32 #include "base/bitfield.hh"
33 #include "base/trace.hh"
34 #include "cpu/base.hh"
35 #include "cpu/thread_context.hh"
36 #include "debug/Quiesce.hh"
37 #include "debug/Timer.hh"
38 #include "sim/system.hh"
40 using namespace SparcISA
;
45 ISA::checkSoftInt(ThreadContext
*tc
)
47 BaseCPU
*cpu
= tc
->getCpuPtr();
49 // If PIL < 14, copy over the tm and sm bits
50 if (pil
< 14 && softint
& 0x10000)
51 cpu
->postInterrupt(IT_SOFT_INT
, 16);
53 cpu
->clearInterrupt(IT_SOFT_INT
, 16);
54 if (pil
< 14 && softint
& 0x1)
55 cpu
->postInterrupt(IT_SOFT_INT
, 0);
57 cpu
->clearInterrupt(IT_SOFT_INT
, 0);
59 // Copy over any of the other bits that are set
60 for (int bit
= 15; bit
> 0; --bit
) {
61 if (1 << bit
& softint
&& bit
> pil
)
62 cpu
->postInterrupt(IT_SOFT_INT
, bit
);
64 cpu
->clearInterrupt(IT_SOFT_INT
, bit
);
68 // These functions map register indices to names
70 getMiscRegName(RegIndex index
)
72 static string miscRegName
[NumMiscRegs
] =
73 {/*"y", "ccr",*/ "asi", "tick", "fprs", "pcr", "pic",
74 "gsr", "softint_set", "softint_clr", "softint", "tick_cmpr",
75 "stick", "stick_cmpr",
76 "tpc", "tnpc", "tstate", "tt", "privtick", "tba", "pstate", "tl",
77 "pil", "cwp", /*"cansave", "canrestore", "cleanwin", "otherwin",
79 "hpstate", "htstate", "hintp", "htba", "hver", "strand_sts_reg",
81 "fsr", "prictx", "secctx", "partId", "lsuCtrlReg",
82 "scratch0", "scratch1", "scratch2", "scratch3", "scratch4",
83 "scratch5", "scratch6", "scratch7", "cpuMondoHead", "cpuMondoTail",
84 "devMondoHead", "devMondoTail", "resErrorHead", "resErrorTail",
85 "nresErrorHead", "nresErrorTail", "TlbData" };
86 return miscRegName
[index
];
90 ISA::setFSReg(int miscReg
, const MiscReg
&val
, ThreadContext
*tc
)
92 BaseCPU
*cpu
= tc
->getCpuPtr();
96 /* Full system only ASRs */
98 setMiscRegNoEffect(miscReg
, val
);;
101 case MISCREG_SOFTINT_CLR
:
102 return setMiscReg(MISCREG_SOFTINT
, ~val
& softint
, tc
);
103 case MISCREG_SOFTINT_SET
:
104 return setMiscReg(MISCREG_SOFTINT
, val
| softint
, tc
);
106 case MISCREG_TICK_CMPR
:
107 if (tickCompare
== NULL
)
108 tickCompare
= new TickCompareEvent(this, tc
);
109 setMiscRegNoEffect(miscReg
, val
);
110 if ((tick_cmpr
& ~mask(63)) && tickCompare
->scheduled())
111 cpu
->deschedule(tickCompare
);
112 time
= (tick_cmpr
& mask(63)) - (tick
& mask(63));
113 if (!(tick_cmpr
& ~mask(63)) && time
> 0) {
114 if (tickCompare
->scheduled())
115 cpu
->deschedule(tickCompare
);
116 cpu
->schedule(tickCompare
, curTick() + time
* cpu
->ticks(1));
118 panic("writing to TICK compare register %#X\n", val
);
121 case MISCREG_STICK_CMPR
:
122 if (sTickCompare
== NULL
)
123 sTickCompare
= new STickCompareEvent(this, tc
);
124 setMiscRegNoEffect(miscReg
, val
);
125 if ((stick_cmpr
& ~mask(63)) && sTickCompare
->scheduled())
126 cpu
->deschedule(sTickCompare
);
127 time
= ((int64_t)(stick_cmpr
& mask(63)) - (int64_t)stick
) -
129 if (!(stick_cmpr
& ~mask(63)) && time
> 0) {
130 if (sTickCompare
->scheduled())
131 cpu
->deschedule(sTickCompare
);
132 cpu
->schedule(sTickCompare
, curTick() + time
* cpu
->ticks(1));
134 DPRINTF(Timer
, "writing to sTICK compare register value %#X\n", val
);
138 setMiscRegNoEffect(miscReg
, val
);
141 setMiscRegNoEffect(miscReg
, val
);
146 panic("Shouldn't be writing HVER\n");
149 setMiscRegNoEffect(miscReg
, val
);
151 cpu
->postInterrupt(IT_HINTP
, 0);
153 cpu
->clearInterrupt(IT_HINTP
, 0);
157 // clear lower 7 bits on writes.
158 setMiscRegNoEffect(miscReg
, val
& ULL(~0x7FFF));
161 case MISCREG_QUEUE_CPU_MONDO_HEAD
:
162 case MISCREG_QUEUE_CPU_MONDO_TAIL
:
163 setMiscRegNoEffect(miscReg
, val
);
164 if (cpu_mondo_head
!= cpu_mondo_tail
)
165 cpu
->postInterrupt(IT_CPU_MONDO
, 0);
167 cpu
->clearInterrupt(IT_CPU_MONDO
, 0);
169 case MISCREG_QUEUE_DEV_MONDO_HEAD
:
170 case MISCREG_QUEUE_DEV_MONDO_TAIL
:
171 setMiscRegNoEffect(miscReg
, val
);
172 if (dev_mondo_head
!= dev_mondo_tail
)
173 cpu
->postInterrupt(IT_DEV_MONDO
, 0);
175 cpu
->clearInterrupt(IT_DEV_MONDO
, 0);
177 case MISCREG_QUEUE_RES_ERROR_HEAD
:
178 case MISCREG_QUEUE_RES_ERROR_TAIL
:
179 setMiscRegNoEffect(miscReg
, val
);
180 if (res_error_head
!= res_error_tail
)
181 cpu
->postInterrupt(IT_RES_ERROR
, 0);
183 cpu
->clearInterrupt(IT_RES_ERROR
, 0);
185 case MISCREG_QUEUE_NRES_ERROR_HEAD
:
186 case MISCREG_QUEUE_NRES_ERROR_TAIL
:
187 setMiscRegNoEffect(miscReg
, val
);
188 // This one doesn't have an interrupt to report to the guest OS
191 case MISCREG_HSTICK_CMPR
:
192 if (hSTickCompare
== NULL
)
193 hSTickCompare
= new HSTickCompareEvent(this, tc
);
194 setMiscRegNoEffect(miscReg
, val
);
195 if ((hstick_cmpr
& ~mask(63)) && hSTickCompare
->scheduled())
196 cpu
->deschedule(hSTickCompare
);
197 time
= ((int64_t)(hstick_cmpr
& mask(63)) - (int64_t)stick
) -
199 if (!(hstick_cmpr
& ~mask(63)) && time
> 0) {
200 if (hSTickCompare
->scheduled())
201 cpu
->deschedule(hSTickCompare
);
202 cpu
->schedule(hSTickCompare
, curTick() + time
* cpu
->ticks(1));
204 DPRINTF(Timer
, "writing to hsTICK compare register value %#X\n", val
);
207 case MISCREG_HPSTATE
:
208 // T1000 spec says impl. dependent val must always be 1
209 setMiscRegNoEffect(miscReg
, val
| HPSTATE::id
);
210 if (hpstate
& HPSTATE::tlz
&& tl
== 0 && !(hpstate
& HPSTATE::hpriv
))
211 cpu
->postInterrupt(IT_TRAP_LEVEL_ZERO
, 0);
213 cpu
->clearInterrupt(IT_TRAP_LEVEL_ZERO
, 0);
215 case MISCREG_HTSTATE
:
216 setMiscRegNoEffect(miscReg
, val
);
219 case MISCREG_STRAND_STS_REG
:
221 panic("No support for setting spec_en bit\n");
222 setMiscRegNoEffect(miscReg
, bits(val
,0,0));
223 if (!bits(val
,0,0)) {
224 DPRINTF(Quiesce
, "Cpu executed quiescing instruction\n");
225 // Time to go to sleep
228 if (tc
->getKernelStats())
229 tc
->getKernelStats()->quiesce();
235 panic("Invalid write to FS misc register %s\n",
236 getMiscRegName(miscReg
));
241 ISA::readFSReg(int miscReg
, ThreadContext
* tc
)
246 /* Privileged registers. */
247 case MISCREG_QUEUE_CPU_MONDO_HEAD
:
248 case MISCREG_QUEUE_CPU_MONDO_TAIL
:
249 case MISCREG_QUEUE_DEV_MONDO_HEAD
:
250 case MISCREG_QUEUE_DEV_MONDO_TAIL
:
251 case MISCREG_QUEUE_RES_ERROR_HEAD
:
252 case MISCREG_QUEUE_RES_ERROR_TAIL
:
253 case MISCREG_QUEUE_NRES_ERROR_HEAD
:
254 case MISCREG_QUEUE_NRES_ERROR_TAIL
:
255 case MISCREG_SOFTINT
:
256 case MISCREG_TICK_CMPR
:
257 case MISCREG_STICK_CMPR
:
259 case MISCREG_HPSTATE
:
261 case MISCREG_HTSTATE
:
262 case MISCREG_HSTICK_CMPR
:
263 return readMiscRegNoEffect(miscReg
) ;
266 return readMiscRegNoEffect(miscReg
) & ULL(~0x7FFF);
268 // XXX set to match Legion
269 return ULL(0x3e) << 48 |
272 // MaxGL << 16 | XXX For some reason legion doesn't set GL
276 case MISCREG_STRAND_STS_REG
:
279 sys
= tc
->getSystemPtr();
281 temp
= readMiscRegNoEffect(miscReg
) & (STS::active
| STS::speculative
);
282 // Check that the CPU array is fully populated
283 // (by calling getNumCPus())
284 assert(sys
->numContexts() > tc
->contextId());
286 temp
|= tc
->contextId() << STS::shft_id
;
288 for (x
= tc
->contextId() & ~3; x
< sys
->threadContexts
.size(); x
++) {
289 switch (sys
->threadContexts
[x
]->status()) {
290 case ThreadContext::Active
:
291 temp
|= STS::st_run
<< (STS::shft_fsm0
-
292 ((x
& 0x3) * (STS::shft_fsm0
-STS::shft_fsm1
)));
294 case ThreadContext::Suspended
:
295 // should this be idle?
296 temp
|= STS::st_idle
<< (STS::shft_fsm0
-
297 ((x
& 0x3) * (STS::shft_fsm0
-STS::shft_fsm1
)));
299 case ThreadContext::Halted
:
300 temp
|= STS::st_halt
<< (STS::shft_fsm0
-
301 ((x
& 0x3) * (STS::shft_fsm0
-STS::shft_fsm1
)));
304 panic("What state are we in?!\n");
310 panic("Invalid read to FS misc register\n");
315 ISA::processTickCompare(ThreadContext
*tc
)
317 panic("tick compare not implemented\n");
321 ISA::processSTickCompare(ThreadContext
*tc
)
323 BaseCPU
*cpu
= tc
->getCpuPtr();
325 // since our microcode instructions take two cycles we need to check if
326 // we're actually at the correct cycle or we need to wait a little while
329 ticks
= ((int64_t)(stick_cmpr
& mask(63)) - (int64_t)stick
) -
331 assert(ticks
>= 0 && "stick compare missed interrupt cycle");
333 if (ticks
== 0 || tc
->status() == ThreadContext::Suspended
) {
334 DPRINTF(Timer
, "STick compare cycle reached at %#x\n",
335 (stick_cmpr
& mask(63)));
336 if (!(tc
->readMiscRegNoEffect(MISCREG_STICK_CMPR
) & (ULL(1) << 63))) {
337 setMiscReg(MISCREG_SOFTINT
, softint
| (ULL(1) << 16), tc
);
340 cpu
->schedule(sTickCompare
, curTick() + ticks
* cpu
->ticks(1));
345 ISA::processHSTickCompare(ThreadContext
*tc
)
347 BaseCPU
*cpu
= tc
->getCpuPtr();
349 // since our microcode instructions take two cycles we need to check if
350 // we're actually at the correct cycle or we need to wait a little while
353 if ( tc
->status() == ThreadContext::Halted
)
356 ticks
= ((int64_t)(hstick_cmpr
& mask(63)) - (int64_t)stick
) -
358 assert(ticks
>= 0 && "hstick compare missed interrupt cycle");
360 if (ticks
== 0 || tc
->status() == ThreadContext::Suspended
) {
361 DPRINTF(Timer
, "HSTick compare cycle reached at %#x\n",
362 (stick_cmpr
& mask(63)));
363 if (!(tc
->readMiscRegNoEffect(MISCREG_HSTICK_CMPR
) & (ULL(1) << 63))) {
364 setMiscReg(MISCREG_HINTP
, 1, tc
);
366 // Need to do something to cause interrupt to happen here !!! @todo
368 cpu
->schedule(hSTickCompare
, curTick() + ticks
* cpu
->ticks(1));