src/arch/sparc/ua2005.cc

   1 /*
   2  * Copyright (c) 2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #include "arch/sparc/kernel_stats.hh"
  30 #include "arch/sparc/miscregfile.hh"
  31 #include "base/bitfield.hh"
  32 #include "base/trace.hh"
  33 #include "cpu/base.hh"
  34 #include "cpu/thread_context.hh"
  35 #include "sim/system.hh"
  36
  37 using namespace SparcISA;
  38
  39
  40 void
  41 MiscRegFile::checkSoftInt(ThreadContext *tc)
  42 {
  43     // If PIL < 14, copy over the tm and sm bits
  44     if (pil < 14 && softint & 0x10000)
  45         tc->getCpuPtr()->post_interrupt(IT_SOFT_INT,16);
  46     else
  47         tc->getCpuPtr()->clear_interrupt(IT_SOFT_INT,16);
  48     if (pil < 14 && softint & 0x1)
  49         tc->getCpuPtr()->post_interrupt(IT_SOFT_INT,0);
  50     else
  51         tc->getCpuPtr()->clear_interrupt(IT_SOFT_INT,0);
  52
  53     // Copy over any of the other bits that are set
  54     for (int bit = 15; bit > 0; --bit) {
  55         if (1 << bit & softint && bit > pil)
  56             tc->getCpuPtr()->post_interrupt(IT_SOFT_INT,bit);
  57         else
  58             tc->getCpuPtr()->clear_interrupt(IT_SOFT_INT,bit);
  59     }
  60 }
  61
  62
  63 void
  64 MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
  65 {
  66     int64_t time;
  67     switch (miscReg) {
  68         /* Full system only ASRs */
  69       case MISCREG_SOFTINT:
  70         setRegNoEffect(miscReg, val);;
  71         checkSoftInt(tc);
  72         break;
  73       case MISCREG_SOFTINT_CLR:
  74         return setReg(MISCREG_SOFTINT, ~val & softint, tc);
  75       case MISCREG_SOFTINT_SET:
  76         return setReg(MISCREG_SOFTINT, val | softint, tc);
  77
  78       case MISCREG_TICK_CMPR:
  79         if (tickCompare == NULL)
  80             tickCompare = new TickCompareEvent(this, tc);
  81         setRegNoEffect(miscReg, val);
  82         if ((tick_cmpr & ~mask(63)) && tickCompare->scheduled())
  83             tickCompare->deschedule();
  84         time = (tick_cmpr & mask(63)) - (tick & mask(63));
  85         if (!(tick_cmpr & ~mask(63)) && time > 0) {
  86             if (tickCompare->scheduled())
  87                 tickCompare->deschedule();
  88             tickCompare->schedule(time * tc->getCpuPtr()->cycles(1));
  89         }
  90         panic("writing to TICK compare register %#X\n", val);
  91         break;
  92
  93       case MISCREG_STICK_CMPR:
  94         if (sTickCompare == NULL)
  95             sTickCompare = new STickCompareEvent(this, tc);
  96         setRegNoEffect(miscReg, val);
  97         if ((stick_cmpr & ~mask(63)) && sTickCompare->scheduled())
  98             sTickCompare->deschedule();
  99         time = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) -
 100             tc->getCpuPtr()->instCount();
 101         if (!(stick_cmpr & ~mask(63)) && time > 0) {
 102             if (sTickCompare->scheduled())
 103                 sTickCompare->deschedule();
 104             sTickCompare->schedule(time * tc->getCpuPtr()->cycles(1) + curTick);
 105         }
 106         DPRINTF(Timer, "writing to sTICK compare register value %#X\n", val);
 107         break;
 108
 109       case MISCREG_PSTATE:
 110         setRegNoEffect(miscReg, val);
 111
 112       case MISCREG_PIL:
 113         setRegNoEffect(miscReg, val);
 114         checkSoftInt(tc);
 115         break;
 116
 117       case MISCREG_HVER:
 118         panic("Shouldn't be writing HVER\n");
 119
 120       case MISCREG_HINTP:
 121         setRegNoEffect(miscReg, val);
 122         if (hintp)
 123             tc->getCpuPtr()->post_interrupt(IT_HINTP,0);
 124         else
 125             tc->getCpuPtr()->clear_interrupt(IT_HINTP,0);
 126         break;
 127
 128       case MISCREG_HTBA:
 129         // clear lower 7 bits on writes.
 130         setRegNoEffect(miscReg, val & ULL(~0x7FFF));
 131         break;
 132
 133       case MISCREG_QUEUE_CPU_MONDO_HEAD:
 134       case MISCREG_QUEUE_CPU_MONDO_TAIL:
 135         setRegNoEffect(miscReg, val);
 136         if (cpu_mondo_head != cpu_mondo_tail)
 137             tc->getCpuPtr()->post_interrupt(IT_CPU_MONDO,0);
 138         else
 139             tc->getCpuPtr()->clear_interrupt(IT_CPU_MONDO,0);
 140         break;
 141       case MISCREG_QUEUE_DEV_MONDO_HEAD:
 142       case MISCREG_QUEUE_DEV_MONDO_TAIL:
 143         setRegNoEffect(miscReg, val);
 144         if (dev_mondo_head != dev_mondo_tail)
 145             tc->getCpuPtr()->post_interrupt(IT_DEV_MONDO,0);
 146         else
 147             tc->getCpuPtr()->clear_interrupt(IT_DEV_MONDO,0);
 148         break;
 149       case MISCREG_QUEUE_RES_ERROR_HEAD:
 150       case MISCREG_QUEUE_RES_ERROR_TAIL:
 151         setRegNoEffect(miscReg, val);
 152         if (res_error_head != res_error_tail)
 153             tc->getCpuPtr()->post_interrupt(IT_RES_ERROR,0);
 154         else
 155             tc->getCpuPtr()->clear_interrupt(IT_RES_ERROR,0);
 156         break;
 157       case MISCREG_QUEUE_NRES_ERROR_HEAD:
 158       case MISCREG_QUEUE_NRES_ERROR_TAIL:
 159         setRegNoEffect(miscReg, val);
 160         // This one doesn't have an interrupt to report to the guest OS
 161         break;
 162
 163       case MISCREG_HSTICK_CMPR:
 164         if (hSTickCompare == NULL)
 165             hSTickCompare = new HSTickCompareEvent(this, tc);
 166         setRegNoEffect(miscReg, val);
 167         if ((hstick_cmpr & ~mask(63)) && hSTickCompare->scheduled())
 168             hSTickCompare->deschedule();
 169         time = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) -
 170             tc->getCpuPtr()->instCount();
 171         if (!(hstick_cmpr & ~mask(63)) && time > 0) {
 172             if (hSTickCompare->scheduled())
 173                 hSTickCompare->deschedule();
 174             hSTickCompare->schedule(curTick + time * tc->getCpuPtr()->cycles(1));
 175         }
 176         DPRINTF(Timer, "writing to hsTICK compare register value %#X\n", val);
 177         break;
 178
 179       case MISCREG_HPSTATE:
 180         // T1000 spec says impl. dependent val must always be 1
 181         setRegNoEffect(miscReg, val | HPSTATE::id);
 182 #if FULL_SYSTEM
 183         if (hpstate & HPSTATE::tlz && tl == 0 && !(hpstate & HPSTATE::hpriv))
 184             tc->getCpuPtr()->post_interrupt(IT_TRAP_LEVEL_ZERO,0);
 185         else
 186             tc->getCpuPtr()->clear_interrupt(IT_TRAP_LEVEL_ZERO,0);
 187 #endif
 188         break;
 189       case MISCREG_HTSTATE:
 190         setRegNoEffect(miscReg, val);
 191         break;
 192
 193       case MISCREG_STRAND_STS_REG:
 194         if (bits(val,2,2))
 195             panic("No support for setting spec_en bit\n");
 196         setRegNoEffect(miscReg, bits(val,0,0));
 197         if (!bits(val,0,0)) {
 198             // Time to go to sleep
 199             tc->suspend();
 200             if (tc->getKernelStats())
 201                 tc->getKernelStats()->quiesce();
 202             }
 203         break;
 204
 205       default:
 206         panic("Invalid write to FS misc register %s\n", getMiscRegName(miscReg));
 207     }
 208 }
 209
 210 MiscReg
 211 MiscRegFile::readFSReg(int miscReg, ThreadContext * tc)
 212 {
 213     uint64_t temp;
 214
 215     switch (miscReg) {
 216         /* Privileged registers. */
 217       case MISCREG_QUEUE_CPU_MONDO_HEAD:
 218       case MISCREG_QUEUE_CPU_MONDO_TAIL:
 219       case MISCREG_QUEUE_DEV_MONDO_HEAD:
 220       case MISCREG_QUEUE_DEV_MONDO_TAIL:
 221       case MISCREG_QUEUE_RES_ERROR_HEAD:
 222       case MISCREG_QUEUE_RES_ERROR_TAIL:
 223       case MISCREG_QUEUE_NRES_ERROR_HEAD:
 224       case MISCREG_QUEUE_NRES_ERROR_TAIL:
 225       case MISCREG_SOFTINT:
 226       case MISCREG_TICK_CMPR:
 227       case MISCREG_STICK_CMPR:
 228       case MISCREG_PIL:
 229       case MISCREG_HPSTATE:
 230       case MISCREG_HINTP:
 231       case MISCREG_HTSTATE:
 232       case MISCREG_HSTICK_CMPR:
 233         return readRegNoEffect(miscReg) ;
 234
 235       case MISCREG_HTBA:
 236         return readRegNoEffect(miscReg) & ULL(~0x7FFF);
 237       case MISCREG_HVER:
 238         // XXX set to match Legion
 239         return ULL(0x3e) << 48 |
 240                ULL(0x23) << 32 |
 241                ULL(0x20) << 24 |
 242                    //MaxGL << 16 | XXX For some reason legion doesn't set GL
 243                    MaxTL << 8  |
 244            (NWindows -1) << 0;
 245
 246       case MISCREG_STRAND_STS_REG:
 247         System *sys;
 248         int x;
 249         sys = tc->getSystemPtr();
 250
 251         temp = readRegNoEffect(miscReg) & (STS::active | STS::speculative);
 252         // Check that the CPU array is fully populated (by calling getNumCPus())
 253         assert(sys->getNumCPUs() > tc->readCpuId());
 254
 255         temp |= tc->readCpuId()  << STS::shft_id;
 256
 257         for (x = tc->readCpuId() & ~3; x < sys->threadContexts.size(); x++) {
 258             switch (sys->threadContexts[x]->status()) {
 259               case ThreadContext::Active:
 260                 temp |= STS::st_run << (STS::shft_fsm0 -
 261                         ((x & 0x3) * (STS::shft_fsm0-STS::shft_fsm1)));
 262                 break;
 263               case ThreadContext::Suspended:
 264                 // should this be idle?
 265                 temp |= STS::st_idle << (STS::shft_fsm0 -
 266                         ((x & 0x3) * (STS::shft_fsm0-STS::shft_fsm1)));
 267                 break;
 268               case ThreadContext::Halted:
 269                 temp |= STS::st_halt << (STS::shft_fsm0 -
 270                         ((x & 0x3) * (STS::shft_fsm0-STS::shft_fsm1)));
 271                 break;
 272               default:
 273                 panic("What state are we in?!\n");
 274             } // switch
 275         } // for
 276
 277         return temp;
 278       default:
 279         panic("Invalid read to FS misc register\n");
 280     }
 281 }
 282 /*
 283   In Niagra STICK==TICK so this isn't needed
 284   case MISCREG_STICK:
 285   SparcSystem *sys;
 286   sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
 287   assert(sys != NULL);
 288   return curTick/Clock::Int::ns - sys->sysTick | (stick & ~(mask(63)));
 289 */
 290
 291
 292
 293 void
 294 MiscRegFile::processTickCompare(ThreadContext *tc)
 295 {
 296     panic("tick compare not implemented\n");
 297 }
 298
 299 void
 300 MiscRegFile::processSTickCompare(ThreadContext *tc)
 301 {
 302     // since our microcode instructions take two cycles we need to check if
 303     // we're actually at the correct cycle or we need to wait a little while
 304     // more
 305     int ticks;
 306     ticks = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) -
 307         tc->getCpuPtr()->instCount();
 308     assert(ticks >= 0 && "stick compare missed interrupt cycle");
 309
 310     if (ticks == 0) {
 311         DPRINTF(Timer, "STick compare cycle reached at %#x\n",
 312                 (stick_cmpr & mask(63)));
 313         if (!(tc->readMiscRegNoEffect(MISCREG_STICK_CMPR) & (ULL(1) << 63))) {
 314             setReg(MISCREG_SOFTINT, softint | (ULL(1) << 16), tc);
 315         }
 316     } else
 317         sTickCompare->schedule(ticks * tc->getCpuPtr()->cycles(1) + curTick);
 318 }
 319
 320 void
 321 MiscRegFile::processHSTickCompare(ThreadContext *tc)
 322 {
 323     // since our microcode instructions take two cycles we need to check if
 324     // we're actually at the correct cycle or we need to wait a little while
 325     // more
 326     int ticks;
 327     ticks = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) -
 328         tc->getCpuPtr()->instCount();
 329     assert(ticks >= 0 && "hstick compare missed interrupt cycle");
 330
 331     if (ticks == 0) {
 332         DPRINTF(Timer, "HSTick compare cycle reached at %#x\n",
 333                 (stick_cmpr & mask(63)));
 334         if (!(tc->readMiscRegNoEffect(MISCREG_HSTICK_CMPR) & (ULL(1) << 63))) {
 335             setReg(MISCREG_HINTP, 1, tc);
 336         }
 337         // Need to do something to cause interrupt to happen here !!! @todo
 338     } else
 339         hSTickCompare->schedule(ticks * tc->getCpuPtr()->cycles(1) + curTick);
 340 }
 341