2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
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14 * this software without specific prior written permission.
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32 #include "arch/sparc/faults.hh"
33 #include "arch/sparc/utility.hh"
35 #include "arch/sparc/vtophys.hh"
36 #include "mem/fs_translating_port_proxy.hh"
42 // The caller uses %o0-%05 for the first 6 arguments even if their floating
43 // point. Double precision floating point values take two registers/args.
44 // Quads, structs, and unions are passed as pointers. All arguments beyond
45 // the sixth are passed on the stack past the 16 word window save area,
46 // space for the struct/union return pointer, and space reserved for the
47 // first 6 arguments which the caller may use but doesn't have to.
49 getArgument(ThreadContext
*tc
, int &number
, uint16_t size
, bool fp
)
52 const int NumArgumentRegs
= 6;
53 if (number
< NumArgumentRegs
) {
54 return tc
->readIntReg(8 + number
);
56 Addr sp
= tc
->readIntReg(StackPointerReg
);
57 FSTranslatingPortProxy
* vp
= tc
->getVirtProxy();
58 uint64_t arg
= vp
->read
<uint64_t>(sp
+ 92 +
59 (number
-NumArgumentRegs
) * sizeof(uint64_t));
63 panic("getArgument() only implemented for FULL_SYSTEM\n");
69 copyMiscRegs(ThreadContext
*src
, ThreadContext
*dest
)
72 uint8_t tl
= src
->readMiscRegNoEffect(MISCREG_TL
);
74 // Read all the trap level dependent registers and save them off
75 for (int i
= 1; i
<= MaxTL
; i
++) {
76 src
->setMiscRegNoEffect(MISCREG_TL
, i
);
77 dest
->setMiscRegNoEffect(MISCREG_TL
, i
);
79 dest
->setMiscRegNoEffect(MISCREG_TT
,
80 src
->readMiscRegNoEffect(MISCREG_TT
));
81 dest
->setMiscRegNoEffect(MISCREG_TPC
,
82 src
->readMiscRegNoEffect(MISCREG_TPC
));
83 dest
->setMiscRegNoEffect(MISCREG_TNPC
,
84 src
->readMiscRegNoEffect(MISCREG_TNPC
));
85 dest
->setMiscRegNoEffect(MISCREG_TSTATE
,
86 src
->readMiscRegNoEffect(MISCREG_TSTATE
));
89 // Save off the traplevel
90 dest
->setMiscRegNoEffect(MISCREG_TL
, tl
);
91 src
->setMiscRegNoEffect(MISCREG_TL
, tl
);
95 // dest->setMiscRegNoEffect(MISCREG_Y,
96 // src->readMiscRegNoEffect(MISCREG_Y));
97 // dest->setMiscRegNoEffect(MISCREG_CCR,
98 // src->readMiscRegNoEffect(MISCREG_CCR));
99 dest
->setMiscRegNoEffect(MISCREG_ASI
,
100 src
->readMiscRegNoEffect(MISCREG_ASI
));
101 dest
->setMiscRegNoEffect(MISCREG_TICK
,
102 src
->readMiscRegNoEffect(MISCREG_TICK
));
103 dest
->setMiscRegNoEffect(MISCREG_FPRS
,
104 src
->readMiscRegNoEffect(MISCREG_FPRS
));
105 dest
->setMiscRegNoEffect(MISCREG_SOFTINT
,
106 src
->readMiscRegNoEffect(MISCREG_SOFTINT
));
107 dest
->setMiscRegNoEffect(MISCREG_TICK_CMPR
,
108 src
->readMiscRegNoEffect(MISCREG_TICK_CMPR
));
109 dest
->setMiscRegNoEffect(MISCREG_STICK
,
110 src
->readMiscRegNoEffect(MISCREG_STICK
));
111 dest
->setMiscRegNoEffect(MISCREG_STICK_CMPR
,
112 src
->readMiscRegNoEffect(MISCREG_STICK_CMPR
));
115 dest
->setMiscRegNoEffect(MISCREG_TICK
,
116 src
->readMiscRegNoEffect(MISCREG_TICK
));
117 dest
->setMiscRegNoEffect(MISCREG_TBA
,
118 src
->readMiscRegNoEffect(MISCREG_TBA
));
119 dest
->setMiscRegNoEffect(MISCREG_PSTATE
,
120 src
->readMiscRegNoEffect(MISCREG_PSTATE
));
121 dest
->setMiscRegNoEffect(MISCREG_PIL
,
122 src
->readMiscRegNoEffect(MISCREG_PIL
));
123 dest
->setMiscReg(MISCREG_CWP
,
124 src
->readMiscRegNoEffect(MISCREG_CWP
));
125 // dest->setMiscRegNoEffect(MISCREG_CANSAVE,
126 // src->readMiscRegNoEffect(MISCREG_CANSAVE));
127 // dest->setMiscRegNoEffect(MISCREG_CANRESTORE,
128 // src->readMiscRegNoEffect(MISCREG_CANRESTORE));
129 // dest->setMiscRegNoEffect(MISCREG_OTHERWIN,
130 // src->readMiscRegNoEffect(MISCREG_OTHERWIN));
131 // dest->setMiscRegNoEffect(MISCREG_CLEANWIN,
132 // src->readMiscRegNoEffect(MISCREG_CLEANWIN));
133 // dest->setMiscRegNoEffect(MISCREG_WSTATE,
134 // src->readMiscRegNoEffect(MISCREG_WSTATE));
135 dest
->setMiscReg(MISCREG_GL
, src
->readMiscRegNoEffect(MISCREG_GL
));
137 // Hyperprivilged registers
138 dest
->setMiscRegNoEffect(MISCREG_HPSTATE
,
139 src
->readMiscRegNoEffect(MISCREG_HPSTATE
));
140 dest
->setMiscRegNoEffect(MISCREG_HINTP
,
141 src
->readMiscRegNoEffect(MISCREG_HINTP
));
142 dest
->setMiscRegNoEffect(MISCREG_HTBA
,
143 src
->readMiscRegNoEffect(MISCREG_HTBA
));
144 dest
->setMiscRegNoEffect(MISCREG_STRAND_STS_REG
,
145 src
->readMiscRegNoEffect(MISCREG_STRAND_STS_REG
));
146 dest
->setMiscRegNoEffect(MISCREG_HSTICK_CMPR
,
147 src
->readMiscRegNoEffect(MISCREG_HSTICK_CMPR
));
150 dest
->setMiscRegNoEffect(MISCREG_FSR
,
151 src
->readMiscRegNoEffect(MISCREG_FSR
));
153 // Strand Status Register
154 dest
->setMiscRegNoEffect(MISCREG_STRAND_STS_REG
,
155 src
->readMiscRegNoEffect(MISCREG_STRAND_STS_REG
));
158 dest
->setMiscRegNoEffect(MISCREG_MMU_P_CONTEXT
,
159 src
->readMiscRegNoEffect(MISCREG_MMU_P_CONTEXT
));
160 dest
->setMiscRegNoEffect(MISCREG_MMU_S_CONTEXT
,
161 src
->readMiscRegNoEffect(MISCREG_MMU_S_CONTEXT
));
162 dest
->setMiscRegNoEffect(MISCREG_MMU_PART_ID
,
163 src
->readMiscRegNoEffect(MISCREG_MMU_PART_ID
));
164 dest
->setMiscRegNoEffect(MISCREG_MMU_LSU_CTRL
,
165 src
->readMiscRegNoEffect(MISCREG_MMU_LSU_CTRL
));
167 // Scratchpad Registers
168 dest
->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R0
,
169 src
->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R0
));
170 dest
->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R1
,
171 src
->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R1
));
172 dest
->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R2
,
173 src
->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R2
));
174 dest
->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R3
,
175 src
->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R3
));
176 dest
->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R4
,
177 src
->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R4
));
178 dest
->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R5
,
179 src
->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R5
));
180 dest
->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R6
,
181 src
->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R6
));
182 dest
->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R7
,
183 src
->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R7
));
186 dest
->setMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_HEAD
,
187 src
->readMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_HEAD
));
188 dest
->setMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_TAIL
,
189 src
->readMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_TAIL
));
190 dest
->setMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_HEAD
,
191 src
->readMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_HEAD
));
192 dest
->setMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_TAIL
,
193 src
->readMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_TAIL
));
194 dest
->setMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_HEAD
,
195 src
->readMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_HEAD
));
196 dest
->setMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_TAIL
,
197 src
->readMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_TAIL
));
198 dest
->setMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_HEAD
,
199 src
->readMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_HEAD
));
200 dest
->setMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_TAIL
,
201 src
->readMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_TAIL
));
205 copyRegs(ThreadContext
*src
, ThreadContext
*dest
)
207 // First loop through the integer registers.
208 int old_gl
= src
->readMiscRegNoEffect(MISCREG_GL
);
209 int old_cwp
= src
->readMiscRegNoEffect(MISCREG_CWP
);
211 for (int x
= 0; x
< MaxGL
; ++x
) {
212 src
->setMiscReg(MISCREG_GL
, x
);
213 dest
->setMiscReg(MISCREG_GL
, x
);
214 // Skip %g0 which is always zero.
215 for (int y
= 1; y
< 8; y
++)
216 dest
->setIntReg(y
, src
->readIntReg(y
));
218 // Locals and ins. Outs are all also ins.
219 for (int x
= 0; x
< NWindows
; ++x
) {
220 src
->setMiscReg(MISCREG_CWP
, x
);
221 dest
->setMiscReg(MISCREG_CWP
, x
);
222 for (int y
= 16; y
< 32; y
++)
223 dest
->setIntReg(y
, src
->readIntReg(y
));
225 // Microcode reg and pseudo int regs (misc regs in the integer regfile).
226 for (int y
= NumIntArchRegs
; y
< NumIntArchRegs
+ NumMicroIntRegs
; ++y
)
227 dest
->setIntReg(y
, src
->readIntReg(y
));
229 // Restore src's GL, CWP
230 src
->setMiscReg(MISCREG_GL
, old_gl
);
231 src
->setMiscReg(MISCREG_CWP
, old_cwp
);
234 // Then loop through the floating point registers.
235 for (int i
= 0; i
< SparcISA::NumFloatArchRegs
; ++i
) {
236 dest
->setFloatRegBits(i
, src
->readFloatRegBits(i
));
239 // Copy misc. registers
240 copyMiscRegs(src
, dest
);
242 // Lastly copy PC/NPC
243 dest
->pcState(src
->pcState());
247 skipFunction(ThreadContext
*tc
)
249 TheISA::PCState newPC
= tc
->pcState();
250 newPC
.set(tc
->readIntReg(ReturnAddressReg
));
256 initCPU(ThreadContext
*tc
, int cpuId
)
258 static Fault por
= new PowerOnReset();
263 } // namespace SPARC_ISA