2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
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32 #include "arch/sparc/utility.hh"
34 #include "arch/sparc/vtophys.hh"
35 #include "mem/vport.hh"
41 //The caller uses %o0-%05 for the first 6 arguments even if their floating
42 //point. Double precision floating point values take two registers/args.
43 //Quads, structs, and unions are passed as pointers. All arguments beyond
44 //the sixth are passed on the stack past the 16 word window save area,
45 //space for the struct/union return pointer, and space reserved for the
46 //first 6 arguments which the caller may use but doesn't have to.
47 uint64_t getArgument(ThreadContext
*tc
, int number
, bool fp
) {
49 const int NumArgumentRegs
= 6;
50 if (number
< NumArgumentRegs
) {
51 return tc
->readIntReg(8 + number
);
53 Addr sp
= tc
->readIntReg(StackPointerReg
);
54 VirtualPort
*vp
= tc
->getVirtPort();
55 uint64_t arg
= vp
->read
<uint64_t>(sp
+ 92 +
56 (number
-NumArgumentRegs
) * sizeof(uint64_t));
60 panic("getArgument() only implemented for FULL_SYSTEM\n");
66 copyMiscRegs(ThreadContext
*src
, ThreadContext
*dest
)
69 uint8_t tl
= src
->readMiscRegNoEffect(MISCREG_TL
);
71 // Read all the trap level dependent registers and save them off
72 for(int i
= 1; i
<= MaxTL
; i
++)
74 src
->setMiscRegNoEffect(MISCREG_TL
, i
);
75 dest
->setMiscRegNoEffect(MISCREG_TL
, i
);
77 dest
->setMiscRegNoEffect(MISCREG_TT
, src
->readMiscRegNoEffect(MISCREG_TT
));
78 dest
->setMiscRegNoEffect(MISCREG_TPC
, src
->readMiscRegNoEffect(MISCREG_TPC
));
79 dest
->setMiscRegNoEffect(MISCREG_TNPC
, src
->readMiscRegNoEffect(MISCREG_TNPC
));
80 dest
->setMiscRegNoEffect(MISCREG_TSTATE
, src
->readMiscRegNoEffect(MISCREG_TSTATE
));
83 // Save off the traplevel
84 dest
->setMiscRegNoEffect(MISCREG_TL
, tl
);
85 src
->setMiscRegNoEffect(MISCREG_TL
, tl
);
89 // dest->setMiscRegNoEffect(MISCREG_Y, src->readMiscRegNoEffect(MISCREG_Y));
90 // dest->setMiscRegNoEffect(MISCREG_CCR, src->readMiscRegNoEffect(MISCREG_CCR));
91 dest
->setMiscRegNoEffect(MISCREG_ASI
, src
->readMiscRegNoEffect(MISCREG_ASI
));
92 dest
->setMiscRegNoEffect(MISCREG_TICK
, src
->readMiscRegNoEffect(MISCREG_TICK
));
93 dest
->setMiscRegNoEffect(MISCREG_FPRS
, src
->readMiscRegNoEffect(MISCREG_FPRS
));
94 dest
->setMiscRegNoEffect(MISCREG_SOFTINT
, src
->readMiscRegNoEffect(MISCREG_SOFTINT
));
95 dest
->setMiscRegNoEffect(MISCREG_TICK_CMPR
, src
->readMiscRegNoEffect(MISCREG_TICK_CMPR
));
96 dest
->setMiscRegNoEffect(MISCREG_STICK
, src
->readMiscRegNoEffect(MISCREG_STICK
));
97 dest
->setMiscRegNoEffect(MISCREG_STICK_CMPR
, src
->readMiscRegNoEffect(MISCREG_STICK_CMPR
));
100 dest
->setMiscRegNoEffect(MISCREG_TICK
, src
->readMiscRegNoEffect(MISCREG_TICK
));
101 dest
->setMiscRegNoEffect(MISCREG_TBA
, src
->readMiscRegNoEffect(MISCREG_TBA
));
102 dest
->setMiscRegNoEffect(MISCREG_PSTATE
, src
->readMiscRegNoEffect(MISCREG_PSTATE
));
103 dest
->setMiscRegNoEffect(MISCREG_PIL
, src
->readMiscRegNoEffect(MISCREG_PIL
));
104 dest
->setMiscReg(MISCREG_CWP
, src
->readMiscRegNoEffect(MISCREG_CWP
));
105 // dest->setMiscRegNoEffect(MISCREG_CANSAVE, src->readMiscRegNoEffect(MISCREG_CANSAVE));
106 // dest->setMiscRegNoEffect(MISCREG_CANRESTORE, src->readMiscRegNoEffect(MISCREG_CANRESTORE));
107 // dest->setMiscRegNoEffect(MISCREG_OTHERWIN, src->readMiscRegNoEffect(MISCREG_OTHERWIN));
108 // dest->setMiscRegNoEffect(MISCREG_CLEANWIN, src->readMiscRegNoEffect(MISCREG_CLEANWIN));
109 // dest->setMiscRegNoEffect(MISCREG_WSTATE, src->readMiscRegNoEffect(MISCREG_WSTATE));
110 dest
->setMiscReg(MISCREG_GL
, src
->readMiscRegNoEffect(MISCREG_GL
));
112 // Hyperprivilged registers
113 dest
->setMiscRegNoEffect(MISCREG_HPSTATE
, src
->readMiscRegNoEffect(MISCREG_HPSTATE
));
114 dest
->setMiscRegNoEffect(MISCREG_HINTP
, src
->readMiscRegNoEffect(MISCREG_HINTP
));
115 dest
->setMiscRegNoEffect(MISCREG_HTBA
, src
->readMiscRegNoEffect(MISCREG_HTBA
));
116 dest
->setMiscRegNoEffect(MISCREG_STRAND_STS_REG
,
117 src
->readMiscRegNoEffect(MISCREG_STRAND_STS_REG
));
118 dest
->setMiscRegNoEffect(MISCREG_HSTICK_CMPR
,
119 src
->readMiscRegNoEffect(MISCREG_HSTICK_CMPR
));
122 dest
->setMiscRegNoEffect(MISCREG_FSR
, src
->readMiscRegNoEffect(MISCREG_FSR
));
124 //Strand Status Register
125 dest
->setMiscRegNoEffect(MISCREG_STRAND_STS_REG
,
126 src
->readMiscRegNoEffect(MISCREG_STRAND_STS_REG
));
129 dest
->setMiscRegNoEffect(MISCREG_MMU_P_CONTEXT
,
130 src
->readMiscRegNoEffect(MISCREG_MMU_P_CONTEXT
));
131 dest
->setMiscRegNoEffect(MISCREG_MMU_S_CONTEXT
,
132 src
->readMiscRegNoEffect(MISCREG_MMU_S_CONTEXT
));
133 dest
->setMiscRegNoEffect(MISCREG_MMU_PART_ID
,
134 src
->readMiscRegNoEffect(MISCREG_MMU_PART_ID
));
135 dest
->setMiscRegNoEffect(MISCREG_MMU_LSU_CTRL
,
136 src
->readMiscRegNoEffect(MISCREG_MMU_LSU_CTRL
));
138 // Scratchpad Registers
139 dest
->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R0
,
140 src
->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R0
));
141 dest
->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R1
,
142 src
->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R1
));
143 dest
->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R2
,
144 src
->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R2
));
145 dest
->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R3
,
146 src
->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R3
));
147 dest
->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R4
,
148 src
->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R4
));
149 dest
->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R5
,
150 src
->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R5
));
151 dest
->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R6
,
152 src
->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R6
));
153 dest
->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R7
,
154 src
->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R7
));
157 dest
->setMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_HEAD
,
158 src
->readMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_HEAD
));
159 dest
->setMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_TAIL
,
160 src
->readMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_TAIL
));
161 dest
->setMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_HEAD
,
162 src
->readMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_HEAD
));
163 dest
->setMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_TAIL
,
164 src
->readMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_TAIL
));
165 dest
->setMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_HEAD
,
166 src
->readMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_HEAD
));
167 dest
->setMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_TAIL
,
168 src
->readMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_TAIL
));
169 dest
->setMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_HEAD
,
170 src
->readMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_HEAD
));
171 dest
->setMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_TAIL
,
172 src
->readMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_TAIL
));
176 copyRegs(ThreadContext
*src
, ThreadContext
*dest
)
178 //First loop through the integer registers.
179 int old_gl
= src
->readMiscRegNoEffect(MISCREG_GL
);
180 int old_cwp
= src
->readMiscRegNoEffect(MISCREG_CWP
);
182 for (int x
= 0; x
< MaxGL
; ++x
) {
183 src
->setMiscReg(MISCREG_GL
, x
);
184 dest
->setMiscReg(MISCREG_GL
, x
);
185 // Skip %g0 which is always zero.
186 for (int y
= 1; y
< 8; y
++)
187 dest
->setIntReg(y
, src
->readIntReg(y
));
189 //Locals and ins. Outs are all also ins.
190 for (int x
= 0; x
< NWindows
; ++x
) {
191 src
->setMiscReg(MISCREG_CWP
, x
);
192 dest
->setMiscReg(MISCREG_CWP
, x
);
193 for (int y
= 16; y
< 32; y
++)
194 dest
->setIntReg(y
, src
->readIntReg(y
));
196 //Microcode reg and pseudo int regs (misc regs in the integer regfile).
197 for (int y
= NumIntArchRegs
; y
< NumIntArchRegs
+ NumMicroIntRegs
; ++y
)
198 dest
->setIntReg(y
, src
->readIntReg(y
));
200 //Restore src's GL, CWP
201 src
->setMiscReg(MISCREG_GL
, old_gl
);
202 src
->setMiscReg(MISCREG_CWP
, old_cwp
);
205 // Then loop through the floating point registers.
206 for (int i
= 0; i
< SparcISA::NumFloatArchRegs
; ++i
) {
207 dest
->setFloatRegBits(i
, src
->readFloatRegBits(i
));
210 // Copy misc. registers
211 copyMiscRegs(src
, dest
);
214 // Lastly copy PC/NPC
215 dest
->setPC(src
->readPC());
216 dest
->setNextPC(src
->readNextPC());
217 dest
->setNextNPC(src
->readNextNPC());
219 } //namespace SPARC_ISA