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31 #ifndef __ARCH_SPARC_UTILITY_HH__
32 #define __ARCH_SPARC_UTILITY_HH__
34 #include "arch/sparc/isa_traits.hh"
35 #include "base/misc.hh"
36 #include "base/bitfield.hh"
37 #include "cpu/thread_context.hh"
42 makeExtMI(MachInst inst, ThreadContext * xc) {
43 ExtMachInst emi = (unsigned MachInst) inst;
44 //The I bit, bit 13, is used to figure out where the ASI
45 //should come from. Use that in the ExtMachInst. This is
46 //slightly redundant, but it removes the need to put a condition
47 //into all the execute functions
49 emi |= (static_cast<ExtMachInst>(xc->readMiscReg(MISCREG_ASI))
50 << (sizeof(MachInst) * 8));
52 emi |= (static_cast<ExtMachInst>(bits(inst, 12, 5))
53 << (sizeof(MachInst) * 8));
57 inline bool isCallerSaveIntegerRegister(unsigned int reg) {
58 panic("register classification not implemented");
62 inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
63 panic("register classification not implemented");
67 inline bool isCallerSaveFloatRegister(unsigned int reg) {
68 panic("register classification not implemented");
72 inline bool isCalleeSaveFloatRegister(unsigned int reg) {
73 panic("register classification not implemented");
77 // Instruction address compression hooks
78 inline Addr realPCToFetchPC(const Addr &addr)
83 inline Addr fetchPCToRealPC(const Addr &addr)
88 // the size of "fetched" instructions (not necessarily the size
89 // of real instructions for PISA)
90 inline size_t fetchInstSize()
92 return sizeof(MachInst);
96 * Function to insure ISA semantics about 0 registers.
97 * @param tc The thread context.
100 void zeroRegisters(TC *tc);
102 } // namespace SparcISA