2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
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31 #ifndef __ARCH_SPARC_UTILITY_HH__
32 #define __ARCH_SPARC_UTILITY_HH__
34 #include "arch/sparc/isa_traits.hh"
35 #include "arch/sparc/registers.hh"
36 #include "arch/sparc/tlb.hh"
37 #include "base/bitfield.hh"
38 #include "base/misc.hh"
39 #include "cpu/static_inst.hh"
40 #include "cpu/thread_context.hh"
41 #include "sim/fault_fwd.hh"
47 buildRetPC(const PCState &curPC, const PCState &callPC)
55 uint64_t getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp);
58 inUserMode(ThreadContext *tc)
60 return !((tc->readMiscRegNoEffect(MISCREG_PSTATE) & (1 << 2)) ||
61 (tc->readMiscRegNoEffect(MISCREG_HPSTATE) & (1 << 2)));
65 * Function to insure ISA semantics about 0 registers.
66 * @param tc The thread context.
69 void zeroRegisters(TC *tc);
71 void initCPU(ThreadContext *tc, int cpuId);
74 startupCPU(ThreadContext *tc, int cpuId)
77 // Other CPUs will get activated by IPIs
85 void copyRegs(ThreadContext *src, ThreadContext *dest);
87 void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
89 void skipFunction(ThreadContext *tc);
92 advancePC(PCState &pc, const StaticInstPtr inst)
98 getExecutingAsid(ThreadContext *tc)
100 return tc->readMiscRegNoEffect(MISCREG_MMU_P_CONTEXT);
103 } // namespace SparcISA