2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
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31 #ifndef __ARCH_SPARC_UTILITY_HH__
32 #define __ARCH_SPARC_UTILITY_HH__
34 #include "arch/sparc/faults.hh"
35 #include "arch/sparc/isa_traits.hh"
36 #include "arch/sparc/tlb.hh"
37 #include "base/misc.hh"
38 #include "base/bitfield.hh"
39 #include "cpu/thread_context.hh"
45 uint64_t getArgument(ThreadContext *tc, int number, bool fp);
48 inUserMode(ThreadContext *tc)
50 return !(tc->readMiscRegNoEffect(MISCREG_PSTATE & (1 << 2)) ||
51 tc->readMiscRegNoEffect(MISCREG_HPSTATE & (1 << 2)));
54 inline bool isCallerSaveIntegerRegister(unsigned int reg) {
55 panic("register classification not implemented");
59 inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
60 panic("register classification not implemented");
64 inline bool isCallerSaveFloatRegister(unsigned int reg) {
65 panic("register classification not implemented");
69 inline bool isCalleeSaveFloatRegister(unsigned int reg) {
70 panic("register classification not implemented");
74 // Instruction address compression hooks
75 inline Addr realPCToFetchPC(const Addr &addr)
80 inline Addr fetchPCToRealPC(const Addr &addr)
85 // the size of "fetched" instructions (not necessarily the size
86 // of real instructions for PISA)
87 inline size_t fetchInstSize()
89 return sizeof(MachInst);
93 * Function to insure ISA semantics about 0 registers.
94 * @param tc The thread context.
97 void zeroRegisters(TC *tc);
99 inline void initCPU(ThreadContext *tc, int cpuId)
101 static Fault por = new PowerOnReset();
107 inline void startupCPU(ThreadContext *tc, int cpuId)
110 // Other CPUs will get activated by IPIs
118 } // namespace SparcISA