src/arch/sparc/utility.hh

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Gabe Black
  29  */
  30
  31 #ifndef __ARCH_SPARC_UTILITY_HH__
  32 #define __ARCH_SPARC_UTILITY_HH__
  33
  34 #include "arch/sparc/isa_traits.hh"
  35 #include "arch/sparc/registers.hh"
  36 #include "arch/sparc/tlb.hh"
  37 #include "base/bitfield.hh"
  38 #include "base/logging.hh"
  39 #include "cpu/static_inst.hh"
  40 #include "cpu/thread_context.hh"
  41 #include "sim/full_system.hh"
  42
  43 namespace SparcISA
  44 {
  45
  46 inline PCState
  47 buildRetPC(const PCState &curPC, const PCState &callPC)
  48 {
  49     PCState ret = callPC;
  50     ret.uEnd();
  51     ret.pc(curPC.npc());
  52     return ret;
  53 }
  54
  55 uint64_t getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp);
  56
  57 static inline bool
  58 inUserMode(ThreadContext *tc)
  59 {
  60     PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
  61     HPSTATE hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
  62     return !(pstate.priv || hpstate.hpriv);
  63 }
  64
  65 /**
  66  * Function to insure ISA semantics about 0 registers.
  67  * @param tc The thread context.
  68  */
  69 template <class TC>
  70 void zeroRegisters(TC *tc);
  71
  72 void initCPU(ThreadContext *tc, int cpuId);
  73
  74 inline void
  75 startupCPU(ThreadContext *tc, int cpuId)
  76 {
  77     // Other CPUs will get activated by IPIs
  78     if (cpuId == 0 || !FullSystem)
  79         tc->activate();
  80 }
  81
  82 void copyRegs(ThreadContext *src, ThreadContext *dest);
  83
  84 void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
  85
  86 void skipFunction(ThreadContext *tc);
  87
  88 inline void
  89 advancePC(PCState &pc, const StaticInstPtr &inst)
  90 {
  91     inst->advancePC(pc);
  92 }
  93
  94 inline uint64_t
  95 getExecutingAsid(ThreadContext *tc)
  96 {
  97     return tc->readMiscRegNoEffect(MISCREG_MMU_P_CONTEXT);
  98 }
  99
 100 } // namespace SparcISA
 101
 102 #endif