src/arch/sparc/utility.hh

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Gabe Black
  29  */
  30
  31 #ifndef __ARCH_SPARC_UTILITY_HH__
  32 #define __ARCH_SPARC_UTILITY_HH__
  33
  34 #include "arch/sparc/faults.hh"
  35 #include "arch/sparc/isa_traits.hh"
  36 #include "base/misc.hh"
  37 #include "base/bitfield.hh"
  38 #include "cpu/thread_context.hh"
  39
  40 namespace SparcISA
  41 {
  42     inline ExtMachInst
  43     makeExtMI(MachInst inst, ThreadContext * xc) {
  44         ExtMachInst emi = (unsigned MachInst) inst;
  45         //The I bit, bit 13, is used to figure out where the ASI
  46         //should come from. Use that in the ExtMachInst. This is
  47         //slightly redundant, but it removes the need to put a condition
  48         //into all the execute functions
  49         if(inst & (1 << 13))
  50             emi |= (static_cast<ExtMachInst>(xc->readMiscReg(MISCREG_ASI))
  51                     << (sizeof(MachInst) * 8));
  52         else
  53             emi |= (static_cast<ExtMachInst>(bits(inst, 12, 5))
  54                     << (sizeof(MachInst) * 8));
  55         return emi;
  56     }
  57
  58     inline bool isCallerSaveIntegerRegister(unsigned int reg) {
  59         panic("register classification not implemented");
  60         return false;
  61     }
  62
  63     inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
  64         panic("register classification not implemented");
  65         return false;
  66     }
  67
  68     inline bool isCallerSaveFloatRegister(unsigned int reg) {
  69         panic("register classification not implemented");
  70         return false;
  71     }
  72
  73     inline bool isCalleeSaveFloatRegister(unsigned int reg) {
  74         panic("register classification not implemented");
  75         return false;
  76     }
  77
  78     // Instruction address compression hooks
  79     inline Addr realPCToFetchPC(const Addr &addr)
  80     {
  81         return addr;
  82     }
  83
  84     inline Addr fetchPCToRealPC(const Addr &addr)
  85     {
  86         return addr;
  87     }
  88
  89     // the size of "fetched" instructions (not necessarily the size
  90     // of real instructions for PISA)
  91     inline size_t fetchInstSize()
  92     {
  93         return sizeof(MachInst);
  94     }
  95
  96     /**
  97      * Function to insure ISA semantics about 0 registers.
  98      * @param tc The thread context.
  99      */
 100     template <class TC>
 101     void zeroRegisters(TC *tc);
 102
 103     inline void initCPU(ThreadContext *tc, int cpuId)
 104     {
 105         static Fault por = new PowerOnReset();
 106         por->invoke(tc);
 107     }
 108
 109 } // namespace SparcISA
 110
 111 #endif