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31 #ifndef __ARCH_SPARC_UTILITY_HH__
32 #define __ARCH_SPARC_UTILITY_HH__
34 #include "arch/sparc/faults.hh"
35 #include "arch/sparc/isa_traits.hh"
36 #include "base/misc.hh"
37 #include "base/bitfield.hh"
38 #include "cpu/thread_context.hh"
44 inUserMode(ThreadContext *tc)
46 return !(tc->readMiscReg(MISCREG_PSTATE & (1 << 2)) ||
47 tc->readMiscReg(MISCREG_HPSTATE & (1 << 2)));
51 makeExtMI(MachInst inst, ThreadContext * xc) {
52 ExtMachInst emi = (unsigned MachInst) inst;
53 //The I bit, bit 13, is used to figure out where the ASI
54 //should come from. Use that in the ExtMachInst. This is
55 //slightly redundant, but it removes the need to put a condition
56 //into all the execute functions
58 emi |= (static_cast<ExtMachInst>(xc->readMiscReg(MISCREG_ASI))
59 << (sizeof(MachInst) * 8));
61 emi |= (static_cast<ExtMachInst>(bits(inst, 12, 5))
62 << (sizeof(MachInst) * 8));
66 inline bool isCallerSaveIntegerRegister(unsigned int reg) {
67 panic("register classification not implemented");
71 inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
72 panic("register classification not implemented");
76 inline bool isCallerSaveFloatRegister(unsigned int reg) {
77 panic("register classification not implemented");
81 inline bool isCalleeSaveFloatRegister(unsigned int reg) {
82 panic("register classification not implemented");
86 // Instruction address compression hooks
87 inline Addr realPCToFetchPC(const Addr &addr)
92 inline Addr fetchPCToRealPC(const Addr &addr)
97 // the size of "fetched" instructions (not necessarily the size
98 // of real instructions for PISA)
99 inline size_t fetchInstSize()
101 return sizeof(MachInst);
105 * Function to insure ISA semantics about 0 registers.
106 * @param tc The thread context.
109 void zeroRegisters(TC *tc);
111 inline void initCPU(ThreadContext *tc, int cpuId)
113 static Fault por = new PowerOnReset();
117 } // namespace SparcISA