src/arch/sparc/utility.hh

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Gabe Black
  29  */
  30
  31 #ifndef __ARCH_SPARC_UTILITY_HH__
  32 #define __ARCH_SPARC_UTILITY_HH__
  33
  34 #include "arch/sparc/isa_traits.hh"
  35 #include "arch/sparc/registers.hh"
  36 #include "arch/sparc/tlb.hh"
  37 #include "base/bitfield.hh"
  38 #include "base/misc.hh"
  39 #include "cpu/static_inst.hh"
  40 #include "cpu/thread_context.hh"
  41 #include "sim/fault_fwd.hh"
  42 #include "sim/full_system.hh"
  43
  44 namespace SparcISA
  45 {
  46
  47 inline PCState
  48 buildRetPC(const PCState &curPC, const PCState &callPC)
  49 {
  50     PCState ret = callPC;
  51     ret.uEnd();
  52     ret.pc(curPC.npc());
  53     return ret;
  54 }
  55
  56 uint64_t getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp);
  57
  58 static inline bool
  59 inUserMode(ThreadContext *tc)
  60 {
  61     PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
  62     HPSTATE hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
  63     return !(pstate.priv || hpstate.hpriv);
  64 }
  65
  66 /**
  67  * Function to insure ISA semantics about 0 registers.
  68  * @param tc The thread context.
  69  */
  70 template <class TC>
  71 void zeroRegisters(TC *tc);
  72
  73 void initCPU(ThreadContext *tc, int cpuId);
  74
  75 inline void
  76 startupCPU(ThreadContext *tc, int cpuId)
  77 {
  78     // Other CPUs will get activated by IPIs
  79     if (cpuId == 0 || !FullSystem)
  80         tc->activate();
  81 }
  82
  83 void copyRegs(ThreadContext *src, ThreadContext *dest);
  84
  85 void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
  86
  87 void skipFunction(ThreadContext *tc);
  88
  89 inline void
  90 advancePC(PCState &pc, const StaticInstPtr &inst)
  91 {
  92     inst->advancePC(pc);
  93 }
  94
  95 inline uint64_t
  96 getExecutingAsid(ThreadContext *tc)
  97 {
  98     return tc->readMiscRegNoEffect(MISCREG_MMU_P_CONTEXT);
  99 }
 100
 101 } // namespace SparcISA
 102
 103 #endif