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33 #include "arch/sparc/vtophys.hh"
34 #include "arch/sparc/tlb.hh"
35 #include "base/compiler.hh"
36 #include "base/chunk_generator.hh"
37 #include "base/trace.hh"
38 #include "cpu/thread_context.hh"
39 #include "mem/vport.hh"
48 // In SPARC it's almost always impossible to turn a VA->PA w/o a
49 // context The only times we can kinda do it are if we have a
50 // SegKPM mapping and can find the real address in the tlb or we
51 // have a physical adddress already (beacuse we are looking at the
52 // hypervisor) Either case is rare, so we'll just panic.
54 panic("vtophys() without context on SPARC largly worthless\n");
59 vtophys(ThreadContext
*tc
, Addr addr
)
61 // Here we have many options and are really implementing something like
62 // a fill handler to find the address since there isn't a multilevel
63 // table for us to walk around.
65 // 1. We are currently hyperpriv, return the address unmodified
66 // 2. The mmu is off return(ra->pa)
67 // 3. We are currently priv, use ctx0* tsbs to find the page
68 // 4. We are not priv, use ctxN0* tsbs to find the page
69 // For all accesses we check the tlbs first since it's possible that
70 // long standing pages (e.g. locked kernel mappings) won't be in the tsb
71 uint64_t tlbdata
= tc
->readMiscRegNoEffect(MISCREG_TLB_DATA
);
73 bool hpriv
= bits(tlbdata
,0,0);
74 // bool priv = bits(tlbdata,2,2);
75 bool addr_mask
= bits(tlbdata
,3,3);
76 bool data_real
= !bits(tlbdata
,5,5);
77 bool inst_real
= !bits(tlbdata
,4,4);
78 bool ctx_zero
= bits(tlbdata
,18,16) > 0;
79 int part_id
= bits(tlbdata
,15,8);
80 int pri_context
= bits(tlbdata
,47,32);
81 // int sec_context = bits(tlbdata,63,48);
83 FunctionalPort
*mem
= tc
->getPhysPort();
84 TLB
* itb
= tc
->getITBPtr();
85 TLB
* dtb
= tc
->getDTBPtr();
96 addr
= addr
& VAddrAMask
;
98 tbe
= dtb
->lookup(addr
, part_id
, data_real
, ctx_zero
? 0 : pri_context
,
103 tbe
= itb
->lookup(addr
, part_id
, inst_real
, ctx_zero
? 0 : pri_context
,
108 // We didn't find it in the tlbs, so lets look at the TSBs
109 dtb
->GetTsbPtr(tc
, addr
, ctx_zero
? 0 : pri_context
, tsbs
);
110 va_tag
= bits(addr
, 63, 22);
111 for (int x
= 0; x
< 4; x
++) {
112 ttetag
= betoh(mem
->read
<uint64_t>(tsbs
[x
]));
113 if (ttetag
.valid() && ttetag
.va() == va_tag
) {
114 uint64_t entry
= mem
->read
<uint64_t>(tsbs
[x
]) + sizeof(uint64_t);
115 // I think it's sun4v at least!
116 pte
.populate(betoh(entry
), PageTableEntry::sun4v
);
117 DPRINTF(VtoPhys
, "Virtual(%#x)->Physical(%#x) found in TTE\n",
118 addr
, pte
.translate(addr
));
122 panic("couldn't translate %#x\n", addr
);
126 DPRINTF(VtoPhys
, "Virtual(%#x)->Physical(%#x) found in TLB\n", addr
,
127 pte
.translate(addr
));
129 return pte
.translate(addr
);
132 } // namespace SparcISA