mem-cache: Add multiple eviction stats
[gem5.git] / src / arch / x86 / X86LocalApic.py
1 # Copyright (c) 2012 ARM Limited
2 # All rights reserved.
3 #
4 # The license below extends only to copyright in the software and shall
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8 # licensed hereunder. You may use the software subject to the license
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12 #
13 # Copyright (c) 2008 The Regents of The University of Michigan
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25 # this software without specific prior written permission.
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27 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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33 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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38 #
39 # Authors: Gabe Black
40
41 from m5.defines import buildEnv
42 from m5.params import *
43 from m5.proxy import *
44
45 from m5.objects.BaseInterrupts import BaseInterrupts
46 from m5.objects.ClockDomain import DerivedClockDomain
47 from m5.SimObject import SimObject
48
49 class X86LocalApic(BaseInterrupts):
50 type = 'X86LocalApic'
51 cxx_class = 'X86ISA::Interrupts'
52 cxx_header = 'arch/x86/interrupts.hh'
53 int_master = MasterPort("Port for sending interrupt messages")
54 int_slave = SlavePort("Port for receiving interrupt messages")
55 int_latency = Param.Latency('1ns', \
56 "Latency for an interrupt to propagate through this device.")
57 pio = SlavePort("Programmed I/O port")
58 system = Param.System(Parent.any, "System this device is part of")
59
60 pio_latency = Param.Latency('100ns', 'Programmed IO latency')
61
62 # The clock rate for the local APIC timer is supposed to be the "bus clock"
63 # which we assume is 1/16th the rate of the CPU clock. I don't think this
64 # is a hard rule, but seems to be true in practice. This can be overriden
65 # in configs that use it.
66 clk_domain = Param.DerivedClockDomain(
67 DerivedClockDomain(clk_domain=Parent.clk_domain, clk_divider=16),
68 "The clock for the local APIC. Should not be modified.")