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56 from MemObject
import MemObject
57 from m5
.SimObject
import SimObject
58 from m5
.params
import *
59 from m5
.proxy
import *
60 from m5
import build_env
62 if build_env
['FULL_SYSTEM']:
63 class X86PagetableWalker(MemObject
):
64 type = 'X86PagetableWalker'
65 cxx_namespace
= 'X86ISA'
67 port
= Port("Port for the hardware table walker")
68 system
= Param
.System(Parent
.any
, "system object")
70 class X86TLB(SimObject
):
72 cxx_namespace
= 'X86ISA'
75 size
= Param
.Int("TLB size")
76 if build_env
['FULL_SYSTEM']:
77 walker
= Param
.X86PagetableWalker(\
78 X86PagetableWalker(), "page table walker")
82 cxx_namespace
= 'X86ISA'
89 cxx_namespace
= 'X86ISA'