src/arch/x86/X86TLB.py

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  53 #
  54 # Authors: Gabe Black
  55
  56 from MemObject import MemObject
  57 from m5.SimObject import SimObject
  58 from m5.params import *
  59 from m5.proxy import *
  60 from m5 import build_env
  61
  62 if build_env['FULL_SYSTEM']:
  63     class X86PagetableWalker(MemObject):
  64         type = 'X86PagetableWalker'
  65         cxx_namespace = 'X86ISA'
  66         cxx_class = 'Walker'
  67         port = Port("Port for the hardware table walker")
  68         system = Param.System(Parent.any, "system object")
  69
  70 class X86TLB(SimObject):
  71     type = 'X86TLB'
  72     abstract = True
  73     size = Param.Int("TLB size")
  74     if build_env['FULL_SYSTEM']:
  75         walker = Param.X86PagetableWalker(\
  76                 X86PagetableWalker(), "page table walker")
  77
  78 class X86DTB(X86TLB):
  79     type = 'X86DTB'
  80     cxx_namespace = 'X86ISA'
  81     cxx_class = 'DTB'
  82
  83     size = 64
  84
  85 class X86ITB(X86TLB):
  86     type = 'X86ITB'
  87     cxx_namespace = 'X86ISA'
  88     cxx_class = 'ITB'
  89
  90     size = 64