src/arch/x86/bios/intelmp.hh

   1 /*
   2  * Copyright (c) 2008 The Hewlett-Packard Development Company
   3  * All rights reserved.
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Redistribution and use in source and binary forms, with or without
  15  * modification, are permitted provided that the following conditions are
  16  * met: redistributions of source code must retain the above copyright
  17  * notice, this list of conditions and the following disclaimer;
  18  * redistributions in binary form must reproduce the above copyright
  19  * notice, this list of conditions and the following disclaimer in the
  20  * documentation and/or other materials provided with the distribution;
  21  * neither the name of the copyright holders nor the names of its
  22  * contributors may be used to endorse or promote products derived from
  23  * this software without specific prior written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  *
  37  * Authors: Gabe Black
  38  */
  39
  40 #ifndef __ARCH_X86_BIOS_INTELMP_HH__
  41 #define __ARCH_X86_BIOS_INTELMP_HH__
  42
  43 #include <string>
  44 #include <vector>
  45
  46 #include "base/bitfield.hh"
  47 #include "enums/X86IntelMPAddressType.hh"
  48 #include "enums/X86IntelMPInterruptType.hh"
  49 #include "enums/X86IntelMPPolarity.hh"
  50 #include "enums/X86IntelMPRangeList.hh"
  51 #include "enums/X86IntelMPTriggerMode.hh"
  52 #include "sim/sim_object.hh"
  53
  54 class PortProxy;
  55
  56 // Config entry types
  57 struct X86IntelMPBaseConfigEntryParams;
  58 struct X86IntelMPExtConfigEntryParams;
  59
  60 // General table structures
  61 struct X86IntelMPConfigTableParams;
  62 struct X86IntelMPFloatingPointerParams;
  63
  64 // Base entry types
  65 struct X86IntelMPBusParams;
  66 struct X86IntelMPIOAPICParams;
  67 struct X86IntelMPIOIntAssignmentParams;
  68 struct X86IntelMPLocalIntAssignmentParams;
  69 struct X86IntelMPProcessorParams;
  70
  71 // Extended entry types
  72 struct X86IntelMPAddrSpaceMappingParams;
  73 struct X86IntelMPBusHierarchyParams;
  74 struct X86IntelMPCompatAddrSpaceModParams;
  75
  76 template<class T>
  77 uint8_t writeOutField(PortProxy& proxy, Addr addr, T val);
  78
  79 uint8_t writeOutString(PortProxy& proxy, Addr addr, std::string str,
  80                        int length);
  81
  82 namespace X86ISA
  83 {
  84
  85 namespace IntelMP
  86 {
  87
  88 class FloatingPointer : public SimObject
  89 {
  90   protected:
  91     typedef X86IntelMPFloatingPointerParams Params;
  92
  93     uint32_t tableAddr;
  94     uint8_t specRev;
  95     uint8_t defaultConfig;
  96     bool imcrPresent;
  97
  98     static const char signature[];
  99
 100   public:
 101
 102     Addr writeOut(PortProxy& proxy, Addr addr);
 103
 104     Addr getTableAddr()
 105     {
 106         return tableAddr;
 107     }
 108
 109     void setTableAddr(Addr addr)
 110     {
 111         tableAddr = addr;
 112     }
 113
 114     FloatingPointer(Params * p);
 115 };
 116
 117 class BaseConfigEntry : public SimObject
 118 {
 119   protected:
 120     typedef X86IntelMPBaseConfigEntryParams Params;
 121
 122     uint8_t type;
 123
 124   public:
 125
 126     virtual Addr writeOut(PortProxy& proxy, Addr addr, uint8_t &checkSum);
 127
 128     BaseConfigEntry(Params * p, uint8_t _type);
 129 };
 130
 131 class ExtConfigEntry : public SimObject
 132 {
 133   protected:
 134     typedef X86IntelMPExtConfigEntryParams Params;
 135
 136     uint8_t type;
 137     uint8_t length;
 138
 139   public:
 140
 141     virtual Addr writeOut(PortProxy& proxy, Addr addr, uint8_t &checkSum);
 142
 143     ExtConfigEntry(Params * p, uint8_t _type, uint8_t _length);
 144 };
 145
 146 class ConfigTable : public SimObject
 147 {
 148   protected:
 149     typedef X86IntelMPConfigTableParams Params;
 150
 151     static const char signature[];
 152
 153     uint8_t specRev;
 154     std::string oemID;
 155     std::string productID;
 156     uint32_t oemTableAddr;
 157     uint16_t oemTableSize;
 158     uint32_t localApic;
 159
 160     std::vector<BaseConfigEntry *> baseEntries;
 161     std::vector<ExtConfigEntry *> extEntries;
 162
 163   public:
 164     Addr writeOut(PortProxy& proxy, Addr addr);
 165
 166     ConfigTable(Params * p);
 167 };
 168
 169 class Processor : public BaseConfigEntry
 170 {
 171   protected:
 172     typedef X86IntelMPProcessorParams Params;
 173
 174     uint8_t localApicID;
 175     uint8_t localApicVersion;
 176     uint8_t cpuFlags;
 177     uint32_t cpuSignature;
 178     uint32_t featureFlags;
 179
 180   public:
 181     Addr writeOut(PortProxy& proxy, Addr addr, uint8_t &checkSum);
 182
 183     Processor(Params * p);
 184 };
 185
 186 class Bus : public BaseConfigEntry
 187 {
 188   protected:
 189     typedef X86IntelMPBusParams Params;
 190
 191     uint8_t busID;
 192     std::string busType;
 193
 194   public:
 195     Addr writeOut(PortProxy& proxy, Addr addr, uint8_t &checkSum);
 196
 197     Bus(Params * p);
 198 };
 199
 200 class IOAPIC : public BaseConfigEntry
 201 {
 202   protected:
 203     typedef X86IntelMPIOAPICParams Params;
 204
 205     uint8_t id;
 206     uint8_t version;
 207     uint8_t flags;
 208     uint32_t address;
 209
 210   public:
 211     Addr writeOut(PortProxy& proxy, Addr addr, uint8_t &checkSum);
 212
 213     IOAPIC(Params * p);
 214 };
 215
 216 class IntAssignment : public BaseConfigEntry
 217 {
 218   protected:
 219     uint8_t interruptType;
 220
 221     uint16_t flags;
 222
 223     uint8_t sourceBusID;
 224     uint8_t sourceBusIRQ;
 225
 226     uint8_t destApicID;
 227     uint8_t destApicIntIn;
 228
 229   public:
 230     Addr writeOut(PortProxy& proxy, Addr addr, uint8_t &checkSum);
 231
 232     IntAssignment(X86IntelMPBaseConfigEntryParams * p,
 233             Enums::X86IntelMPInterruptType _interruptType,
 234             Enums::X86IntelMPPolarity polarity,
 235             Enums::X86IntelMPTriggerMode trigger,
 236             uint8_t _type,
 237             uint8_t _sourceBusID, uint8_t _sourceBusIRQ,
 238             uint8_t _destApicID, uint8_t _destApicIntIn) :
 239         BaseConfigEntry(p, _type),
 240         interruptType(_interruptType), flags(0),
 241         sourceBusID(_sourceBusID), sourceBusIRQ(_sourceBusIRQ),
 242         destApicID(_destApicID), destApicIntIn(_destApicIntIn)
 243     {
 244         replaceBits(flags, 0, 1, polarity);
 245         replaceBits(flags, 2, 3, trigger);
 246     }
 247 };
 248
 249 class IOIntAssignment : public IntAssignment
 250 {
 251   protected:
 252     typedef X86IntelMPIOIntAssignmentParams Params;
 253
 254   public:
 255     IOIntAssignment(Params * p);
 256 };
 257
 258 class LocalIntAssignment : public IntAssignment
 259 {
 260   protected:
 261     typedef X86IntelMPLocalIntAssignmentParams Params;
 262
 263   public:
 264     LocalIntAssignment(Params * p);
 265 };
 266
 267 class AddrSpaceMapping : public ExtConfigEntry
 268 {
 269   protected:
 270     typedef X86IntelMPAddrSpaceMappingParams Params;
 271
 272     uint8_t busID;
 273     uint8_t addrType;
 274     uint64_t addr;
 275     uint64_t addrLength;
 276
 277   public:
 278     Addr writeOut(PortProxy& proxy, Addr addr, uint8_t &checkSum);
 279
 280     AddrSpaceMapping(Params * p);
 281 };
 282
 283 class BusHierarchy : public ExtConfigEntry
 284 {
 285   protected:
 286     typedef X86IntelMPBusHierarchyParams Params;
 287
 288     uint8_t busID;
 289     uint8_t info;
 290     uint8_t parentBus;
 291
 292   public:
 293     Addr writeOut(PortProxy& proxy, Addr addr, uint8_t &checkSum);
 294
 295     BusHierarchy(Params * p);
 296 };
 297
 298 class CompatAddrSpaceMod : public ExtConfigEntry
 299 {
 300   protected:
 301     typedef X86IntelMPCompatAddrSpaceModParams Params;
 302
 303     uint8_t busID;
 304     uint8_t mod;
 305     uint32_t rangeList;
 306
 307   public:
 308     Addr writeOut(PortProxy& proxy, Addr addr, uint8_t &checkSum);
 309
 310     CompatAddrSpaceMod(Params * p);
 311 };
 312
 313 } //IntelMP
 314
 315 } //X86ISA
 316
 317 #endif