2 * Copyright (c) 2007 The Hewlett-Packard Development Company
5 * The license below extends only to copyright in the software and shall
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43 #include "arch/x86/decoder.hh"
44 #include "arch/x86/faults.hh"
45 #include "base/trace.hh"
46 #include "config/full_system.hh"
47 #include "cpu/thread_context.hh"
49 #include "arch/x86/isa_traits.hh"
50 #include "mem/page_table.hh"
51 #include "sim/process.hh"
53 #include "arch/x86/tlb.hh"
59 void X86FaultBase::invoke(ThreadContext
* tc
)
61 Addr pc
= tc
->readPC();
62 DPRINTF(Faults
, "RIP %#x: vector %d: %s\n", pc
, vector
, describe());
63 using namespace X86ISAInst::RomLabels
;
64 HandyM5Reg m5reg
= tc
->readMiscRegNoEffect(MISCREG_M5_REG
);
66 if (m5reg
.mode
== LongMode
) {
68 entry
= extern_label_longModeSoftInterrupt
;
70 entry
= extern_label_longModeInterrupt
;
73 entry
= extern_label_legacyModeInterrupt
;
75 tc
->setIntReg(INTREG_MICRO(1), vector
);
76 tc
->setIntReg(INTREG_MICRO(7), pc
);
77 if (errorCode
!= (uint64_t)(-1)) {
78 if (m5reg
.mode
== LongMode
) {
79 entry
= extern_label_longModeInterruptWithError
;
81 panic("Legacy mode interrupts with error codes "
82 "aren't implementde.\n");
84 // Software interrupts shouldn't have error codes. If one does,
85 // there would need to be microcode to set it up.
87 tc
->setIntReg(INTREG_MICRO(15), errorCode
);
89 tc
->setMicroPC(romMicroPC(entry
));
90 tc
->setNextMicroPC(romMicroPC(entry
) + 1);
94 X86FaultBase::describe() const
97 ccprintf(ss
, "%s", mnemonic());
98 if (errorCode
!= (uint64_t)(-1)) {
99 ccprintf(ss
, "(%#x)", errorCode
);
105 void X86Trap::invoke(ThreadContext
* tc
)
107 X86FaultBase::invoke(tc
);
108 // This is the same as a fault, but it happens -after- the instruction.
109 tc
->setPC(tc
->readNextPC());
110 tc
->setNextPC(tc
->readNextNPC());
111 tc
->setNextNPC(tc
->readNextNPC() + sizeof(MachInst
));
114 void X86Abort::invoke(ThreadContext
* tc
)
116 panic("Abort exception!");
119 void PageFault::invoke(ThreadContext
* tc
)
121 HandyM5Reg m5reg
= tc
->readMiscRegNoEffect(MISCREG_M5_REG
);
122 X86FaultBase::invoke(tc
);
124 * If something bad happens while trying to enter the page fault
125 * handler, I'm pretty sure that's a double fault and then all bets are
126 * off. That means it should be safe to update this state now.
128 if (m5reg
.mode
== LongMode
) {
129 tc
->setMiscReg(MISCREG_CR2
, addr
);
131 tc
->setMiscReg(MISCREG_CR2
, (uint32_t)addr
);
136 PageFault::describe() const
138 std::stringstream ss
;
139 ccprintf(ss
, "%s at %#x", X86FaultBase::describe(), addr
);
144 InitInterrupt::invoke(ThreadContext
*tc
)
146 DPRINTF(Faults
, "Init interrupt.\n");
147 // The otherwise unmodified integer registers should be set to 0.
148 for (int index
= 0; index
< NUM_INTREGS
; index
++) {
149 tc
->setIntReg(index
, 0);
152 CR0 cr0
= tc
->readMiscReg(MISCREG_CR0
);
156 tc
->setMiscReg(MISCREG_CR0
, newCR0
);
157 tc
->setMiscReg(MISCREG_CR2
, 0);
158 tc
->setMiscReg(MISCREG_CR3
, 0);
159 tc
->setMiscReg(MISCREG_CR4
, 0);
161 tc
->setMiscReg(MISCREG_RFLAGS
, 0x0000000000000002ULL
);
163 tc
->setMiscReg(MISCREG_EFER
, 0);
165 SegAttr dataAttr
= 0;
167 dataAttr
.unusable
= 0;
168 dataAttr
.defaultSize
= 0;
169 dataAttr
.longMode
= 0;
171 dataAttr
.granularity
= 0;
172 dataAttr
.present
= 1;
174 dataAttr
.writable
= 1;
175 dataAttr
.readable
= 1;
176 dataAttr
.expandDown
= 0;
179 for (int seg
= 0; seg
!= NUM_SEGMENTREGS
; seg
++) {
180 tc
->setMiscReg(MISCREG_SEG_SEL(seg
), 0);
181 tc
->setMiscReg(MISCREG_SEG_BASE(seg
), 0);
182 tc
->setMiscReg(MISCREG_SEG_EFF_BASE(seg
), 0);
183 tc
->setMiscReg(MISCREG_SEG_LIMIT(seg
), 0xffff);
184 tc
->setMiscReg(MISCREG_SEG_ATTR(seg
), dataAttr
);
187 SegAttr codeAttr
= 0;
189 codeAttr
.unusable
= 0;
190 codeAttr
.defaultSize
= 0;
191 codeAttr
.longMode
= 0;
193 codeAttr
.granularity
= 0;
194 codeAttr
.present
= 1;
196 codeAttr
.writable
= 0;
197 codeAttr
.readable
= 1;
198 codeAttr
.expandDown
= 0;
201 tc
->setMiscReg(MISCREG_CS
, 0xf000);
202 tc
->setMiscReg(MISCREG_CS_BASE
,
203 0x00000000ffff0000ULL
);
204 tc
->setMiscReg(MISCREG_CS_EFF_BASE
,
205 0x00000000ffff0000ULL
);
206 // This has the base value pre-added.
207 tc
->setMiscReg(MISCREG_CS_LIMIT
, 0xffffffff);
208 tc
->setMiscReg(MISCREG_CS_ATTR
, codeAttr
);
210 tc
->setPC(0x000000000000fff0ULL
+
211 tc
->readMiscReg(MISCREG_CS_BASE
));
212 tc
->setNextPC(tc
->readPC() + sizeof(MachInst
));
214 tc
->setMiscReg(MISCREG_TSG_BASE
, 0);
215 tc
->setMiscReg(MISCREG_TSG_LIMIT
, 0xffff);
217 tc
->setMiscReg(MISCREG_IDTR_BASE
, 0);
218 tc
->setMiscReg(MISCREG_IDTR_LIMIT
, 0xffff);
220 tc
->setMiscReg(MISCREG_TSL
, 0);
221 tc
->setMiscReg(MISCREG_TSL_BASE
, 0);
222 tc
->setMiscReg(MISCREG_TSL_LIMIT
, 0xffff);
223 tc
->setMiscReg(MISCREG_TSL_ATTR
, 0);
225 tc
->setMiscReg(MISCREG_TR
, 0);
226 tc
->setMiscReg(MISCREG_TR_BASE
, 0);
227 tc
->setMiscReg(MISCREG_TR_LIMIT
, 0xffff);
228 tc
->setMiscReg(MISCREG_TR_ATTR
, 0);
230 // This value should be the family/model/stepping of the processor.
231 // (page 418). It should be consistent with the value from CPUID, but
232 // the actual value probably doesn't matter much.
233 tc
->setIntReg(INTREG_RDX
, 0);
235 tc
->setMiscReg(MISCREG_DR0
, 0);
236 tc
->setMiscReg(MISCREG_DR1
, 0);
237 tc
->setMiscReg(MISCREG_DR2
, 0);
238 tc
->setMiscReg(MISCREG_DR3
, 0);
240 tc
->setMiscReg(MISCREG_DR6
, 0x00000000ffff0ff0ULL
);
241 tc
->setMiscReg(MISCREG_DR7
, 0x0000000000000400ULL
);
243 // Update the handy M5 Reg.
244 tc
->setMiscReg(MISCREG_M5_REG
, 0);
245 MicroPC entry
= X86ISAInst::RomLabels::extern_label_initIntHalt
;
246 tc
->setMicroPC(romMicroPC(entry
));
247 tc
->setNextMicroPC(romMicroPC(entry
) + 1);
251 StartupInterrupt::invoke(ThreadContext
*tc
)
253 DPRINTF(Faults
, "Startup interrupt with vector %#x.\n", vector
);
254 HandyM5Reg m5Reg
= tc
->readMiscReg(MISCREG_M5_REG
);
255 if (m5Reg
.mode
!= LegacyMode
|| m5Reg
.submode
!= RealMode
) {
256 panic("Startup IPI recived outside of real mode. "
257 "Don't know what to do. %d, %d", m5Reg
.mode
, m5Reg
.submode
);
260 tc
->setMiscReg(MISCREG_CS
, vector
<< 8);
261 tc
->setMiscReg(MISCREG_CS_BASE
, vector
<< 12);
262 tc
->setMiscReg(MISCREG_CS_EFF_BASE
, vector
<< 12);
263 // This has the base value pre-added.
264 tc
->setMiscReg(MISCREG_CS_LIMIT
, 0xffff);
266 tc
->setPC(tc
->readMiscReg(MISCREG_CS_BASE
));
267 tc
->setNextPC(tc
->readPC() + sizeof(MachInst
));
273 PageFault::invoke(ThreadContext
* tc
)
275 PageFaultErrorCode code
= errorCode
;
276 const char *modeStr
= "";
283 panic("Tried to %s unmapped address %#x.\n", modeStr
, addr
);
287 } // namespace X86ISA