2 * Copyright (c) 2007 The Hewlett-Packard Development Company
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
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8 * to a hardware implementation of the functionality of the software
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14 * Copyright (c) 2003-2007 The Regents of The University of Michigan
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43 #include "arch/x86/decoder.hh"
44 #include "arch/x86/faults.hh"
45 #include "arch/x86/isa_traits.hh"
46 #include "base/trace.hh"
47 #include "cpu/thread_context.hh"
48 #include "debug/Faults.hh"
49 #include "sim/full_system.hh"
53 void X86FaultBase::invoke(ThreadContext
* tc
, StaticInstPtr inst
)
56 PCState pcState
= tc
->pcState();
57 Addr pc
= pcState
.pc();
58 DPRINTF(Faults
, "RIP %#x: vector %d: %s\n",
59 pc
, vector
, describe());
60 using namespace X86ISAInst::RomLabels
;
61 HandyM5Reg m5reg
= tc
->readMiscRegNoEffect(MISCREG_M5_REG
);
63 if (m5reg
.mode
== LongMode
) {
65 entry
= extern_label_longModeSoftInterrupt
;
67 entry
= extern_label_longModeInterrupt
;
70 entry
= extern_label_legacyModeInterrupt
;
72 tc
->setIntReg(INTREG_MICRO(1), vector
);
73 tc
->setIntReg(INTREG_MICRO(7), pc
);
74 if (errorCode
!= (uint64_t)(-1)) {
75 if (m5reg
.mode
== LongMode
) {
76 entry
= extern_label_longModeInterruptWithError
;
78 panic("Legacy mode interrupts with error codes "
79 "aren't implementde.\n");
81 // Software interrupts shouldn't have error codes. If one
82 // does, there would need to be microcode to set it up.
84 tc
->setIntReg(INTREG_MICRO(15), errorCode
);
86 pcState
.upc(romMicroPC(entry
));
87 pcState
.nupc(romMicroPC(entry
) + 1);
90 FaultBase::invoke(tc
, inst
);
95 X86FaultBase::describe() const
98 ccprintf(ss
, "%s", mnemonic());
99 if (errorCode
!= (uint64_t)(-1)) {
100 ccprintf(ss
, "(%#x)", errorCode
);
106 void X86Trap::invoke(ThreadContext
* tc
, StaticInstPtr inst
)
108 X86FaultBase::invoke(tc
);
110 // This is the same as a fault, but it happens -after- the
112 PCState pc
= tc
->pcState();
117 void X86Abort::invoke(ThreadContext
* tc
, StaticInstPtr inst
)
119 panic("Abort exception!");
123 InvalidOpcode::invoke(ThreadContext
* tc
, StaticInstPtr inst
)
126 X86Fault::invoke(tc
, inst
);
128 panic("Unrecognized/invalid instruction executed:\n %s",
133 void PageFault::invoke(ThreadContext
* tc
, StaticInstPtr inst
)
136 HandyM5Reg m5reg
= tc
->readMiscRegNoEffect(MISCREG_M5_REG
);
137 X86FaultBase::invoke(tc
);
139 * If something bad happens while trying to enter the page fault
140 * handler, I'm pretty sure that's a double fault and then all
141 * bets are off. That means it should be safe to update this
144 if (m5reg
.mode
== LongMode
) {
145 tc
->setMiscReg(MISCREG_CR2
, addr
);
147 tc
->setMiscReg(MISCREG_CR2
, (uint32_t)addr
);
150 PageFaultErrorCode code
= errorCode
;
151 const char *modeStr
= "";
158 panic("Tried to %s unmapped address %#x.\n", modeStr
, addr
);
163 PageFault::describe() const
165 std::stringstream ss
;
166 ccprintf(ss
, "%s at %#x", X86FaultBase::describe(), addr
);
171 InitInterrupt::invoke(ThreadContext
*tc
, StaticInstPtr inst
)
173 DPRINTF(Faults
, "Init interrupt.\n");
174 // The otherwise unmodified integer registers should be set to 0.
175 for (int index
= 0; index
< NUM_INTREGS
; index
++) {
176 tc
->setIntReg(index
, 0);
179 CR0 cr0
= tc
->readMiscReg(MISCREG_CR0
);
183 tc
->setMiscReg(MISCREG_CR0
, newCR0
);
184 tc
->setMiscReg(MISCREG_CR2
, 0);
185 tc
->setMiscReg(MISCREG_CR3
, 0);
186 tc
->setMiscReg(MISCREG_CR4
, 0);
188 tc
->setMiscReg(MISCREG_RFLAGS
, 0x0000000000000002ULL
);
190 tc
->setMiscReg(MISCREG_EFER
, 0);
192 SegAttr dataAttr
= 0;
194 dataAttr
.unusable
= 0;
195 dataAttr
.defaultSize
= 0;
196 dataAttr
.longMode
= 0;
198 dataAttr
.granularity
= 0;
199 dataAttr
.present
= 1;
201 dataAttr
.writable
= 1;
202 dataAttr
.readable
= 1;
203 dataAttr
.expandDown
= 0;
206 for (int seg
= 0; seg
!= NUM_SEGMENTREGS
; seg
++) {
207 tc
->setMiscReg(MISCREG_SEG_SEL(seg
), 0);
208 tc
->setMiscReg(MISCREG_SEG_BASE(seg
), 0);
209 tc
->setMiscReg(MISCREG_SEG_EFF_BASE(seg
), 0);
210 tc
->setMiscReg(MISCREG_SEG_LIMIT(seg
), 0xffff);
211 tc
->setMiscReg(MISCREG_SEG_ATTR(seg
), dataAttr
);
214 SegAttr codeAttr
= 0;
216 codeAttr
.unusable
= 0;
217 codeAttr
.defaultSize
= 0;
218 codeAttr
.longMode
= 0;
220 codeAttr
.granularity
= 0;
221 codeAttr
.present
= 1;
223 codeAttr
.writable
= 0;
224 codeAttr
.readable
= 1;
225 codeAttr
.expandDown
= 0;
228 tc
->setMiscReg(MISCREG_CS
, 0xf000);
229 tc
->setMiscReg(MISCREG_CS_BASE
,
230 0x00000000ffff0000ULL
);
231 tc
->setMiscReg(MISCREG_CS_EFF_BASE
,
232 0x00000000ffff0000ULL
);
233 // This has the base value pre-added.
234 tc
->setMiscReg(MISCREG_CS_LIMIT
, 0xffffffff);
235 tc
->setMiscReg(MISCREG_CS_ATTR
, codeAttr
);
237 PCState
pc(0x000000000000fff0ULL
+ tc
->readMiscReg(MISCREG_CS_BASE
));
240 tc
->setMiscReg(MISCREG_TSG_BASE
, 0);
241 tc
->setMiscReg(MISCREG_TSG_LIMIT
, 0xffff);
243 tc
->setMiscReg(MISCREG_IDTR_BASE
, 0);
244 tc
->setMiscReg(MISCREG_IDTR_LIMIT
, 0xffff);
246 tc
->setMiscReg(MISCREG_TSL
, 0);
247 tc
->setMiscReg(MISCREG_TSL_BASE
, 0);
248 tc
->setMiscReg(MISCREG_TSL_LIMIT
, 0xffff);
249 tc
->setMiscReg(MISCREG_TSL_ATTR
, 0);
251 tc
->setMiscReg(MISCREG_TR
, 0);
252 tc
->setMiscReg(MISCREG_TR_BASE
, 0);
253 tc
->setMiscReg(MISCREG_TR_LIMIT
, 0xffff);
254 tc
->setMiscReg(MISCREG_TR_ATTR
, 0);
256 // This value should be the family/model/stepping of the processor.
257 // (page 418). It should be consistent with the value from CPUID, but
258 // the actual value probably doesn't matter much.
259 tc
->setIntReg(INTREG_RDX
, 0);
261 tc
->setMiscReg(MISCREG_DR0
, 0);
262 tc
->setMiscReg(MISCREG_DR1
, 0);
263 tc
->setMiscReg(MISCREG_DR2
, 0);
264 tc
->setMiscReg(MISCREG_DR3
, 0);
266 tc
->setMiscReg(MISCREG_DR6
, 0x00000000ffff0ff0ULL
);
267 tc
->setMiscReg(MISCREG_DR7
, 0x0000000000000400ULL
);
269 // Update the handy M5 Reg.
270 tc
->setMiscReg(MISCREG_M5_REG
, 0);
271 MicroPC entry
= X86ISAInst::RomLabels::extern_label_initIntHalt
;
272 pc
.upc(romMicroPC(entry
));
273 pc
.nupc(romMicroPC(entry
) + 1);
278 StartupInterrupt::invoke(ThreadContext
*tc
, StaticInstPtr inst
)
280 DPRINTF(Faults
, "Startup interrupt with vector %#x.\n", vector
);
281 HandyM5Reg m5Reg
= tc
->readMiscReg(MISCREG_M5_REG
);
282 if (m5Reg
.mode
!= LegacyMode
|| m5Reg
.submode
!= RealMode
) {
283 panic("Startup IPI recived outside of real mode. "
284 "Don't know what to do. %d, %d", m5Reg
.mode
, m5Reg
.submode
);
287 tc
->setMiscReg(MISCREG_CS
, vector
<< 8);
288 tc
->setMiscReg(MISCREG_CS_BASE
, vector
<< 12);
289 tc
->setMiscReg(MISCREG_CS_EFF_BASE
, vector
<< 12);
290 // This has the base value pre-added.
291 tc
->setMiscReg(MISCREG_CS_LIMIT
, 0xffff);
293 tc
->pcState(tc
->readMiscReg(MISCREG_CS_BASE
));
295 } // namespace X86ISA