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88 #include "arch/x86/faults.hh"
89 #include "base/trace.hh"
90 #include "config/full_system.hh"
91 #include "cpu/thread_context.hh"
93 #include "arch/x86/isa_traits.hh"
94 #include "mem/page_table.hh"
95 #include "sim/process.hh"
101 void X86Trap::invoke(ThreadContext
* tc
)
103 panic("X86 faults are not implemented!");
106 void X86Abort::invoke(ThreadContext
* tc
)
108 panic("X86 faults are not implemented!");
111 void X86Interrupt::invoke(ThreadContext
* tc
)
113 panic("X86 faults are not implemented!");
115 #else // !FULL_SYSTEM
116 void FakeITLBFault::invoke(ThreadContext
* tc
)
118 DPRINTF(TLB
, "Invoking an ITLB fault for address %#x at pc %#x.\n",
119 vaddr
, tc
->readPC());
120 Process
*p
= tc
->getProcessPtr();
122 bool success
= p
->pTable
->lookup(vaddr
, entry
);
124 panic("Tried to execute unmapped address %#x.\n", vaddr
);
126 Addr alignedVaddr
= p
->pTable
->pageAlign(vaddr
);
127 DPRINTF(TLB
, "Mapping %#x to %#x\n", alignedVaddr
, entry
.pageStart
);
128 tc
->getITBPtr()->insert(alignedVaddr
, entry
);
132 void FakeDTLBFault::invoke(ThreadContext
* tc
)
134 DPRINTF(TLB
, "Invoking an DTLB fault for address %#x at pc %#x.\n",
135 vaddr
, tc
->readPC());
136 Process
*p
= tc
->getProcessPtr();
138 bool success
= p
->pTable
->lookup(vaddr
, entry
);
140 p
->checkAndAllocNextPage(vaddr
);
141 success
= p
->pTable
->lookup(vaddr
, entry
);
144 panic("Tried to access unmapped address %#x.\n", vaddr
);
146 Addr alignedVaddr
= p
->pTable
->pageAlign(vaddr
);
147 DPRINTF(TLB
, "Mapping %#x to %#x\n", alignedVaddr
, entry
.pageStart
);
148 tc
->getDTBPtr()->insert(alignedVaddr
, entry
);
152 } // namespace X86ISA