src/arch/x86/faults.hh

   1 /*
   2  * Copyright (c) 2007 The Hewlett-Packard Development Company
   3  * All rights reserved.
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Redistribution and use in source and binary forms, with or without
  15  * modification, are permitted provided that the following conditions are
  16  * met: redistributions of source code must retain the above copyright
  17  * notice, this list of conditions and the following disclaimer;
  18  * redistributions in binary form must reproduce the above copyright
  19  * notice, this list of conditions and the following disclaimer in the
  20  * documentation and/or other materials provided with the distribution;
  21  * neither the name of the copyright holders nor the names of its
  22  * contributors may be used to endorse or promote products derived from
  23  * this software without specific prior written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  *
  37  * Authors: Gabe Black
  38  */
  39
  40 #ifndef __ARCH_X86_FAULTS_HH__
  41 #define __ARCH_X86_FAULTS_HH__
  42
  43 #include <string>
  44
  45 #include "arch/x86/tlb.hh"
  46 #include "base/bitunion.hh"
  47 #include "base/misc.hh"
  48 #include "sim/faults.hh"
  49
  50 namespace X86ISA
  51 {
  52     // Base class for all x86 "faults" where faults is in the m5 sense
  53     class X86FaultBase : public FaultBase
  54     {
  55       protected:
  56         const char * faultName;
  57         const char * mnem;
  58         uint8_t vector;
  59         uint64_t errorCode;
  60
  61         X86FaultBase(const char * _faultName, const char * _mnem,
  62                      const uint8_t _vector, uint64_t _errorCode = (uint64_t)-1)
  63             : faultName(_faultName), mnem(_mnem),
  64               vector(_vector), errorCode(_errorCode)
  65         {
  66         }
  67
  68         const char * name() const
  69         {
  70             return faultName;
  71         }
  72
  73         virtual bool isBenign()
  74         {
  75             return true;
  76         }
  77
  78         virtual const char * mnemonic() const
  79         {
  80             return mnem;
  81         }
  82
  83         virtual bool isSoft()
  84         {
  85             return false;
  86         }
  87
  88         void invoke(ThreadContext * tc, const StaticInstPtr &inst =
  89                     StaticInst::nullStaticInstPtr);
  90
  91         virtual std::string describe() const;
  92
  93       public:
  94         /**
  95          * Get the vector of an interrupt.
  96          *
  97          * @return interrupt vector number.
  98          */
  99         virtual uint8_t getVector() const { return vector; }
 100     };
 101
 102     // Base class for x86 faults which behave as if the underlying instruction
 103     // didn't happen.
 104     class X86Fault : public X86FaultBase
 105     {
 106       protected:
 107         X86Fault(const char * name, const char * mnem,
 108                  const uint8_t vector, uint64_t _errorCode = (uint64_t)-1)
 109             : X86FaultBase(name, mnem, vector, _errorCode)
 110         {}
 111     };
 112
 113     // Base class for x86 traps which behave as if the underlying instruction
 114     // completed.
 115     class X86Trap : public X86FaultBase
 116     {
 117       protected:
 118         X86Trap(const char * name, const char * mnem,
 119                 const uint8_t vector, uint64_t _errorCode = (uint64_t)-1)
 120             : X86FaultBase(name, mnem, vector, _errorCode)
 121         {}
 122
 123         void invoke(ThreadContext * tc, const StaticInstPtr &inst =
 124                     StaticInst::nullStaticInstPtr);
 125     };
 126
 127     // Base class for x86 aborts which seem to be catastrophic failures.
 128     class X86Abort : public X86FaultBase
 129     {
 130       protected:
 131         X86Abort(const char * name, const char * mnem,
 132                 const uint8_t vector, uint64_t _errorCode = (uint64_t)-1)
 133             : X86FaultBase(name, mnem, vector, _errorCode)
 134         {}
 135
 136         void invoke(ThreadContext * tc, const StaticInstPtr &inst =
 137                     StaticInst::nullStaticInstPtr);
 138     };
 139
 140     // Base class for x86 interrupts.
 141     class X86Interrupt : public X86FaultBase
 142     {
 143       protected:
 144         X86Interrupt(const char * name, const char * mnem,
 145                 const uint8_t _vector, uint64_t _errorCode = (uint64_t)-1)
 146             : X86FaultBase(name, mnem, _vector, _errorCode)
 147         {}
 148     };
 149
 150     class UnimpInstFault : public FaultBase
 151     {
 152       public:
 153         const char * name() const
 154         {
 155             return "unimplemented_micro";
 156         }
 157
 158         void invoke(ThreadContext * tc, const StaticInstPtr &inst =
 159                     StaticInst::nullStaticInstPtr)
 160         {
 161             panic("Unimplemented instruction!");
 162         }
 163     };
 164
 165     // Below is a summary of the interrupt/exception information in the
 166     // architecture manuals.
 167
 168     // Class  |  Type    | vector |               Cause                 | mnem
 169     //------------------------------------------------------------------------
 170     //Contrib   Fault     0         Divide Error                          #DE
 171     //Benign    Either    1         Debug                                 #DB
 172     //Benign    Interrupt 2         Non-Maskable-Interrupt                #NMI
 173     //Benign    Trap      3         Breakpoint                            #BP
 174     //Benign    Trap      4         Overflow                              #OF
 175     //Benign    Fault     5         Bound-Range                           #BR
 176     //Benign    Fault     6         Invalid-Opcode                        #UD
 177     //Benign    Fault     7         Device-Not-Available                  #NM
 178     //Benign    Abort     8         Double-Fault                          #DF
 179     //                    9         Coprocessor-Segment-Overrun
 180     //Contrib   Fault     10        Invalid-TSS                           #TS
 181     //Contrib   Fault     11        Segment-Not-Present                   #NP
 182     //Contrib   Fault     12        Stack                                 #SS
 183     //Contrib   Fault     13        General-Protection                    #GP
 184     //Either    Fault     14        Page-Fault                            #PF
 185     //                    15        Reserved
 186     //Benign    Fault     16        x87 Floating-Point Exception Pending  #MF
 187     //Benign    Fault     17        Alignment-Check                       #AC
 188     //Benign    Abort     18        Machine-Check                         #MC
 189     //Benign    Fault     19        SIMD Floating-Point                   #XF
 190     //                    20-29     Reserved
 191     //Contrib   ?         30        Security Exception                    #SX
 192     //                    31        Reserved
 193     //Benign    Interrupt 0-255     External Interrupts                   #INTR
 194     //Benign    Interrupt 0-255     Software Interrupts                   INTn
 195
 196     // Note that
 197     class DivideError : public X86Fault
 198     {
 199       public:
 200         DivideError() :
 201             X86Fault("Divide-Error", "#DE", 0)
 202         {}
 203     };
 204
 205     class DebugException : public X86FaultBase
 206     {
 207       public:
 208         DebugException() :
 209             X86FaultBase("Debug", "#DB", 1)
 210         {}
 211     };
 212
 213     class NonMaskableInterrupt : public X86Interrupt
 214     {
 215       public:
 216         NonMaskableInterrupt(uint8_t _vector) :
 217             X86Interrupt("Non Maskable Interrupt", "#NMI", 2, _vector)
 218         {}
 219     };
 220
 221     class Breakpoint : public X86Trap
 222     {
 223       public:
 224         Breakpoint() :
 225             X86Trap("Breakpoint", "#BP", 3)
 226         {}
 227     };
 228
 229     class OverflowTrap : public X86Trap
 230     {
 231       public:
 232         OverflowTrap() :
 233             X86Trap("Overflow", "#OF", 4)
 234         {}
 235     };
 236
 237     class BoundRange : public X86Fault
 238     {
 239       public:
 240         BoundRange() :
 241             X86Fault("Bound-Range", "#BR", 5)
 242         {}
 243     };
 244
 245     class InvalidOpcode : public X86Fault
 246     {
 247       public:
 248         InvalidOpcode() :
 249             X86Fault("Invalid-Opcode", "#UD", 6)
 250         {}
 251
 252         void invoke(ThreadContext * tc, const StaticInstPtr &inst =
 253                     StaticInst::nullStaticInstPtr);
 254     };
 255
 256     class DeviceNotAvailable : public X86Fault
 257     {
 258       public:
 259         DeviceNotAvailable() :
 260             X86Fault("Device-Not-Available", "#NM", 7)
 261         {}
 262     };
 263
 264     class DoubleFault : public X86Abort
 265     {
 266       public:
 267         DoubleFault() :
 268             X86Abort("Double-Fault", "#DF", 8, 0)
 269         {}
 270     };
 271
 272     class InvalidTSS : public X86Fault
 273     {
 274       public:
 275         InvalidTSS(uint32_t _errorCode) :
 276             X86Fault("Invalid-TSS", "#TS", 10, _errorCode)
 277         {}
 278     };
 279
 280     class SegmentNotPresent : public X86Fault
 281     {
 282       public:
 283         SegmentNotPresent(uint32_t _errorCode) :
 284             X86Fault("Segment-Not-Present", "#NP", 11, _errorCode)
 285         {}
 286     };
 287
 288     class StackFault : public X86Fault
 289     {
 290       public:
 291         StackFault(uint32_t _errorCode) :
 292             X86Fault("Stack", "#SS", 12, _errorCode)
 293         {}
 294     };
 295
 296     class GeneralProtection : public X86Fault
 297     {
 298       public:
 299         GeneralProtection(uint32_t _errorCode) :
 300             X86Fault("General-Protection", "#GP", 13, _errorCode)
 301         {}
 302     };
 303
 304     class PageFault : public X86Fault
 305     {
 306       protected:
 307         BitUnion32(PageFaultErrorCode)
 308             Bitfield<0> present;
 309             Bitfield<1> write;
 310             Bitfield<2> user;
 311             Bitfield<3> reserved;
 312             Bitfield<4> fetch;
 313         EndBitUnion(PageFaultErrorCode)
 314
 315         Addr addr;
 316
 317       public:
 318         PageFault(Addr _addr, uint32_t _errorCode) :
 319             X86Fault("Page-Fault", "#PF", 14, _errorCode), addr(_addr)
 320         {}
 321
 322         PageFault(Addr _addr, bool present, BaseTLB::Mode mode,
 323                 bool user, bool reserved) :
 324             X86Fault("Page-Fault", "#PF", 14, 0), addr(_addr)
 325         {
 326             PageFaultErrorCode code = 0;
 327             code.present = present;
 328             code.write = (mode == BaseTLB::Write);
 329             code.user = user;
 330             code.reserved = reserved;
 331             code.fetch = (mode == BaseTLB::Execute);
 332             errorCode = code;
 333         }
 334
 335         void invoke(ThreadContext * tc, const StaticInstPtr &inst =
 336                     StaticInst::nullStaticInstPtr);
 337
 338         virtual std::string describe() const;
 339     };
 340
 341     class X87FpExceptionPending : public X86Fault
 342     {
 343       public:
 344         X87FpExceptionPending() :
 345             X86Fault("x87 Floating-Point Exception Pending", "#MF", 16)
 346         {}
 347     };
 348
 349     class AlignmentCheck : public X86Fault
 350     {
 351       public:
 352         AlignmentCheck() :
 353             X86Fault("Alignment-Check", "#AC", 17, 0)
 354         {}
 355     };
 356
 357     class MachineCheck : public X86Abort
 358     {
 359       public:
 360         MachineCheck() :
 361             X86Abort("Machine-Check", "#MC", 18)
 362         {}
 363     };
 364
 365     class SIMDFloatingPointFault : public X86Fault
 366     {
 367       public:
 368         SIMDFloatingPointFault() :
 369             X86Fault("SIMD Floating-Point", "#XF", 19)
 370         {}
 371     };
 372
 373     class SecurityException : public X86FaultBase
 374     {
 375       public:
 376         SecurityException() :
 377             X86FaultBase("Security Exception", "#SX", 30)
 378         {}
 379     };
 380
 381     class ExternalInterrupt : public X86Interrupt
 382     {
 383       public:
 384         ExternalInterrupt(uint8_t _vector) :
 385             X86Interrupt("External Interrupt", "#INTR", _vector)
 386         {}
 387     };
 388
 389     class SystemManagementInterrupt : public X86Interrupt
 390     {
 391       public:
 392         SystemManagementInterrupt() :
 393             X86Interrupt("System Management Interrupt", "#SMI", 0)
 394         {}
 395     };
 396
 397     class InitInterrupt : public X86Interrupt
 398     {
 399       public:
 400         InitInterrupt(uint8_t _vector) :
 401             X86Interrupt("INIT Interrupt", "#INIT", _vector)
 402         {}
 403
 404         void invoke(ThreadContext * tc, const StaticInstPtr &inst =
 405                     StaticInst::nullStaticInstPtr);
 406     };
 407
 408     class StartupInterrupt : public X86Interrupt
 409     {
 410       public:
 411         StartupInterrupt(uint8_t _vector) :
 412             X86Interrupt("Startup Interrupt", "#SIPI", _vector)
 413         {}
 414
 415         void invoke(ThreadContext * tc, const StaticInstPtr &inst =
 416                     StaticInst::nullStaticInstPtr);
 417     };
 418
 419     class SoftwareInterrupt : public X86Interrupt
 420     {
 421       public:
 422         SoftwareInterrupt(uint8_t _vector) :
 423             X86Interrupt("Software Interrupt", "#INTR", _vector)
 424         {}
 425
 426         bool isSoft()
 427         {
 428             return true;
 429         }
 430     };
 431 }
 432
 433 #endif // __ARCH_X86_FAULTS_HH__