src/arch/x86/faults.hh

   1 /*
   2  * Copyright (c) 2007 The Hewlett-Packard Development Company
   3  * All rights reserved.
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Redistribution and use in source and binary forms, with or without
  15  * modification, are permitted provided that the following conditions are
  16  * met: redistributions of source code must retain the above copyright
  17  * notice, this list of conditions and the following disclaimer;
  18  * redistributions in binary form must reproduce the above copyright
  19  * notice, this list of conditions and the following disclaimer in the
  20  * documentation and/or other materials provided with the distribution;
  21  * neither the name of the copyright holders nor the names of its
  22  * contributors may be used to endorse or promote products derived from
  23  * this software without specific prior written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  *
  37  * Authors: Gabe Black
  38  */
  39
  40 #ifndef __ARCH_X86_FAULTS_HH__
  41 #define __ARCH_X86_FAULTS_HH__
  42
  43 #include "base/bitunion.hh"
  44 #include "base/misc.hh"
  45 #include "sim/faults.hh"
  46 #include "sim/tlb.hh"
  47
  48 #include <string>
  49
  50 namespace X86ISA
  51 {
  52     // Base class for all x86 "faults" where faults is in the m5 sense
  53     class X86FaultBase : public FaultBase
  54     {
  55       protected:
  56         const char * faultName;
  57         const char * mnem;
  58         uint8_t vector;
  59         uint64_t errorCode;
  60
  61         X86FaultBase(const char * _faultName, const char * _mnem,
  62                      const uint8_t _vector, uint64_t _errorCode = (uint64_t)-1)
  63             : faultName(_faultName), mnem(_mnem),
  64               vector(_vector), errorCode(_errorCode)
  65         {
  66         }
  67
  68         const char * name() const
  69         {
  70             return faultName;
  71         }
  72
  73         virtual bool isBenign()
  74         {
  75             return true;
  76         }
  77
  78         virtual const char * mnemonic() const
  79         {
  80             return mnem;
  81         }
  82
  83         virtual bool isSoft()
  84         {
  85             return false;
  86         }
  87
  88 #if FULL_SYSTEM
  89         void invoke(ThreadContext * tc,
  90                 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
  91
  92         virtual std::string describe() const;
  93 #endif
  94     };
  95
  96     // Base class for x86 faults which behave as if the underlying instruction
  97     // didn't happen.
  98     class X86Fault : public X86FaultBase
  99     {
 100       protected:
 101         X86Fault(const char * name, const char * mnem,
 102                  const uint8_t vector, uint64_t _errorCode = (uint64_t)-1)
 103             : X86FaultBase(name, mnem, vector, _errorCode)
 104         {}
 105     };
 106
 107     // Base class for x86 traps which behave as if the underlying instruction
 108     // completed.
 109     class X86Trap : public X86FaultBase
 110     {
 111       protected:
 112         X86Trap(const char * name, const char * mnem,
 113                 const uint8_t vector, uint64_t _errorCode = (uint64_t)-1)
 114             : X86FaultBase(name, mnem, vector, _errorCode)
 115         {}
 116
 117 #if FULL_SYSTEM
 118         void invoke(ThreadContext * tc,
 119                 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 120 #endif
 121     };
 122
 123     // Base class for x86 aborts which seem to be catastrophic failures.
 124     class X86Abort : public X86FaultBase
 125     {
 126       protected:
 127         X86Abort(const char * name, const char * mnem,
 128                 const uint8_t vector, uint64_t _errorCode = (uint64_t)-1)
 129             : X86FaultBase(name, mnem, vector, _errorCode)
 130         {}
 131
 132 #if FULL_SYSTEM
 133         void invoke(ThreadContext * tc,
 134                 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 135 #endif
 136     };
 137
 138     // Base class for x86 interrupts.
 139     class X86Interrupt : public X86FaultBase
 140     {
 141       protected:
 142         X86Interrupt(const char * name, const char * mnem,
 143                 const uint8_t _vector, uint64_t _errorCode = (uint64_t)-1)
 144             : X86FaultBase(name, mnem, _vector, _errorCode)
 145         {}
 146     };
 147
 148     class UnimpInstFault : public FaultBase
 149     {
 150       public:
 151         const char * name() const
 152         {
 153             return "unimplemented_micro";
 154         }
 155
 156         void invoke(ThreadContext * tc,
 157                 StaticInstPtr inst = StaticInst::nullStaticInstPtr)
 158         {
 159             panic("Unimplemented instruction!");
 160         }
 161     };
 162
 163     static inline Fault genMachineCheckFault()
 164     {
 165         panic("Machine check fault not implemented in x86!\n");
 166     }
 167
 168     // Below is a summary of the interrupt/exception information in the
 169     // architecture manuals.
 170
 171     // Class  |  Type    | vector |               Cause                 | mnem
 172     //------------------------------------------------------------------------
 173     //Contrib   Fault     0         Divide-by-Zero-Error                  #DE
 174     //Benign    Either    1         Debug                                 #DB
 175     //Benign    Interrupt 2         Non-Maskable-Interrupt                #NMI
 176     //Benign    Trap      3         Breakpoint                            #BP
 177     //Benign    Trap      4         Overflow                              #OF
 178     //Benign    Fault     5         Bound-Range                           #BR
 179     //Benign    Fault     6         Invalid-Opcode                        #UD
 180     //Benign    Fault     7         Device-Not-Available                  #NM
 181     //Benign    Abort     8         Double-Fault                          #DF
 182     //                    9         Coprocessor-Segment-Overrun
 183     //Contrib   Fault     10        Invalid-TSS                           #TS
 184     //Contrib   Fault     11        Segment-Not-Present                   #NP
 185     //Contrib   Fault     12        Stack                                 #SS
 186     //Contrib   Fault     13        General-Protection                    #GP
 187     //Either    Fault     14        Page-Fault                            #PF
 188     //                    15        Reserved
 189     //Benign    Fault     16        x87 Floating-Point Exception Pending  #MF
 190     //Benign    Fault     17        Alignment-Check                       #AC
 191     //Benign    Abort     18        Machine-Check                         #MC
 192     //Benign    Fault     19        SIMD Floating-Point                   #XF
 193     //                    20-29     Reserved
 194     //Contrib   ?         30        Security Exception                    #SX
 195     //                    31        Reserved
 196     //Benign    Interrupt 0-255     External Interrupts                   #INTR
 197     //Benign    Interrupt 0-255     Software Interrupts                   INTn
 198
 199     class DivideByZero : public X86Fault
 200     {
 201       public:
 202         DivideByZero() :
 203             X86Fault("Divide-by-Zero-Error", "#DE", 0)
 204         {}
 205     };
 206
 207     class DebugException : public X86FaultBase
 208     {
 209       public:
 210         DebugException() :
 211             X86FaultBase("Debug", "#DB", 1)
 212         {}
 213     };
 214
 215     class NonMaskableInterrupt : public X86Interrupt
 216     {
 217       public:
 218         NonMaskableInterrupt(uint8_t _vector) :
 219             X86Interrupt("Non Maskable Interrupt", "#NMI", 2, _vector)
 220         {}
 221     };
 222
 223     class Breakpoint : public X86Trap
 224     {
 225       public:
 226         Breakpoint() :
 227             X86Trap("Breakpoint", "#BP", 3)
 228         {}
 229     };
 230
 231     class OverflowTrap : public X86Trap
 232     {
 233       public:
 234         OverflowTrap() :
 235             X86Trap("Overflow", "#OF", 4)
 236         {}
 237     };
 238
 239     class BoundRange : public X86Fault
 240     {
 241       public:
 242         BoundRange() :
 243             X86Fault("Bound-Range", "#BR", 5)
 244         {}
 245     };
 246
 247     class InvalidOpcode : public X86Fault
 248     {
 249       public:
 250         InvalidOpcode() :
 251             X86Fault("Invalid-Opcode", "#UD", 6)
 252         {}
 253
 254 #if !FULL_SYSTEM
 255         void invoke(ThreadContext * tc,
 256                 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 257 #endif
 258     };
 259
 260     class DeviceNotAvailable : public X86Fault
 261     {
 262       public:
 263         DeviceNotAvailable() :
 264             X86Fault("Device-Not-Available", "#NM", 7)
 265         {}
 266     };
 267
 268     class DoubleFault : public X86Abort
 269     {
 270       public:
 271         DoubleFault() :
 272             X86Abort("Double-Fault", "#DF", 8, 0)
 273         {}
 274     };
 275
 276     class InvalidTSS : public X86Fault
 277     {
 278       public:
 279         InvalidTSS(uint32_t _errorCode) :
 280             X86Fault("Invalid-TSS", "#TS", 10, _errorCode)
 281         {}
 282     };
 283
 284     class SegmentNotPresent : public X86Fault
 285     {
 286       public:
 287         SegmentNotPresent(uint32_t _errorCode) :
 288             X86Fault("Segment-Not-Present", "#NP", 11, _errorCode)
 289         {}
 290     };
 291
 292     class StackFault : public X86Fault
 293     {
 294       public:
 295         StackFault(uint32_t _errorCode) :
 296             X86Fault("Stack", "#SS", 12, _errorCode)
 297         {}
 298     };
 299
 300     class GeneralProtection : public X86Fault
 301     {
 302       public:
 303         GeneralProtection(uint32_t _errorCode) :
 304             X86Fault("General-Protection", "#GP", 13, _errorCode)
 305         {}
 306     };
 307
 308     class PageFault : public X86Fault
 309     {
 310       protected:
 311         BitUnion32(PageFaultErrorCode)
 312             Bitfield<0> present;
 313             Bitfield<1> write;
 314             Bitfield<2> user;
 315             Bitfield<3> reserved;
 316             Bitfield<4> fetch;
 317         EndBitUnion(PageFaultErrorCode)
 318
 319         Addr addr;
 320
 321       public:
 322         PageFault(Addr _addr, uint32_t _errorCode) :
 323             X86Fault("Page-Fault", "#PF", 14, _errorCode), addr(_addr)
 324         {}
 325
 326         PageFault(Addr _addr, bool present, BaseTLB::Mode mode,
 327                 bool user, bool reserved) :
 328             X86Fault("Page-Fault", "#PF", 14, 0), addr(_addr)
 329         {
 330             PageFaultErrorCode code = 0;
 331             code.present = present;
 332             code.write = (mode == BaseTLB::Write);
 333             code.user = user;
 334             code.reserved = reserved;
 335             code.fetch = (mode == BaseTLB::Execute);
 336             errorCode = code;
 337         }
 338
 339         void invoke(ThreadContext * tc,
 340                 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 341
 342 #if FULL_SYSTEM
 343         virtual std::string describe() const;
 344 #endif
 345     };
 346
 347     class X87FpExceptionPending : public X86Fault
 348     {
 349       public:
 350         X87FpExceptionPending() :
 351             X86Fault("x87 Floating-Point Exception Pending", "#MF", 16)
 352         {}
 353     };
 354
 355     class AlignmentCheck : public X86Fault
 356     {
 357       public:
 358         AlignmentCheck() :
 359             X86Fault("Alignment-Check", "#AC", 17, 0)
 360         {}
 361     };
 362
 363     class MachineCheck : public X86Abort
 364     {
 365       public:
 366         MachineCheck() :
 367             X86Abort("Machine-Check", "#MC", 18)
 368         {}
 369     };
 370
 371     class SIMDFloatingPointFault : public X86Fault
 372     {
 373       public:
 374         SIMDFloatingPointFault() :
 375             X86Fault("SIMD Floating-Point", "#XF", 19)
 376         {}
 377     };
 378
 379     class SecurityException : public X86FaultBase
 380     {
 381       public:
 382         SecurityException() :
 383             X86FaultBase("Security Exception", "#SX", 30)
 384         {}
 385     };
 386
 387     class ExternalInterrupt : public X86Interrupt
 388     {
 389       public:
 390         ExternalInterrupt(uint8_t _vector) :
 391             X86Interrupt("External Interrupt", "#INTR", _vector)
 392         {}
 393     };
 394
 395     class SystemManagementInterrupt : public X86Interrupt
 396     {
 397       public:
 398         SystemManagementInterrupt() :
 399             X86Interrupt("System Management Interrupt", "#SMI", 0)
 400         {}
 401     };
 402
 403     class InitInterrupt : public X86Interrupt
 404     {
 405       public:
 406         InitInterrupt(uint8_t _vector) :
 407             X86Interrupt("INIT Interrupt", "#INIT", _vector)
 408         {}
 409
 410         void invoke(ThreadContext * tc,
 411                 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 412     };
 413
 414     class StartupInterrupt : public X86Interrupt
 415     {
 416       public:
 417         StartupInterrupt(uint8_t _vector) :
 418             X86Interrupt("Startup Interrupt", "#SIPI", _vector)
 419         {}
 420
 421         void invoke(ThreadContext * tc,
 422                 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 423     };
 424
 425     class SoftwareInterrupt : public X86Interrupt
 426     {
 427       public:
 428         SoftwareInterrupt(uint8_t _vector) :
 429             X86Interrupt("Software Interrupt", "#INTR", _vector)
 430         {}
 431
 432         bool isSoft()
 433         {
 434             return true;
 435         }
 436     };
 437 };
 438
 439 #endif // __ARCH_X86_FAULTS_HH__