1ec31cae68d7002310002ecba5f6307dd16dad96
[gem5.git] / src / arch / x86 / insts / microldstop.hh
1 /*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * Copyright (c) 2015 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions are
17 * met: redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer;
19 * redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the distribution;
22 * neither the name of the copyright holders nor the names of its
23 * contributors may be used to endorse or promote products derived from
24 * this software without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 */
38
39 #ifndef __ARCH_X86_INSTS_MICROLDSTOP_HH__
40 #define __ARCH_X86_INSTS_MICROLDSTOP_HH__
41
42 #include "arch/x86/insts/microop.hh"
43 #include "arch/x86/ldstflags.hh"
44 #include "mem/packet.hh"
45 #include "mem/request.hh"
46 #include "sim/faults.hh"
47
48 namespace X86ISA
49 {
50 /**
51 * Base class for memory ops
52 */
53 class MemOp : public X86MicroopBase
54 {
55 protected:
56 const uint8_t scale;
57 const RegIndex index;
58 const RegIndex base;
59 const uint64_t disp;
60 const uint8_t segment;
61 const uint8_t dataSize;
62 const uint8_t addressSize;
63 const Request::FlagsType memFlags;
64 RegIndex foldOBit, foldABit;
65
66 //Constructor
67 MemOp(ExtMachInst _machInst,
68 const char * mnem, const char * _instMnem,
69 uint64_t setFlags,
70 uint8_t _scale, InstRegIndex _index, InstRegIndex _base,
71 uint64_t _disp, InstRegIndex _segment,
72 uint8_t _dataSize, uint8_t _addressSize,
73 Request::FlagsType _memFlags,
74 OpClass __opClass) :
75 X86MicroopBase(_machInst, mnem, _instMnem, setFlags, __opClass),
76 scale(_scale), index(_index.index()), base(_base.index()),
77 disp(_disp), segment(_segment.index()),
78 dataSize(_dataSize), addressSize(_addressSize),
79 memFlags(_memFlags | _segment.index())
80 {
81 assert(_segment.index() < NUM_SEGMENTREGS);
82 foldOBit =
83 (dataSize == 1 && !_machInst.rex.present) ? 1 << 6 : 0;
84 foldABit =
85 (addressSize == 1 && !_machInst.rex.present) ? 1 << 6 : 0;
86 }
87 };
88
89 /**
90 * Base class for load and store ops using one register
91 */
92 class LdStOp : public MemOp
93 {
94 protected:
95 const RegIndex data;
96
97 //Constructor
98 LdStOp(ExtMachInst _machInst,
99 const char * mnem, const char * _instMnem,
100 uint64_t setFlags,
101 uint8_t _scale, InstRegIndex _index, InstRegIndex _base,
102 uint64_t _disp, InstRegIndex _segment,
103 InstRegIndex _data,
104 uint8_t _dataSize, uint8_t _addressSize,
105 Request::FlagsType _memFlags,
106 OpClass __opClass) :
107 MemOp(_machInst, mnem, _instMnem, setFlags,
108 _scale, _index, _base, _disp, _segment,
109 _dataSize, _addressSize, _memFlags,
110 __opClass),
111 data(_data.index())
112 {
113 }
114
115 std::string generateDisassembly(
116 Addr pc, const Loader::SymbolTable *symtab) const override;
117 };
118
119 /**
120 * Base class for load and store ops using two registers, we will
121 * call them split ops for this reason. These are mainly used to
122 * implement cmpxchg8b and cmpxchg16b.
123 */
124 class LdStSplitOp : public MemOp
125 {
126 protected:
127 const RegIndex dataLow;
128 const RegIndex dataHi;
129
130 //Constructor
131 LdStSplitOp(ExtMachInst _machInst,
132 const char * mnem, const char * _instMnem,
133 uint64_t setFlags,
134 uint8_t _scale, InstRegIndex _index, InstRegIndex _base,
135 uint64_t _disp, InstRegIndex _segment,
136 InstRegIndex _dataLow, InstRegIndex _dataHi,
137 uint8_t _dataSize, uint8_t _addressSize,
138 Request::FlagsType _memFlags,
139 OpClass __opClass) :
140 MemOp(_machInst, mnem, _instMnem, setFlags,
141 _scale, _index, _base, _disp, _segment,
142 _dataSize, _addressSize, _memFlags,
143 __opClass),
144 dataLow(_dataLow.index()),
145 dataHi(_dataHi.index())
146 {
147 }
148
149 std::string generateDisassembly(
150 Addr pc, const Loader::SymbolTable *symtab) const override;
151 };
152 }
153
154 #endif //__ARCH_X86_INSTS_MICROLDSTOP_HH__