2 * Copyright (c) 2012-2013 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2008 The Hewlett-Packard Development Company
15 * All rights reserved.
17 * The license below extends only to copyright in the software and shall
18 * not be construed as granting a license to any other intellectual
19 * property including but not limited to intellectual property relating
20 * to a hardware implementation of the functionality of the software
21 * licensed hereunder. You may use the software subject to the license
22 * terms below provided that you ensure that this notice is replicated
23 * unmodified and in its entirety in all distributions of the software,
24 * modified or unmodified, in source code or in binary form.
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54 #include "arch/x86/regs/apic.hh"
55 #include "arch/x86/interrupts.hh"
56 #include "arch/x86/intmessage.hh"
57 #include "cpu/base.hh"
58 #include "debug/LocalApic.hh"
59 #include "dev/x86/i82094aa.hh"
60 #include "dev/x86/pc.hh"
61 #include "dev/x86/south_bridge.hh"
62 #include "mem/packet_access.hh"
63 #include "sim/system.hh"
64 #include "sim/full_system.hh"
67 divideFromConf(uint32_t conf
)
69 // This figures out what division we want from the division configuration
70 // register in the local APIC. The encoding is a little odd but it can
71 // be deciphered fairly easily.
72 int shift
= ((conf
& 0x8) >> 1) | (conf
& 0x3);
73 shift
= (shift
+ 1) % 8;
81 decodeAddr(Addr paddr
)
91 regNum
= APIC_VERSION
;
94 regNum
= APIC_TASK_PRIORITY
;
97 regNum
= APIC_ARBITRATION_PRIORITY
;
100 regNum
= APIC_PROCESSOR_PRIORITY
;
106 regNum
= APIC_LOGICAL_DESTINATION
;
109 regNum
= APIC_DESTINATION_FORMAT
;
112 regNum
= APIC_SPURIOUS_INTERRUPT_VECTOR
;
122 regNum
= APIC_IN_SERVICE((paddr
- 0x100) / 0x10);
132 regNum
= APIC_TRIGGER_MODE((paddr
- 0x180) / 0x10);
142 regNum
= APIC_INTERRUPT_REQUEST((paddr
- 0x200) / 0x10);
145 regNum
= APIC_ERROR_STATUS
;
148 regNum
= APIC_INTERRUPT_COMMAND_LOW
;
151 regNum
= APIC_INTERRUPT_COMMAND_HIGH
;
154 regNum
= APIC_LVT_TIMER
;
157 regNum
= APIC_LVT_THERMAL_SENSOR
;
160 regNum
= APIC_LVT_PERFORMANCE_MONITORING_COUNTERS
;
163 regNum
= APIC_LVT_LINT0
;
166 regNum
= APIC_LVT_LINT1
;
169 regNum
= APIC_LVT_ERROR
;
172 regNum
= APIC_INITIAL_COUNT
;
175 regNum
= APIC_CURRENT_COUNT
;
178 regNum
= APIC_DIVIDE_CONFIGURATION
;
181 // A reserved register field.
182 panic("Accessed reserved register field %#x.\n", paddr
);
190 X86ISA::Interrupts::read(PacketPtr pkt
)
192 Addr offset
= pkt
->getAddr() - pioAddr
;
193 //Make sure we're at least only accessing one register.
194 if ((offset
& ~mask(3)) != ((offset
+ pkt
->getSize()) & ~mask(3)))
195 panic("Accessed more than one register at a time in the APIC!\n");
196 ApicRegIndex reg
= decodeAddr(offset
);
197 uint32_t val
= htog(readReg(reg
));
199 "Reading Local APIC register %d at offset %#x as %#x.\n",
201 pkt
->setData(((uint8_t *)&val
) + (offset
& mask(3)));
202 pkt
->makeAtomicResponse();
207 X86ISA::Interrupts::write(PacketPtr pkt
)
209 Addr offset
= pkt
->getAddr() - pioAddr
;
210 //Make sure we're at least only accessing one register.
211 if ((offset
& ~mask(3)) != ((offset
+ pkt
->getSize()) & ~mask(3)))
212 panic("Accessed more than one register at a time in the APIC!\n");
213 ApicRegIndex reg
= decodeAddr(offset
);
214 uint32_t val
= regs
[reg
];
215 pkt
->writeData(((uint8_t *)&val
) + (offset
& mask(3)));
217 "Writing Local APIC register %d at offset %#x as %#x.\n",
218 reg
, offset
, gtoh(val
));
219 setReg(reg
, gtoh(val
));
220 pkt
->makeAtomicResponse();
224 X86ISA::Interrupts::requestInterrupt(uint8_t vector
,
225 uint8_t deliveryMode
, bool level
)
228 * Fixed and lowest-priority delivery mode interrupts are handled
229 * using the IRR/ISR registers, checking against the TPR, etc.
230 * The SMI, NMI, ExtInt, INIT, etc interrupts go straight through.
232 if (deliveryMode
== DeliveryMode::Fixed
||
233 deliveryMode
== DeliveryMode::LowestPriority
) {
234 DPRINTF(LocalApic
, "Interrupt is an %s.\n",
235 DeliveryMode::names
[deliveryMode
]);
236 // Queue up the interrupt in the IRR.
239 if (!getRegArrayBit(APIC_INTERRUPT_REQUEST_BASE
, vector
)) {
240 setRegArrayBit(APIC_INTERRUPT_REQUEST_BASE
, vector
);
242 setRegArrayBit(APIC_TRIGGER_MODE_BASE
, vector
);
244 clearRegArrayBit(APIC_TRIGGER_MODE_BASE
, vector
);
247 } else if (!DeliveryMode::isReserved(deliveryMode
)) {
248 DPRINTF(LocalApic
, "Interrupt is an %s.\n",
249 DeliveryMode::names
[deliveryMode
]);
250 if (deliveryMode
== DeliveryMode::SMI
&& !pendingSmi
) {
251 pendingUnmaskableInt
= pendingSmi
= true;
253 } else if (deliveryMode
== DeliveryMode::NMI
&& !pendingNmi
) {
254 pendingUnmaskableInt
= pendingNmi
= true;
256 } else if (deliveryMode
== DeliveryMode::ExtInt
&& !pendingExtInt
) {
257 pendingExtInt
= true;
258 extIntVector
= vector
;
259 } else if (deliveryMode
== DeliveryMode::INIT
&& !pendingInit
) {
260 pendingUnmaskableInt
= pendingInit
= true;
262 } else if (deliveryMode
== DeliveryMode::SIPI
&&
263 !pendingStartup
&& !startedUp
) {
264 pendingUnmaskableInt
= pendingStartup
= true;
265 startupVector
= vector
;
274 X86ISA::Interrupts::setCPU(BaseCPU
* newCPU
)
277 if (cpu
!= NULL
&& cpu
->cpuId() != newCPU
->cpuId()) {
278 panic("Local APICs can't be moved between CPUs"
279 " with different IDs.\n");
282 initialApicId
= cpu
->cpuId();
283 regs
[APIC_ID
] = (initialApicId
<< 24);
284 pioAddr
= x86LocalAPICAddress(initialApicId
, 0);
289 X86ISA::Interrupts::init()
292 // The local apic must register its address ranges on both its pio
293 // port via the basicpiodevice(piodevice) init() function and its
294 // int port that it inherited from IntDevice. Note IntDevice is
295 // not a SimObject itself.
297 BasicPioDevice::init();
300 // the slave port has a range so inform the connected master
301 intSlavePort
.sendRangeChange();
306 X86ISA::Interrupts::recvMessage(PacketPtr pkt
)
308 Addr offset
= pkt
->getAddr() - x86InterruptAddress(initialApicId
, 0);
309 assert(pkt
->cmd
== MemCmd::MessageReq
);
314 TriggerIntMessage message
= pkt
->get
<TriggerIntMessage
>();
316 "Got Trigger Interrupt message with vector %#x.\n",
319 requestInterrupt(message
.vector
,
320 message
.deliveryMode
, message
.trigger
);
324 panic("Local apic got unknown interrupt message at offset %#x.\n",
328 pkt
->makeAtomicResponse();
334 X86ISA::Interrupts::recvResponse(PacketPtr pkt
)
336 assert(!pkt
->isError());
337 assert(pkt
->cmd
== MemCmd::MessageResp
);
338 if (--pendingIPIs
== 0) {
339 InterruptCommandRegLow low
= regs
[APIC_INTERRUPT_COMMAND_LOW
];
340 // Record that the ICR is now idle.
341 low
.deliveryStatus
= 0;
342 regs
[APIC_INTERRUPT_COMMAND_LOW
] = low
;
344 DPRINTF(LocalApic
, "ICR is now idle.\n");
350 X86ISA::Interrupts::getIntAddrRange() const
352 AddrRangeList ranges
;
353 ranges
.push_back(RangeEx(x86InterruptAddress(initialApicId
, 0),
354 x86InterruptAddress(initialApicId
, 0) +
355 PhysAddrAPICRangeSize
));
361 X86ISA::Interrupts::readReg(ApicRegIndex reg
)
363 if (reg
>= APIC_TRIGGER_MODE(0) &&
364 reg
<= APIC_TRIGGER_MODE(15)) {
365 panic("Local APIC Trigger Mode registers are unimplemented.\n");
368 case APIC_ARBITRATION_PRIORITY
:
369 panic("Local APIC Arbitration Priority register unimplemented.\n");
371 case APIC_PROCESSOR_PRIORITY
:
372 panic("Local APIC Processor Priority register unimplemented.\n");
374 case APIC_ERROR_STATUS
:
375 regs
[APIC_INTERNAL_STATE
] &= ~ULL(0x1);
377 case APIC_CURRENT_COUNT
:
379 if (apicTimerEvent
.scheduled()) {
380 // Compute how many m5 ticks happen per count.
381 uint64_t ticksPerCount
= clockPeriod() *
382 divideFromConf(regs
[APIC_DIVIDE_CONFIGURATION
]);
383 // Compute how many m5 ticks are left.
384 uint64_t val
= apicTimerEvent
.when() - curTick();
385 // Turn that into a count.
386 val
= (val
+ ticksPerCount
- 1) / ticksPerCount
;
399 X86ISA::Interrupts::setReg(ApicRegIndex reg
, uint32_t val
)
401 uint32_t newVal
= val
;
402 if (reg
>= APIC_IN_SERVICE(0) &&
403 reg
<= APIC_IN_SERVICE(15)) {
404 panic("Local APIC In-Service registers are unimplemented.\n");
406 if (reg
>= APIC_TRIGGER_MODE(0) &&
407 reg
<= APIC_TRIGGER_MODE(15)) {
408 panic("Local APIC Trigger Mode registers are unimplemented.\n");
410 if (reg
>= APIC_INTERRUPT_REQUEST(0) &&
411 reg
<= APIC_INTERRUPT_REQUEST(15)) {
412 panic("Local APIC Interrupt Request registers "
413 "are unimplemented.\n");
420 // The Local APIC Version register is read only.
422 case APIC_TASK_PRIORITY
:
425 case APIC_ARBITRATION_PRIORITY
:
426 panic("Local APIC Arbitration Priority register unimplemented.\n");
428 case APIC_PROCESSOR_PRIORITY
:
429 panic("Local APIC Processor Priority register unimplemented.\n");
432 // Remove the interrupt that just completed from the local apic state.
433 clearRegArrayBit(APIC_IN_SERVICE_BASE
, ISRV
);
436 case APIC_LOGICAL_DESTINATION
:
437 newVal
= val
& 0xFF000000;
439 case APIC_DESTINATION_FORMAT
:
440 newVal
= val
| 0x0FFFFFFF;
442 case APIC_SPURIOUS_INTERRUPT_VECTOR
:
443 regs
[APIC_INTERNAL_STATE
] &= ~ULL(1 << 1);
444 regs
[APIC_INTERNAL_STATE
] |= val
& (1 << 8);
446 warn("Focus processor checking not implemented.\n");
448 case APIC_ERROR_STATUS
:
450 if (regs
[APIC_INTERNAL_STATE
] & 0x1) {
451 regs
[APIC_INTERNAL_STATE
] &= ~ULL(0x1);
454 regs
[APIC_INTERNAL_STATE
] |= ULL(0x1);
460 case APIC_INTERRUPT_COMMAND_LOW
:
462 InterruptCommandRegLow low
= regs
[APIC_INTERRUPT_COMMAND_LOW
];
463 // Check if we're already sending an IPI.
464 if (low
.deliveryStatus
) {
469 InterruptCommandRegHigh high
= regs
[APIC_INTERRUPT_COMMAND_HIGH
];
470 TriggerIntMessage message
= 0;
471 message
.destination
= high
.destination
;
472 message
.vector
= low
.vector
;
473 message
.deliveryMode
= low
.deliveryMode
;
474 message
.destMode
= low
.destMode
;
475 message
.level
= low
.level
;
476 message
.trigger
= low
.trigger
;
478 int numContexts
= sys
->numContexts();
479 switch (low
.destShorthand
) {
481 if (message
.deliveryMode
== DeliveryMode::LowestPriority
) {
482 panic("Lowest priority delivery mode "
483 "IPIs aren't implemented.\n");
485 if (message
.destMode
== 1) {
486 int dest
= message
.destination
;
487 hack_once("Assuming logical destinations are 1 << id.\n");
488 for (int i
= 0; i
< numContexts
; i
++) {
494 if (message
.destination
== 0xFF) {
495 for (int i
= 0; i
< numContexts
; i
++) {
496 if (i
== initialApicId
) {
497 requestInterrupt(message
.vector
,
498 message
.deliveryMode
, message
.trigger
);
504 if (message
.destination
== initialApicId
) {
505 requestInterrupt(message
.vector
,
506 message
.deliveryMode
, message
.trigger
);
508 apics
.push_back(message
.destination
);
515 requestInterrupt(message
.vector
,
516 message
.deliveryMode
, message
.trigger
);
519 requestInterrupt(message
.vector
,
520 message
.deliveryMode
, message
.trigger
);
524 for (int i
= 0; i
< numContexts
; i
++) {
525 if (i
!= initialApicId
) {
532 // Record that an IPI is being sent if one actually is.
534 low
.deliveryStatus
= 1;
535 pendingIPIs
+= apics
.size();
537 regs
[APIC_INTERRUPT_COMMAND_LOW
] = low
;
538 intMasterPort
.sendMessage(apics
, message
, sys
->isTimingMode());
539 newVal
= regs
[APIC_INTERRUPT_COMMAND_LOW
];
543 case APIC_LVT_THERMAL_SENSOR
:
544 case APIC_LVT_PERFORMANCE_MONITORING_COUNTERS
:
549 uint64_t readOnlyMask
= (1 << 12) | (1 << 14);
550 newVal
= (val
& ~readOnlyMask
) |
551 (regs
[reg
] & readOnlyMask
);
554 case APIC_INITIAL_COUNT
:
556 newVal
= bits(val
, 31, 0);
557 // Compute how many timer ticks we're being programmed for.
558 uint64_t newCount
= newVal
*
559 (divideFromConf(regs
[APIC_DIVIDE_CONFIGURATION
]));
560 // Schedule on the edge of the next tick plus the new count.
561 Tick offset
= curTick() % clockPeriod();
563 reschedule(apicTimerEvent
,
564 curTick() + (newCount
+ 1) *
565 clockPeriod() - offset
, true);
568 reschedule(apicTimerEvent
,
569 curTick() + newCount
*
570 clockPeriod(), true);
574 case APIC_CURRENT_COUNT
:
575 //Local APIC Current Count register is read only.
577 case APIC_DIVIDE_CONFIGURATION
:
588 X86ISA::Interrupts::Interrupts(Params
* p
)
589 : BasicPioDevice(p
, PageBytes
), IntDevice(this, p
->int_latency
),
590 apicTimerEvent(this),
591 pendingSmi(false), smiVector(0),
592 pendingNmi(false), nmiVector(0),
593 pendingExtInt(false), extIntVector(0),
594 pendingInit(false), initVector(0),
595 pendingStartup(false), startupVector(0),
596 startedUp(false), pendingUnmaskableInt(false),
597 pendingIPIs(0), cpu(NULL
),
598 intSlavePort(name() + ".int_slave", this, this)
600 memset(regs
, 0, sizeof(regs
));
601 //Set the local apic DFR to the flat model.
602 regs
[APIC_DESTINATION_FORMAT
] = (uint32_t)(-1);
609 X86ISA::Interrupts::checkInterrupts(ThreadContext
*tc
) const
611 RFLAGS rflags
= tc
->readMiscRegNoEffect(MISCREG_RFLAGS
);
612 if (pendingUnmaskableInt
) {
613 DPRINTF(LocalApic
, "Reported pending unmaskable interrupt.\n");
618 DPRINTF(LocalApic
, "Reported pending external interrupt.\n");
621 if (IRRV
> ISRV
&& bits(IRRV
, 7, 4) >
622 bits(regs
[APIC_TASK_PRIORITY
], 7, 4)) {
623 DPRINTF(LocalApic
, "Reported pending regular interrupt.\n");
631 X86ISA::Interrupts::checkInterruptsRaw() const
633 return pendingUnmaskableInt
|| pendingExtInt
||
634 (IRRV
> ISRV
&& bits(IRRV
, 7, 4) >
635 bits(regs
[APIC_TASK_PRIORITY
], 7, 4));
639 X86ISA::Interrupts::getInterrupt(ThreadContext
*tc
)
641 assert(checkInterrupts(tc
));
642 // These are all probably fairly uncommon, so we'll make them easier to
644 if (pendingUnmaskableInt
) {
646 DPRINTF(LocalApic
, "Generated SMI fault object.\n");
647 return std::make_shared
<SystemManagementInterrupt
>();
648 } else if (pendingNmi
) {
649 DPRINTF(LocalApic
, "Generated NMI fault object.\n");
650 return std::make_shared
<NonMaskableInterrupt
>(nmiVector
);
651 } else if (pendingInit
) {
652 DPRINTF(LocalApic
, "Generated INIT fault object.\n");
653 return std::make_shared
<InitInterrupt
>(initVector
);
654 } else if (pendingStartup
) {
655 DPRINTF(LocalApic
, "Generating SIPI fault object.\n");
656 return std::make_shared
<StartupInterrupt
>(startupVector
);
658 panic("pendingUnmaskableInt set, but no unmaskable "
659 "ints were pending.\n");
662 } else if (pendingExtInt
) {
663 DPRINTF(LocalApic
, "Generated external interrupt fault object.\n");
664 return std::make_shared
<ExternalInterrupt
>(extIntVector
);
666 DPRINTF(LocalApic
, "Generated regular interrupt fault object.\n");
667 // The only thing left are fixed and lowest priority interrupts.
668 return std::make_shared
<ExternalInterrupt
>(IRRV
);
673 X86ISA::Interrupts::updateIntrInfo(ThreadContext
*tc
)
675 assert(checkInterrupts(tc
));
676 if (pendingUnmaskableInt
) {
678 DPRINTF(LocalApic
, "SMI sent to core.\n");
680 } else if (pendingNmi
) {
681 DPRINTF(LocalApic
, "NMI sent to core.\n");
683 } else if (pendingInit
) {
684 DPRINTF(LocalApic
, "Init sent to core.\n");
687 } else if (pendingStartup
) {
688 DPRINTF(LocalApic
, "SIPI sent to core.\n");
689 pendingStartup
= false;
692 if (!(pendingSmi
|| pendingNmi
|| pendingInit
|| pendingStartup
))
693 pendingUnmaskableInt
= false;
694 } else if (pendingExtInt
) {
695 pendingExtInt
= false;
697 DPRINTF(LocalApic
, "Interrupt %d sent to core.\n", IRRV
);
698 // Mark the interrupt as "in service".
700 setRegArrayBit(APIC_IN_SERVICE_BASE
, ISRV
);
701 // Clear it out of the IRR.
702 clearRegArrayBit(APIC_INTERRUPT_REQUEST_BASE
, IRRV
);
708 X86ISA::Interrupts::serialize(CheckpointOut
&cp
) const
710 SERIALIZE_ARRAY(regs
, NUM_APIC_REGS
);
711 SERIALIZE_SCALAR(pendingSmi
);
712 SERIALIZE_SCALAR(smiVector
);
713 SERIALIZE_SCALAR(pendingNmi
);
714 SERIALIZE_SCALAR(nmiVector
);
715 SERIALIZE_SCALAR(pendingExtInt
);
716 SERIALIZE_SCALAR(extIntVector
);
717 SERIALIZE_SCALAR(pendingInit
);
718 SERIALIZE_SCALAR(initVector
);
719 SERIALIZE_SCALAR(pendingStartup
);
720 SERIALIZE_SCALAR(startupVector
);
721 SERIALIZE_SCALAR(startedUp
);
722 SERIALIZE_SCALAR(pendingUnmaskableInt
);
723 SERIALIZE_SCALAR(pendingIPIs
);
724 SERIALIZE_SCALAR(IRRV
);
725 SERIALIZE_SCALAR(ISRV
);
726 bool apicTimerEventScheduled
= apicTimerEvent
.scheduled();
727 SERIALIZE_SCALAR(apicTimerEventScheduled
);
728 Tick apicTimerEventTick
= apicTimerEvent
.when();
729 SERIALIZE_SCALAR(apicTimerEventTick
);
733 X86ISA::Interrupts::unserialize(CheckpointIn
&cp
)
735 UNSERIALIZE_ARRAY(regs
, NUM_APIC_REGS
);
736 UNSERIALIZE_SCALAR(pendingSmi
);
737 UNSERIALIZE_SCALAR(smiVector
);
738 UNSERIALIZE_SCALAR(pendingNmi
);
739 UNSERIALIZE_SCALAR(nmiVector
);
740 UNSERIALIZE_SCALAR(pendingExtInt
);
741 UNSERIALIZE_SCALAR(extIntVector
);
742 UNSERIALIZE_SCALAR(pendingInit
);
743 UNSERIALIZE_SCALAR(initVector
);
744 UNSERIALIZE_SCALAR(pendingStartup
);
745 UNSERIALIZE_SCALAR(startupVector
);
746 UNSERIALIZE_SCALAR(startedUp
);
747 UNSERIALIZE_SCALAR(pendingUnmaskableInt
);
748 UNSERIALIZE_SCALAR(pendingIPIs
);
749 UNSERIALIZE_SCALAR(IRRV
);
750 UNSERIALIZE_SCALAR(ISRV
);
751 bool apicTimerEventScheduled
;
752 UNSERIALIZE_SCALAR(apicTimerEventScheduled
);
753 if (apicTimerEventScheduled
) {
754 Tick apicTimerEventTick
;
755 UNSERIALIZE_SCALAR(apicTimerEventTick
);
756 if (apicTimerEvent
.scheduled()) {
757 reschedule(apicTimerEvent
, apicTimerEventTick
, true);
759 schedule(apicTimerEvent
, apicTimerEventTick
);
765 X86LocalApicParams::create()
767 return new X86ISA::Interrupts(this);