2 * Copyright (c) 2012-2013 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2008 The Hewlett-Packard Development Company
15 * All rights reserved.
17 * The license below extends only to copyright in the software and shall
18 * not be construed as granting a license to any other intellectual
19 * property including but not limited to intellectual property relating
20 * to a hardware implementation of the functionality of the software
21 * licensed hereunder. You may use the software subject to the license
22 * terms below provided that you ensure that this notice is replicated
23 * unmodified and in its entirety in all distributions of the software,
24 * modified or unmodified, in source code or in binary form.
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27 * modification, are permitted provided that the following conditions are
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47 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 #include "arch/x86/regs/apic.hh"
55 #include "arch/x86/interrupts.hh"
56 #include "arch/x86/intmessage.hh"
57 #include "cpu/base.hh"
58 #include "debug/LocalApic.hh"
59 #include "dev/x86/i82094aa.hh"
60 #include "dev/x86/pc.hh"
61 #include "dev/x86/south_bridge.hh"
62 #include "mem/packet_access.hh"
63 #include "sim/system.hh"
64 #include "sim/full_system.hh"
67 divideFromConf(uint32_t conf
)
69 // This figures out what division we want from the division configuration
70 // register in the local APIC. The encoding is a little odd but it can
71 // be deciphered fairly easily.
72 int shift
= ((conf
& 0x8) >> 1) | (conf
& 0x3);
73 shift
= (shift
+ 1) % 8;
81 decodeAddr(Addr paddr
)
91 regNum
= APIC_VERSION
;
94 regNum
= APIC_TASK_PRIORITY
;
97 regNum
= APIC_ARBITRATION_PRIORITY
;
100 regNum
= APIC_PROCESSOR_PRIORITY
;
106 regNum
= APIC_LOGICAL_DESTINATION
;
109 regNum
= APIC_DESTINATION_FORMAT
;
112 regNum
= APIC_SPURIOUS_INTERRUPT_VECTOR
;
130 regNum
= APIC_IN_SERVICE((paddr
- 0x100) / 0x8);
148 regNum
= APIC_TRIGGER_MODE((paddr
- 0x180) / 0x8);
166 regNum
= APIC_INTERRUPT_REQUEST((paddr
- 0x200) / 0x8);
169 regNum
= APIC_ERROR_STATUS
;
172 regNum
= APIC_INTERRUPT_COMMAND_LOW
;
175 regNum
= APIC_INTERRUPT_COMMAND_HIGH
;
178 regNum
= APIC_LVT_TIMER
;
181 regNum
= APIC_LVT_THERMAL_SENSOR
;
184 regNum
= APIC_LVT_PERFORMANCE_MONITORING_COUNTERS
;
187 regNum
= APIC_LVT_LINT0
;
190 regNum
= APIC_LVT_LINT1
;
193 regNum
= APIC_LVT_ERROR
;
196 regNum
= APIC_INITIAL_COUNT
;
199 regNum
= APIC_CURRENT_COUNT
;
202 regNum
= APIC_DIVIDE_CONFIGURATION
;
205 // A reserved register field.
206 panic("Accessed reserved register field %#x.\n", paddr
);
214 X86ISA::Interrupts::read(PacketPtr pkt
)
216 Addr offset
= pkt
->getAddr() - pioAddr
;
217 //Make sure we're at least only accessing one register.
218 if ((offset
& ~mask(3)) != ((offset
+ pkt
->getSize()) & ~mask(3)))
219 panic("Accessed more than one register at a time in the APIC!\n");
220 ApicRegIndex reg
= decodeAddr(offset
);
221 uint32_t val
= htog(readReg(reg
));
223 "Reading Local APIC register %d at offset %#x as %#x.\n",
225 pkt
->setData(((uint8_t *)&val
) + (offset
& mask(3)));
226 pkt
->makeAtomicResponse();
231 X86ISA::Interrupts::write(PacketPtr pkt
)
233 Addr offset
= pkt
->getAddr() - pioAddr
;
234 //Make sure we're at least only accessing one register.
235 if ((offset
& ~mask(3)) != ((offset
+ pkt
->getSize()) & ~mask(3)))
236 panic("Accessed more than one register at a time in the APIC!\n");
237 ApicRegIndex reg
= decodeAddr(offset
);
238 uint32_t val
= regs
[reg
];
239 pkt
->writeData(((uint8_t *)&val
) + (offset
& mask(3)));
241 "Writing Local APIC register %d at offset %#x as %#x.\n",
242 reg
, offset
, gtoh(val
));
243 setReg(reg
, gtoh(val
));
244 pkt
->makeAtomicResponse();
248 X86ISA::Interrupts::requestInterrupt(uint8_t vector
,
249 uint8_t deliveryMode
, bool level
)
252 * Fixed and lowest-priority delivery mode interrupts are handled
253 * using the IRR/ISR registers, checking against the TPR, etc.
254 * The SMI, NMI, ExtInt, INIT, etc interrupts go straight through.
256 if (deliveryMode
== DeliveryMode::Fixed
||
257 deliveryMode
== DeliveryMode::LowestPriority
) {
258 DPRINTF(LocalApic
, "Interrupt is an %s.\n",
259 DeliveryMode::names
[deliveryMode
]);
260 // Queue up the interrupt in the IRR.
263 if (!getRegArrayBit(APIC_INTERRUPT_REQUEST_BASE
, vector
)) {
264 setRegArrayBit(APIC_INTERRUPT_REQUEST_BASE
, vector
);
266 setRegArrayBit(APIC_TRIGGER_MODE_BASE
, vector
);
268 clearRegArrayBit(APIC_TRIGGER_MODE_BASE
, vector
);
271 } else if (!DeliveryMode::isReserved(deliveryMode
)) {
272 DPRINTF(LocalApic
, "Interrupt is an %s.\n",
273 DeliveryMode::names
[deliveryMode
]);
274 if (deliveryMode
== DeliveryMode::SMI
&& !pendingSmi
) {
275 pendingUnmaskableInt
= pendingSmi
= true;
277 } else if (deliveryMode
== DeliveryMode::NMI
&& !pendingNmi
) {
278 pendingUnmaskableInt
= pendingNmi
= true;
280 } else if (deliveryMode
== DeliveryMode::ExtInt
&& !pendingExtInt
) {
281 pendingExtInt
= true;
282 extIntVector
= vector
;
283 } else if (deliveryMode
== DeliveryMode::INIT
&& !pendingInit
) {
284 pendingUnmaskableInt
= pendingInit
= true;
286 } else if (deliveryMode
== DeliveryMode::SIPI
&&
287 !pendingStartup
&& !startedUp
) {
288 pendingUnmaskableInt
= pendingStartup
= true;
289 startupVector
= vector
;
298 X86ISA::Interrupts::setCPU(BaseCPU
* newCPU
)
301 if (cpu
!= NULL
&& cpu
->cpuId() != newCPU
->cpuId()) {
302 panic("Local APICs can't be moved between CPUs"
303 " with different IDs.\n");
306 initialApicId
= cpu
->cpuId();
307 regs
[APIC_ID
] = (initialApicId
<< 24);
308 pioAddr
= x86LocalAPICAddress(initialApicId
, 0);
313 X86ISA::Interrupts::init()
316 // The local apic must register its address ranges on both its pio
317 // port via the basicpiodevice(piodevice) init() function and its
318 // int port that it inherited from IntDevice. Note IntDevice is
319 // not a SimObject itself.
321 BasicPioDevice::init();
324 // the slave port has a range so inform the connected master
325 intSlavePort
.sendRangeChange();
330 X86ISA::Interrupts::recvMessage(PacketPtr pkt
)
332 Addr offset
= pkt
->getAddr() - x86InterruptAddress(initialApicId
, 0);
333 assert(pkt
->cmd
== MemCmd::MessageReq
);
338 TriggerIntMessage message
= pkt
->get
<TriggerIntMessage
>();
340 "Got Trigger Interrupt message with vector %#x.\n",
343 requestInterrupt(message
.vector
,
344 message
.deliveryMode
, message
.trigger
);
348 panic("Local apic got unknown interrupt message at offset %#x.\n",
352 pkt
->makeAtomicResponse();
358 X86ISA::Interrupts::recvResponse(PacketPtr pkt
)
360 assert(!pkt
->isError());
361 assert(pkt
->cmd
== MemCmd::MessageResp
);
362 if (--pendingIPIs
== 0) {
363 InterruptCommandRegLow low
= regs
[APIC_INTERRUPT_COMMAND_LOW
];
364 // Record that the ICR is now idle.
365 low
.deliveryStatus
= 0;
366 regs
[APIC_INTERRUPT_COMMAND_LOW
] = low
;
368 DPRINTF(LocalApic
, "ICR is now idle.\n");
374 X86ISA::Interrupts::getIntAddrRange() const
376 AddrRangeList ranges
;
377 ranges
.push_back(RangeEx(x86InterruptAddress(initialApicId
, 0),
378 x86InterruptAddress(initialApicId
, 0) +
379 PhysAddrAPICRangeSize
));
385 X86ISA::Interrupts::readReg(ApicRegIndex reg
)
387 if (reg
>= APIC_TRIGGER_MODE(0) &&
388 reg
<= APIC_TRIGGER_MODE(15)) {
389 panic("Local APIC Trigger Mode registers are unimplemented.\n");
392 case APIC_ARBITRATION_PRIORITY
:
393 panic("Local APIC Arbitration Priority register unimplemented.\n");
395 case APIC_PROCESSOR_PRIORITY
:
396 panic("Local APIC Processor Priority register unimplemented.\n");
398 case APIC_ERROR_STATUS
:
399 regs
[APIC_INTERNAL_STATE
] &= ~ULL(0x1);
401 case APIC_CURRENT_COUNT
:
403 if (apicTimerEvent
.scheduled()) {
404 // Compute how many m5 ticks happen per count.
405 uint64_t ticksPerCount
= clockPeriod() *
406 divideFromConf(regs
[APIC_DIVIDE_CONFIGURATION
]);
407 // Compute how many m5 ticks are left.
408 uint64_t val
= apicTimerEvent
.when() - curTick();
409 // Turn that into a count.
410 val
= (val
+ ticksPerCount
- 1) / ticksPerCount
;
423 X86ISA::Interrupts::setReg(ApicRegIndex reg
, uint32_t val
)
425 uint32_t newVal
= val
;
426 if (reg
>= APIC_IN_SERVICE(0) &&
427 reg
<= APIC_IN_SERVICE(15)) {
428 panic("Local APIC In-Service registers are unimplemented.\n");
430 if (reg
>= APIC_TRIGGER_MODE(0) &&
431 reg
<= APIC_TRIGGER_MODE(15)) {
432 panic("Local APIC Trigger Mode registers are unimplemented.\n");
434 if (reg
>= APIC_INTERRUPT_REQUEST(0) &&
435 reg
<= APIC_INTERRUPT_REQUEST(15)) {
436 panic("Local APIC Interrupt Request registers "
437 "are unimplemented.\n");
444 // The Local APIC Version register is read only.
446 case APIC_TASK_PRIORITY
:
449 case APIC_ARBITRATION_PRIORITY
:
450 panic("Local APIC Arbitration Priority register unimplemented.\n");
452 case APIC_PROCESSOR_PRIORITY
:
453 panic("Local APIC Processor Priority register unimplemented.\n");
456 // Remove the interrupt that just completed from the local apic state.
457 clearRegArrayBit(APIC_IN_SERVICE_BASE
, ISRV
);
460 case APIC_LOGICAL_DESTINATION
:
461 newVal
= val
& 0xFF000000;
463 case APIC_DESTINATION_FORMAT
:
464 newVal
= val
| 0x0FFFFFFF;
466 case APIC_SPURIOUS_INTERRUPT_VECTOR
:
467 regs
[APIC_INTERNAL_STATE
] &= ~ULL(1 << 1);
468 regs
[APIC_INTERNAL_STATE
] |= val
& (1 << 8);
470 warn("Focus processor checking not implemented.\n");
472 case APIC_ERROR_STATUS
:
474 if (regs
[APIC_INTERNAL_STATE
] & 0x1) {
475 regs
[APIC_INTERNAL_STATE
] &= ~ULL(0x1);
478 regs
[APIC_INTERNAL_STATE
] |= ULL(0x1);
484 case APIC_INTERRUPT_COMMAND_LOW
:
486 InterruptCommandRegLow low
= regs
[APIC_INTERRUPT_COMMAND_LOW
];
487 // Check if we're already sending an IPI.
488 if (low
.deliveryStatus
) {
493 InterruptCommandRegHigh high
= regs
[APIC_INTERRUPT_COMMAND_HIGH
];
494 TriggerIntMessage message
= 0;
495 message
.destination
= high
.destination
;
496 message
.vector
= low
.vector
;
497 message
.deliveryMode
= low
.deliveryMode
;
498 message
.destMode
= low
.destMode
;
499 message
.level
= low
.level
;
500 message
.trigger
= low
.trigger
;
502 int numContexts
= sys
->numContexts();
503 switch (low
.destShorthand
) {
505 if (message
.deliveryMode
== DeliveryMode::LowestPriority
) {
506 panic("Lowest priority delivery mode "
507 "IPIs aren't implemented.\n");
509 if (message
.destMode
== 1) {
510 int dest
= message
.destination
;
511 hack_once("Assuming logical destinations are 1 << id.\n");
512 for (int i
= 0; i
< numContexts
; i
++) {
518 if (message
.destination
== 0xFF) {
519 for (int i
= 0; i
< numContexts
; i
++) {
520 if (i
== initialApicId
) {
521 requestInterrupt(message
.vector
,
522 message
.deliveryMode
, message
.trigger
);
528 if (message
.destination
== initialApicId
) {
529 requestInterrupt(message
.vector
,
530 message
.deliveryMode
, message
.trigger
);
532 apics
.push_back(message
.destination
);
539 requestInterrupt(message
.vector
,
540 message
.deliveryMode
, message
.trigger
);
543 requestInterrupt(message
.vector
,
544 message
.deliveryMode
, message
.trigger
);
548 for (int i
= 0; i
< numContexts
; i
++) {
549 if (i
!= initialApicId
) {
556 // Record that an IPI is being sent if one actually is.
558 low
.deliveryStatus
= 1;
559 pendingIPIs
+= apics
.size();
561 regs
[APIC_INTERRUPT_COMMAND_LOW
] = low
;
562 intMasterPort
.sendMessage(apics
, message
, sys
->isTimingMode());
563 newVal
= regs
[APIC_INTERRUPT_COMMAND_LOW
];
567 case APIC_LVT_THERMAL_SENSOR
:
568 case APIC_LVT_PERFORMANCE_MONITORING_COUNTERS
:
573 uint64_t readOnlyMask
= (1 << 12) | (1 << 14);
574 newVal
= (val
& ~readOnlyMask
) |
575 (regs
[reg
] & readOnlyMask
);
578 case APIC_INITIAL_COUNT
:
580 newVal
= bits(val
, 31, 0);
581 // Compute how many timer ticks we're being programmed for.
582 uint64_t newCount
= newVal
*
583 (divideFromConf(regs
[APIC_DIVIDE_CONFIGURATION
]));
584 // Schedule on the edge of the next tick plus the new count.
585 Tick offset
= curTick() % clockPeriod();
587 reschedule(apicTimerEvent
,
588 curTick() + (newCount
+ 1) *
589 clockPeriod() - offset
, true);
592 reschedule(apicTimerEvent
,
593 curTick() + newCount
*
594 clockPeriod(), true);
598 case APIC_CURRENT_COUNT
:
599 //Local APIC Current Count register is read only.
601 case APIC_DIVIDE_CONFIGURATION
:
612 X86ISA::Interrupts::Interrupts(Params
* p
)
613 : BasicPioDevice(p
, PageBytes
), IntDevice(this, p
->int_latency
),
614 apicTimerEvent(this),
615 pendingSmi(false), smiVector(0),
616 pendingNmi(false), nmiVector(0),
617 pendingExtInt(false), extIntVector(0),
618 pendingInit(false), initVector(0),
619 pendingStartup(false), startupVector(0),
620 startedUp(false), pendingUnmaskableInt(false),
621 pendingIPIs(0), cpu(NULL
),
622 intSlavePort(name() + ".int_slave", this, this)
624 memset(regs
, 0, sizeof(regs
));
625 //Set the local apic DFR to the flat model.
626 regs
[APIC_DESTINATION_FORMAT
] = (uint32_t)(-1);
633 X86ISA::Interrupts::checkInterrupts(ThreadContext
*tc
) const
635 RFLAGS rflags
= tc
->readMiscRegNoEffect(MISCREG_RFLAGS
);
636 if (pendingUnmaskableInt
) {
637 DPRINTF(LocalApic
, "Reported pending unmaskable interrupt.\n");
642 DPRINTF(LocalApic
, "Reported pending external interrupt.\n");
645 if (IRRV
> ISRV
&& bits(IRRV
, 7, 4) >
646 bits(regs
[APIC_TASK_PRIORITY
], 7, 4)) {
647 DPRINTF(LocalApic
, "Reported pending regular interrupt.\n");
655 X86ISA::Interrupts::checkInterruptsRaw() const
657 return pendingUnmaskableInt
|| pendingExtInt
||
658 (IRRV
> ISRV
&& bits(IRRV
, 7, 4) >
659 bits(regs
[APIC_TASK_PRIORITY
], 7, 4));
663 X86ISA::Interrupts::getInterrupt(ThreadContext
*tc
)
665 assert(checkInterrupts(tc
));
666 // These are all probably fairly uncommon, so we'll make them easier to
668 if (pendingUnmaskableInt
) {
670 DPRINTF(LocalApic
, "Generated SMI fault object.\n");
671 return std::make_shared
<SystemManagementInterrupt
>();
672 } else if (pendingNmi
) {
673 DPRINTF(LocalApic
, "Generated NMI fault object.\n");
674 return std::make_shared
<NonMaskableInterrupt
>(nmiVector
);
675 } else if (pendingInit
) {
676 DPRINTF(LocalApic
, "Generated INIT fault object.\n");
677 return std::make_shared
<InitInterrupt
>(initVector
);
678 } else if (pendingStartup
) {
679 DPRINTF(LocalApic
, "Generating SIPI fault object.\n");
680 return std::make_shared
<StartupInterrupt
>(startupVector
);
682 panic("pendingUnmaskableInt set, but no unmaskable "
683 "ints were pending.\n");
686 } else if (pendingExtInt
) {
687 DPRINTF(LocalApic
, "Generated external interrupt fault object.\n");
688 return std::make_shared
<ExternalInterrupt
>(extIntVector
);
690 DPRINTF(LocalApic
, "Generated regular interrupt fault object.\n");
691 // The only thing left are fixed and lowest priority interrupts.
692 return std::make_shared
<ExternalInterrupt
>(IRRV
);
697 X86ISA::Interrupts::updateIntrInfo(ThreadContext
*tc
)
699 assert(checkInterrupts(tc
));
700 if (pendingUnmaskableInt
) {
702 DPRINTF(LocalApic
, "SMI sent to core.\n");
704 } else if (pendingNmi
) {
705 DPRINTF(LocalApic
, "NMI sent to core.\n");
707 } else if (pendingInit
) {
708 DPRINTF(LocalApic
, "Init sent to core.\n");
711 } else if (pendingStartup
) {
712 DPRINTF(LocalApic
, "SIPI sent to core.\n");
713 pendingStartup
= false;
716 if (!(pendingSmi
|| pendingNmi
|| pendingInit
|| pendingStartup
))
717 pendingUnmaskableInt
= false;
718 } else if (pendingExtInt
) {
719 pendingExtInt
= false;
721 DPRINTF(LocalApic
, "Interrupt %d sent to core.\n", IRRV
);
722 // Mark the interrupt as "in service".
724 setRegArrayBit(APIC_IN_SERVICE_BASE
, ISRV
);
725 // Clear it out of the IRR.
726 clearRegArrayBit(APIC_INTERRUPT_REQUEST_BASE
, IRRV
);
732 X86ISA::Interrupts::serialize(std::ostream
&os
)
734 SERIALIZE_ARRAY(regs
, NUM_APIC_REGS
);
735 SERIALIZE_SCALAR(pendingSmi
);
736 SERIALIZE_SCALAR(smiVector
);
737 SERIALIZE_SCALAR(pendingNmi
);
738 SERIALIZE_SCALAR(nmiVector
);
739 SERIALIZE_SCALAR(pendingExtInt
);
740 SERIALIZE_SCALAR(extIntVector
);
741 SERIALIZE_SCALAR(pendingInit
);
742 SERIALIZE_SCALAR(initVector
);
743 SERIALIZE_SCALAR(pendingStartup
);
744 SERIALIZE_SCALAR(startupVector
);
745 SERIALIZE_SCALAR(startedUp
);
746 SERIALIZE_SCALAR(pendingUnmaskableInt
);
747 SERIALIZE_SCALAR(pendingIPIs
);
748 SERIALIZE_SCALAR(IRRV
);
749 SERIALIZE_SCALAR(ISRV
);
750 bool apicTimerEventScheduled
= apicTimerEvent
.scheduled();
751 SERIALIZE_SCALAR(apicTimerEventScheduled
);
752 Tick apicTimerEventTick
= apicTimerEvent
.when();
753 SERIALIZE_SCALAR(apicTimerEventTick
);
757 X86ISA::Interrupts::unserialize(Checkpoint
*cp
, const std::string
§ion
)
759 UNSERIALIZE_ARRAY(regs
, NUM_APIC_REGS
);
760 UNSERIALIZE_SCALAR(pendingSmi
);
761 UNSERIALIZE_SCALAR(smiVector
);
762 UNSERIALIZE_SCALAR(pendingNmi
);
763 UNSERIALIZE_SCALAR(nmiVector
);
764 UNSERIALIZE_SCALAR(pendingExtInt
);
765 UNSERIALIZE_SCALAR(extIntVector
);
766 UNSERIALIZE_SCALAR(pendingInit
);
767 UNSERIALIZE_SCALAR(initVector
);
768 UNSERIALIZE_SCALAR(pendingStartup
);
769 UNSERIALIZE_SCALAR(startupVector
);
770 UNSERIALIZE_SCALAR(startedUp
);
771 UNSERIALIZE_SCALAR(pendingUnmaskableInt
);
772 UNSERIALIZE_SCALAR(pendingIPIs
);
773 UNSERIALIZE_SCALAR(IRRV
);
774 UNSERIALIZE_SCALAR(ISRV
);
775 bool apicTimerEventScheduled
;
776 UNSERIALIZE_SCALAR(apicTimerEventScheduled
);
777 if (apicTimerEventScheduled
) {
778 Tick apicTimerEventTick
;
779 UNSERIALIZE_SCALAR(apicTimerEventTick
);
780 if (apicTimerEvent
.scheduled()) {
781 reschedule(apicTimerEvent
, apicTimerEventTick
, true);
783 schedule(apicTimerEvent
, apicTimerEventTick
);
789 X86LocalApicParams::create()
791 return new X86ISA::Interrupts(this);