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58 #include "arch/x86/apicregs.hh"
59 #include "arch/x86/interrupts.hh"
60 #include "arch/x86/intmessage.hh"
61 #include "cpu/base.hh"
62 #include "dev/x86/i82094aa.hh"
63 #include "dev/x86/pc.hh"
64 #include "dev/x86/south_bridge.hh"
65 #include "mem/packet_access.hh"
66 #include "sim/system.hh"
69 divideFromConf(uint32_t conf
)
71 // This figures out what division we want from the division configuration
72 // register in the local APIC. The encoding is a little odd but it can
73 // be deciphered fairly easily.
74 int shift
= ((conf
& 0x8) >> 1) | (conf
& 0x3);
75 shift
= (shift
+ 1) % 8;
83 decodeAddr(Addr paddr
)
93 regNum
= APIC_VERSION
;
96 regNum
= APIC_TASK_PRIORITY
;
99 regNum
= APIC_ARBITRATION_PRIORITY
;
102 regNum
= APIC_PROCESSOR_PRIORITY
;
108 regNum
= APIC_LOGICAL_DESTINATION
;
111 regNum
= APIC_DESTINATION_FORMAT
;
114 regNum
= APIC_SPURIOUS_INTERRUPT_VECTOR
;
132 regNum
= APIC_IN_SERVICE((paddr
- 0x100) / 0x8);
150 regNum
= APIC_TRIGGER_MODE((paddr
- 0x180) / 0x8);
168 regNum
= APIC_INTERRUPT_REQUEST((paddr
- 0x200) / 0x8);
171 regNum
= APIC_ERROR_STATUS
;
174 regNum
= APIC_INTERRUPT_COMMAND_LOW
;
177 regNum
= APIC_INTERRUPT_COMMAND_HIGH
;
180 regNum
= APIC_LVT_TIMER
;
183 regNum
= APIC_LVT_THERMAL_SENSOR
;
186 regNum
= APIC_LVT_PERFORMANCE_MONITORING_COUNTERS
;
189 regNum
= APIC_LVT_LINT0
;
192 regNum
= APIC_LVT_LINT1
;
195 regNum
= APIC_LVT_ERROR
;
198 regNum
= APIC_INITIAL_COUNT
;
201 regNum
= APIC_CURRENT_COUNT
;
204 regNum
= APIC_DIVIDE_CONFIGURATION
;
207 // A reserved register field.
208 panic("Accessed reserved register field %#x.\n", paddr
);
216 X86ISA::Interrupts::read(PacketPtr pkt
)
218 Addr offset
= pkt
->getAddr() - pioAddr
;
219 //Make sure we're at least only accessing one register.
220 if ((offset
& ~mask(3)) != ((offset
+ pkt
->getSize()) & ~mask(3)))
221 panic("Accessed more than one register at a time in the APIC!\n");
222 ApicRegIndex reg
= decodeAddr(offset
);
223 uint32_t val
= htog(readReg(reg
));
225 "Reading Local APIC register %d at offset %#x as %#x.\n",
227 pkt
->setData(((uint8_t *)&val
) + (offset
& mask(3)));
228 pkt
->makeAtomicResponse();
233 X86ISA::Interrupts::write(PacketPtr pkt
)
235 Addr offset
= pkt
->getAddr() - pioAddr
;
236 //Make sure we're at least only accessing one register.
237 if ((offset
& ~mask(3)) != ((offset
+ pkt
->getSize()) & ~mask(3)))
238 panic("Accessed more than one register at a time in the APIC!\n");
239 ApicRegIndex reg
= decodeAddr(offset
);
240 uint32_t val
= regs
[reg
];
241 pkt
->writeData(((uint8_t *)&val
) + (offset
& mask(3)));
243 "Writing Local APIC register %d at offset %#x as %#x.\n",
244 reg
, offset
, gtoh(val
));
245 setReg(reg
, gtoh(val
));
246 pkt
->makeAtomicResponse();
250 X86ISA::Interrupts::requestInterrupt(uint8_t vector
,
251 uint8_t deliveryMode
, bool level
)
254 * Fixed and lowest-priority delivery mode interrupts are handled
255 * using the IRR/ISR registers, checking against the TPR, etc.
256 * The SMI, NMI, ExtInt, INIT, etc interrupts go straight through.
258 if (deliveryMode
== DeliveryMode::Fixed
||
259 deliveryMode
== DeliveryMode::LowestPriority
) {
260 DPRINTF(LocalApic
, "Interrupt is an %s.\n",
261 DeliveryMode::names
[deliveryMode
]);
262 // Queue up the interrupt in the IRR.
265 if (!getRegArrayBit(APIC_INTERRUPT_REQUEST_BASE
, vector
)) {
266 setRegArrayBit(APIC_INTERRUPT_REQUEST_BASE
, vector
);
268 setRegArrayBit(APIC_TRIGGER_MODE_BASE
, vector
);
270 clearRegArrayBit(APIC_TRIGGER_MODE_BASE
, vector
);
273 } else if (!DeliveryMode::isReserved(deliveryMode
)) {
274 DPRINTF(LocalApic
, "Interrupt is an %s.\n",
275 DeliveryMode::names
[deliveryMode
]);
276 if (deliveryMode
== DeliveryMode::SMI
&& !pendingSmi
) {
277 pendingUnmaskableInt
= pendingSmi
= true;
279 } else if (deliveryMode
== DeliveryMode::NMI
&& !pendingNmi
) {
280 pendingUnmaskableInt
= pendingNmi
= true;
282 } else if (deliveryMode
== DeliveryMode::ExtInt
&& !pendingExtInt
) {
283 pendingExtInt
= true;
284 extIntVector
= vector
;
285 } else if (deliveryMode
== DeliveryMode::INIT
&& !pendingInit
) {
286 pendingUnmaskableInt
= pendingInit
= true;
288 } else if (deliveryMode
== DeliveryMode::SIPI
&&
289 !pendingStartup
&& !startedUp
) {
290 pendingUnmaskableInt
= pendingStartup
= true;
291 startupVector
= vector
;
299 X86ISA::Interrupts::setCPU(BaseCPU
* newCPU
)
302 if (cpu
!= NULL
&& cpu
->cpuId() != newCPU
->cpuId()) {
303 panic("Local APICs can't be moved between CPUs"
304 " with different IDs.\n");
307 initialApicId
= cpu
->cpuId();
308 regs
[APIC_ID
] = (initialApicId
<< 24);
313 X86ISA::Interrupts::init()
315 BasicPioDevice::init();
316 Pc
* pc
= dynamic_cast<Pc
*>(platform
);
318 pc
->southBridge
->ioApic
->registerLocalApic(initialApicId
, this);
323 X86ISA::Interrupts::recvMessage(PacketPtr pkt
)
325 Addr offset
= pkt
->getAddr() - x86InterruptAddress(initialApicId
, 0);
326 assert(pkt
->cmd
== MemCmd::MessageReq
);
331 TriggerIntMessage message
= pkt
->get
<TriggerIntMessage
>();
333 "Got Trigger Interrupt message with vector %#x.\n",
336 requestInterrupt(message
.vector
,
337 message
.deliveryMode
, message
.trigger
);
341 panic("Local apic got unknown interrupt message at offset %#x.\n",
345 pkt
->makeAtomicResponse();
351 X86ISA::Interrupts::recvResponse(PacketPtr pkt
)
353 assert(!pkt
->isError());
354 assert(pkt
->cmd
== MemCmd::MessageResp
);
355 if (--pendingIPIs
== 0) {
356 InterruptCommandRegLow low
= regs
[APIC_INTERRUPT_COMMAND_LOW
];
357 // Record that the ICR is now idle.
358 low
.deliveryStatus
= 0;
359 regs
[APIC_INTERRUPT_COMMAND_LOW
] = low
;
363 DPRINTF(LocalApic
, "ICR is now idle.\n");
369 X86ISA::Interrupts::addressRanges(AddrRangeList
&range_list
)
372 Range
<Addr
> range
= RangeEx(x86LocalAPICAddress(initialApicId
, 0),
373 x86LocalAPICAddress(initialApicId
, 0) +
375 range_list
.push_back(range
);
376 pioAddr
= range
.start
;
381 X86ISA::Interrupts::getIntAddrRange(AddrRangeList
&range_list
)
384 range_list
.push_back(RangeEx(x86InterruptAddress(initialApicId
, 0),
385 x86InterruptAddress(initialApicId
, 0) +
386 PhysAddrAPICRangeSize
));
391 X86ISA::Interrupts::readReg(ApicRegIndex reg
)
393 if (reg
>= APIC_TRIGGER_MODE(0) &&
394 reg
<= APIC_TRIGGER_MODE(15)) {
395 panic("Local APIC Trigger Mode registers are unimplemented.\n");
398 case APIC_ARBITRATION_PRIORITY
:
399 panic("Local APIC Arbitration Priority register unimplemented.\n");
401 case APIC_PROCESSOR_PRIORITY
:
402 panic("Local APIC Processor Priority register unimplemented.\n");
404 case APIC_ERROR_STATUS
:
405 regs
[APIC_INTERNAL_STATE
] &= ~ULL(0x1);
407 case APIC_CURRENT_COUNT
:
409 if (apicTimerEvent
.scheduled()) {
411 // Compute how many m5 ticks happen per count.
412 uint64_t ticksPerCount
= clock
*
413 divideFromConf(regs
[APIC_DIVIDE_CONFIGURATION
]);
414 // Compute how many m5 ticks are left.
415 uint64_t val
= apicTimerEvent
.when() - curTick
;
416 // Turn that into a count.
417 val
= (val
+ ticksPerCount
- 1) / ticksPerCount
;
430 X86ISA::Interrupts::setReg(ApicRegIndex reg
, uint32_t val
)
432 uint32_t newVal
= val
;
433 if (reg
>= APIC_IN_SERVICE(0) &&
434 reg
<= APIC_IN_SERVICE(15)) {
435 panic("Local APIC In-Service registers are unimplemented.\n");
437 if (reg
>= APIC_TRIGGER_MODE(0) &&
438 reg
<= APIC_TRIGGER_MODE(15)) {
439 panic("Local APIC Trigger Mode registers are unimplemented.\n");
441 if (reg
>= APIC_INTERRUPT_REQUEST(0) &&
442 reg
<= APIC_INTERRUPT_REQUEST(15)) {
443 panic("Local APIC Interrupt Request registers "
444 "are unimplemented.\n");
451 // The Local APIC Version register is read only.
453 case APIC_TASK_PRIORITY
:
456 case APIC_ARBITRATION_PRIORITY
:
457 panic("Local APIC Arbitration Priority register unimplemented.\n");
459 case APIC_PROCESSOR_PRIORITY
:
460 panic("Local APIC Processor Priority register unimplemented.\n");
463 // Remove the interrupt that just completed from the local apic state.
464 clearRegArrayBit(APIC_IN_SERVICE_BASE
, ISRV
);
467 case APIC_LOGICAL_DESTINATION
:
468 newVal
= val
& 0xFF000000;
470 case APIC_DESTINATION_FORMAT
:
471 newVal
= val
| 0x0FFFFFFF;
473 case APIC_SPURIOUS_INTERRUPT_VECTOR
:
474 regs
[APIC_INTERNAL_STATE
] &= ~ULL(1 << 1);
475 regs
[APIC_INTERNAL_STATE
] |= val
& (1 << 8);
477 warn("Focus processor checking not implemented.\n");
479 case APIC_ERROR_STATUS
:
481 if (regs
[APIC_INTERNAL_STATE
] & 0x1) {
482 regs
[APIC_INTERNAL_STATE
] &= ~ULL(0x1);
485 regs
[APIC_INTERNAL_STATE
] |= ULL(0x1);
491 case APIC_INTERRUPT_COMMAND_LOW
:
493 InterruptCommandRegLow low
= regs
[APIC_INTERRUPT_COMMAND_LOW
];
494 // Check if we're already sending an IPI.
495 if (low
.deliveryStatus
) {
500 InterruptCommandRegHigh high
= regs
[APIC_INTERRUPT_COMMAND_HIGH
];
501 // Record that an IPI is being sent.
502 low
.deliveryStatus
= 1;
503 TriggerIntMessage message
= 0;
504 message
.destination
= high
.destination
;
505 message
.vector
= low
.vector
;
506 message
.deliveryMode
= low
.deliveryMode
;
507 message
.destMode
= low
.destMode
;
508 message
.level
= low
.level
;
509 message
.trigger
= low
.trigger
;
510 bool timing
= sys
->getMemoryMode() == Enums::timing
;
511 // Be careful no updates of the delivery status bit get lost.
512 regs
[APIC_INTERRUPT_COMMAND_LOW
] = low
;
514 int numContexts
= sys
->numContexts();
515 switch (low
.destShorthand
) {
517 if (message
.deliveryMode
== DeliveryMode::LowestPriority
) {
518 panic("Lowest priority delivery mode "
519 "IPIs aren't implemented.\n");
521 if (message
.destMode
== 1) {
522 int dest
= message
.destination
;
523 hack_once("Assuming logical destinations are 1 << id.\n");
524 for (int i
= 0; i
< numContexts
; i
++) {
530 if (message
.destination
== 0xFF) {
531 for (int i
= 0; i
< numContexts
; i
++) {
532 if (i
== initialApicId
) {
533 requestInterrupt(message
.vector
,
534 message
.deliveryMode
, message
.trigger
);
540 if (message
.destination
== initialApicId
) {
541 requestInterrupt(message
.vector
,
542 message
.deliveryMode
, message
.trigger
);
544 apics
.push_back(message
.destination
);
551 requestInterrupt(message
.vector
,
552 message
.deliveryMode
, message
.trigger
);
555 requestInterrupt(message
.vector
,
556 message
.deliveryMode
, message
.trigger
);
560 for (int i
= 0; i
< numContexts
; i
++) {
561 if (i
!= initialApicId
) {
568 pendingIPIs
+= apics
.size();
569 intPort
->sendMessage(apics
, message
, timing
);
570 newVal
= regs
[APIC_INTERRUPT_COMMAND_LOW
];
574 case APIC_LVT_THERMAL_SENSOR
:
575 case APIC_LVT_PERFORMANCE_MONITORING_COUNTERS
:
580 uint64_t readOnlyMask
= (1 << 12) | (1 << 14);
581 newVal
= (val
& ~readOnlyMask
) |
582 (regs
[reg
] & readOnlyMask
);
585 case APIC_INITIAL_COUNT
:
588 newVal
= bits(val
, 31, 0);
589 // Compute how many timer ticks we're being programmed for.
590 uint64_t newCount
= newVal
*
591 (divideFromConf(regs
[APIC_DIVIDE_CONFIGURATION
]));
592 // Schedule on the edge of the next tick plus the new count.
593 Tick offset
= curTick
% clock
;
595 reschedule(apicTimerEvent
,
596 curTick
+ (newCount
+ 1) * clock
- offset
, true);
598 reschedule(apicTimerEvent
,
599 curTick
+ newCount
* clock
, true);
603 case APIC_CURRENT_COUNT
:
604 //Local APIC Current Count register is read only.
606 case APIC_DIVIDE_CONFIGURATION
:
617 X86ISA::Interrupts::Interrupts(Params
* p
) :
618 BasicPioDevice(p
), IntDev(this), latency(p
->pio_latency
), clock(0),
619 apicTimerEvent(this),
620 pendingSmi(false), smiVector(0),
621 pendingNmi(false), nmiVector(0),
622 pendingExtInt(false), extIntVector(0),
623 pendingInit(false), initVector(0),
624 pendingStartup(false), startupVector(0),
625 startedUp(false), pendingUnmaskableInt(false),
626 pendingIPIs(0), cpu(NULL
)
629 memset(regs
, 0, sizeof(regs
));
630 //Set the local apic DFR to the flat model.
631 regs
[APIC_DESTINATION_FORMAT
] = (uint32_t)(-1);
638 X86ISA::Interrupts::checkInterrupts(ThreadContext
*tc
) const
640 RFLAGS rflags
= tc
->readMiscRegNoEffect(MISCREG_RFLAGS
);
641 if (pendingUnmaskableInt
) {
642 DPRINTF(LocalApic
, "Reported pending unmaskable interrupt.\n");
647 DPRINTF(LocalApic
, "Reported pending external interrupt.\n");
650 if (IRRV
> ISRV
&& bits(IRRV
, 7, 4) >
651 bits(regs
[APIC_TASK_PRIORITY
], 7, 4)) {
652 DPRINTF(LocalApic
, "Reported pending regular interrupt.\n");
660 X86ISA::Interrupts::getInterrupt(ThreadContext
*tc
)
662 assert(checkInterrupts(tc
));
663 // These are all probably fairly uncommon, so we'll make them easier to
665 if (pendingUnmaskableInt
) {
667 DPRINTF(LocalApic
, "Generated SMI fault object.\n");
668 return new SystemManagementInterrupt();
669 } else if (pendingNmi
) {
670 DPRINTF(LocalApic
, "Generated NMI fault object.\n");
671 return new NonMaskableInterrupt(nmiVector
);
672 } else if (pendingInit
) {
673 DPRINTF(LocalApic
, "Generated INIT fault object.\n");
674 return new InitInterrupt(initVector
);
675 } else if (pendingStartup
) {
676 DPRINTF(LocalApic
, "Generating SIPI fault object.\n");
677 return new StartupInterrupt(startupVector
);
679 panic("pendingUnmaskableInt set, but no unmaskable "
680 "ints were pending.\n");
683 } else if (pendingExtInt
) {
684 DPRINTF(LocalApic
, "Generated external interrupt fault object.\n");
685 return new ExternalInterrupt(extIntVector
);
687 DPRINTF(LocalApic
, "Generated regular interrupt fault object.\n");
688 // The only thing left are fixed and lowest priority interrupts.
689 return new ExternalInterrupt(IRRV
);
694 X86ISA::Interrupts::updateIntrInfo(ThreadContext
*tc
)
696 assert(checkInterrupts(tc
));
697 if (pendingUnmaskableInt
) {
699 DPRINTF(LocalApic
, "SMI sent to core.\n");
701 } else if (pendingNmi
) {
702 DPRINTF(LocalApic
, "NMI sent to core.\n");
704 } else if (pendingInit
) {
705 DPRINTF(LocalApic
, "Init sent to core.\n");
708 } else if (pendingStartup
) {
709 DPRINTF(LocalApic
, "SIPI sent to core.\n");
710 pendingStartup
= false;
713 if (!(pendingSmi
|| pendingNmi
|| pendingInit
|| pendingStartup
))
714 pendingUnmaskableInt
= false;
715 } else if (pendingExtInt
) {
716 pendingExtInt
= false;
718 DPRINTF(LocalApic
, "Interrupt %d sent to core.\n", IRRV
);
719 // Mark the interrupt as "in service".
721 setRegArrayBit(APIC_IN_SERVICE_BASE
, ISRV
);
722 // Clear it out of the IRR.
723 clearRegArrayBit(APIC_INTERRUPT_REQUEST_BASE
, IRRV
);
729 X86LocalApicParams::create()
731 return new X86ISA::Interrupts(this);