2 * Copyright (c) 2008 The Hewlett-Packard Development Company
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
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21 * neither the name of the copyright holders nor the names of its
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23 * this software without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 #include "arch/x86/regs/apic.hh"
41 #include "arch/x86/interrupts.hh"
42 #include "arch/x86/intmessage.hh"
43 #include "cpu/base.hh"
44 #include "debug/LocalApic.hh"
45 #include "dev/x86/i82094aa.hh"
46 #include "dev/x86/pc.hh"
47 #include "dev/x86/south_bridge.hh"
48 #include "mem/packet_access.hh"
49 #include "sim/system.hh"
50 #include "sim/full_system.hh"
53 divideFromConf(uint32_t conf
)
55 // This figures out what division we want from the division configuration
56 // register in the local APIC. The encoding is a little odd but it can
57 // be deciphered fairly easily.
58 int shift
= ((conf
& 0x8) >> 1) | (conf
& 0x3);
59 shift
= (shift
+ 1) % 8;
67 decodeAddr(Addr paddr
)
77 regNum
= APIC_VERSION
;
80 regNum
= APIC_TASK_PRIORITY
;
83 regNum
= APIC_ARBITRATION_PRIORITY
;
86 regNum
= APIC_PROCESSOR_PRIORITY
;
92 regNum
= APIC_LOGICAL_DESTINATION
;
95 regNum
= APIC_DESTINATION_FORMAT
;
98 regNum
= APIC_SPURIOUS_INTERRUPT_VECTOR
;
116 regNum
= APIC_IN_SERVICE((paddr
- 0x100) / 0x8);
134 regNum
= APIC_TRIGGER_MODE((paddr
- 0x180) / 0x8);
152 regNum
= APIC_INTERRUPT_REQUEST((paddr
- 0x200) / 0x8);
155 regNum
= APIC_ERROR_STATUS
;
158 regNum
= APIC_INTERRUPT_COMMAND_LOW
;
161 regNum
= APIC_INTERRUPT_COMMAND_HIGH
;
164 regNum
= APIC_LVT_TIMER
;
167 regNum
= APIC_LVT_THERMAL_SENSOR
;
170 regNum
= APIC_LVT_PERFORMANCE_MONITORING_COUNTERS
;
173 regNum
= APIC_LVT_LINT0
;
176 regNum
= APIC_LVT_LINT1
;
179 regNum
= APIC_LVT_ERROR
;
182 regNum
= APIC_INITIAL_COUNT
;
185 regNum
= APIC_CURRENT_COUNT
;
188 regNum
= APIC_DIVIDE_CONFIGURATION
;
191 // A reserved register field.
192 panic("Accessed reserved register field %#x.\n", paddr
);
200 X86ISA::Interrupts::read(PacketPtr pkt
)
202 Addr offset
= pkt
->getAddr() - pioAddr
;
203 //Make sure we're at least only accessing one register.
204 if ((offset
& ~mask(3)) != ((offset
+ pkt
->getSize()) & ~mask(3)))
205 panic("Accessed more than one register at a time in the APIC!\n");
206 ApicRegIndex reg
= decodeAddr(offset
);
207 uint32_t val
= htog(readReg(reg
));
209 "Reading Local APIC register %d at offset %#x as %#x.\n",
211 pkt
->setData(((uint8_t *)&val
) + (offset
& mask(3)));
212 pkt
->makeAtomicResponse();
217 X86ISA::Interrupts::write(PacketPtr pkt
)
219 Addr offset
= pkt
->getAddr() - pioAddr
;
220 //Make sure we're at least only accessing one register.
221 if ((offset
& ~mask(3)) != ((offset
+ pkt
->getSize()) & ~mask(3)))
222 panic("Accessed more than one register at a time in the APIC!\n");
223 ApicRegIndex reg
= decodeAddr(offset
);
224 uint32_t val
= regs
[reg
];
225 pkt
->writeData(((uint8_t *)&val
) + (offset
& mask(3)));
227 "Writing Local APIC register %d at offset %#x as %#x.\n",
228 reg
, offset
, gtoh(val
));
229 setReg(reg
, gtoh(val
));
230 pkt
->makeAtomicResponse();
234 X86ISA::Interrupts::requestInterrupt(uint8_t vector
,
235 uint8_t deliveryMode
, bool level
)
238 * Fixed and lowest-priority delivery mode interrupts are handled
239 * using the IRR/ISR registers, checking against the TPR, etc.
240 * The SMI, NMI, ExtInt, INIT, etc interrupts go straight through.
242 if (deliveryMode
== DeliveryMode::Fixed
||
243 deliveryMode
== DeliveryMode::LowestPriority
) {
244 DPRINTF(LocalApic
, "Interrupt is an %s.\n",
245 DeliveryMode::names
[deliveryMode
]);
246 // Queue up the interrupt in the IRR.
249 if (!getRegArrayBit(APIC_INTERRUPT_REQUEST_BASE
, vector
)) {
250 setRegArrayBit(APIC_INTERRUPT_REQUEST_BASE
, vector
);
252 setRegArrayBit(APIC_TRIGGER_MODE_BASE
, vector
);
254 clearRegArrayBit(APIC_TRIGGER_MODE_BASE
, vector
);
257 } else if (!DeliveryMode::isReserved(deliveryMode
)) {
258 DPRINTF(LocalApic
, "Interrupt is an %s.\n",
259 DeliveryMode::names
[deliveryMode
]);
260 if (deliveryMode
== DeliveryMode::SMI
&& !pendingSmi
) {
261 pendingUnmaskableInt
= pendingSmi
= true;
263 } else if (deliveryMode
== DeliveryMode::NMI
&& !pendingNmi
) {
264 pendingUnmaskableInt
= pendingNmi
= true;
266 } else if (deliveryMode
== DeliveryMode::ExtInt
&& !pendingExtInt
) {
267 pendingExtInt
= true;
268 extIntVector
= vector
;
269 } else if (deliveryMode
== DeliveryMode::INIT
&& !pendingInit
) {
270 pendingUnmaskableInt
= pendingInit
= true;
272 } else if (deliveryMode
== DeliveryMode::SIPI
&&
273 !pendingStartup
&& !startedUp
) {
274 pendingUnmaskableInt
= pendingStartup
= true;
275 startupVector
= vector
;
284 X86ISA::Interrupts::setCPU(BaseCPU
* newCPU
)
287 if (cpu
!= NULL
&& cpu
->cpuId() != newCPU
->cpuId()) {
288 panic("Local APICs can't be moved between CPUs"
289 " with different IDs.\n");
292 initialApicId
= cpu
->cpuId();
293 regs
[APIC_ID
] = (initialApicId
<< 24);
298 X86ISA::Interrupts::init()
301 // The local apic must register its address ranges on both its pio port
302 // via the basicpiodevice(piodevice) init() function and its int port
303 // that it inherited from IntDev. Note IntDev is not a SimObject itself.
305 BasicPioDevice::init();
311 X86ISA::Interrupts::recvMessage(PacketPtr pkt
)
313 Addr offset
= pkt
->getAddr() - x86InterruptAddress(initialApicId
, 0);
314 assert(pkt
->cmd
== MemCmd::MessageReq
);
319 TriggerIntMessage message
= pkt
->get
<TriggerIntMessage
>();
321 "Got Trigger Interrupt message with vector %#x.\n",
324 requestInterrupt(message
.vector
,
325 message
.deliveryMode
, message
.trigger
);
329 panic("Local apic got unknown interrupt message at offset %#x.\n",
333 pkt
->makeAtomicResponse();
339 X86ISA::Interrupts::recvResponse(PacketPtr pkt
)
341 assert(!pkt
->isError());
342 assert(pkt
->cmd
== MemCmd::MessageResp
);
343 if (--pendingIPIs
== 0) {
344 InterruptCommandRegLow low
= regs
[APIC_INTERRUPT_COMMAND_LOW
];
345 // Record that the ICR is now idle.
346 low
.deliveryStatus
= 0;
347 regs
[APIC_INTERRUPT_COMMAND_LOW
] = low
;
349 DPRINTF(LocalApic
, "ICR is now idle.\n");
355 X86ISA::Interrupts::addressRanges(AddrRangeList
&range_list
)
358 Range
<Addr
> range
= RangeEx(x86LocalAPICAddress(initialApicId
, 0),
359 x86LocalAPICAddress(initialApicId
, 0) +
361 range_list
.push_back(range
);
362 pioAddr
= range
.start
;
367 X86ISA::Interrupts::getIntAddrRange(AddrRangeList
&range_list
)
370 range_list
.push_back(RangeEx(x86InterruptAddress(initialApicId
, 0),
371 x86InterruptAddress(initialApicId
, 0) +
372 PhysAddrAPICRangeSize
));
377 X86ISA::Interrupts::readReg(ApicRegIndex reg
)
379 if (reg
>= APIC_TRIGGER_MODE(0) &&
380 reg
<= APIC_TRIGGER_MODE(15)) {
381 panic("Local APIC Trigger Mode registers are unimplemented.\n");
384 case APIC_ARBITRATION_PRIORITY
:
385 panic("Local APIC Arbitration Priority register unimplemented.\n");
387 case APIC_PROCESSOR_PRIORITY
:
388 panic("Local APIC Processor Priority register unimplemented.\n");
390 case APIC_ERROR_STATUS
:
391 regs
[APIC_INTERNAL_STATE
] &= ~ULL(0x1);
393 case APIC_CURRENT_COUNT
:
395 if (apicTimerEvent
.scheduled()) {
397 // Compute how many m5 ticks happen per count.
398 uint64_t ticksPerCount
= clock
*
399 divideFromConf(regs
[APIC_DIVIDE_CONFIGURATION
]);
400 // Compute how many m5 ticks are left.
401 uint64_t val
= apicTimerEvent
.when() - curTick();
402 // Turn that into a count.
403 val
= (val
+ ticksPerCount
- 1) / ticksPerCount
;
416 X86ISA::Interrupts::setReg(ApicRegIndex reg
, uint32_t val
)
418 uint32_t newVal
= val
;
419 if (reg
>= APIC_IN_SERVICE(0) &&
420 reg
<= APIC_IN_SERVICE(15)) {
421 panic("Local APIC In-Service registers are unimplemented.\n");
423 if (reg
>= APIC_TRIGGER_MODE(0) &&
424 reg
<= APIC_TRIGGER_MODE(15)) {
425 panic("Local APIC Trigger Mode registers are unimplemented.\n");
427 if (reg
>= APIC_INTERRUPT_REQUEST(0) &&
428 reg
<= APIC_INTERRUPT_REQUEST(15)) {
429 panic("Local APIC Interrupt Request registers "
430 "are unimplemented.\n");
437 // The Local APIC Version register is read only.
439 case APIC_TASK_PRIORITY
:
442 case APIC_ARBITRATION_PRIORITY
:
443 panic("Local APIC Arbitration Priority register unimplemented.\n");
445 case APIC_PROCESSOR_PRIORITY
:
446 panic("Local APIC Processor Priority register unimplemented.\n");
449 // Remove the interrupt that just completed from the local apic state.
450 clearRegArrayBit(APIC_IN_SERVICE_BASE
, ISRV
);
453 case APIC_LOGICAL_DESTINATION
:
454 newVal
= val
& 0xFF000000;
456 case APIC_DESTINATION_FORMAT
:
457 newVal
= val
| 0x0FFFFFFF;
459 case APIC_SPURIOUS_INTERRUPT_VECTOR
:
460 regs
[APIC_INTERNAL_STATE
] &= ~ULL(1 << 1);
461 regs
[APIC_INTERNAL_STATE
] |= val
& (1 << 8);
463 warn("Focus processor checking not implemented.\n");
465 case APIC_ERROR_STATUS
:
467 if (regs
[APIC_INTERNAL_STATE
] & 0x1) {
468 regs
[APIC_INTERNAL_STATE
] &= ~ULL(0x1);
471 regs
[APIC_INTERNAL_STATE
] |= ULL(0x1);
477 case APIC_INTERRUPT_COMMAND_LOW
:
479 InterruptCommandRegLow low
= regs
[APIC_INTERRUPT_COMMAND_LOW
];
480 // Check if we're already sending an IPI.
481 if (low
.deliveryStatus
) {
486 InterruptCommandRegHigh high
= regs
[APIC_INTERRUPT_COMMAND_HIGH
];
487 // Record that an IPI is being sent.
488 low
.deliveryStatus
= 1;
489 TriggerIntMessage message
= 0;
490 message
.destination
= high
.destination
;
491 message
.vector
= low
.vector
;
492 message
.deliveryMode
= low
.deliveryMode
;
493 message
.destMode
= low
.destMode
;
494 message
.level
= low
.level
;
495 message
.trigger
= low
.trigger
;
496 bool timing
= sys
->getMemoryMode() == Enums::timing
;
497 // Be careful no updates of the delivery status bit get lost.
498 regs
[APIC_INTERRUPT_COMMAND_LOW
] = low
;
500 int numContexts
= sys
->numContexts();
501 switch (low
.destShorthand
) {
503 if (message
.deliveryMode
== DeliveryMode::LowestPriority
) {
504 panic("Lowest priority delivery mode "
505 "IPIs aren't implemented.\n");
507 if (message
.destMode
== 1) {
508 int dest
= message
.destination
;
509 hack_once("Assuming logical destinations are 1 << id.\n");
510 for (int i
= 0; i
< numContexts
; i
++) {
516 if (message
.destination
== 0xFF) {
517 for (int i
= 0; i
< numContexts
; i
++) {
518 if (i
== initialApicId
) {
519 requestInterrupt(message
.vector
,
520 message
.deliveryMode
, message
.trigger
);
526 if (message
.destination
== initialApicId
) {
527 requestInterrupt(message
.vector
,
528 message
.deliveryMode
, message
.trigger
);
530 apics
.push_back(message
.destination
);
537 requestInterrupt(message
.vector
,
538 message
.deliveryMode
, message
.trigger
);
541 requestInterrupt(message
.vector
,
542 message
.deliveryMode
, message
.trigger
);
546 for (int i
= 0; i
< numContexts
; i
++) {
547 if (i
!= initialApicId
) {
554 pendingIPIs
+= apics
.size();
555 intPort
->sendMessage(apics
, message
, timing
);
556 newVal
= regs
[APIC_INTERRUPT_COMMAND_LOW
];
560 case APIC_LVT_THERMAL_SENSOR
:
561 case APIC_LVT_PERFORMANCE_MONITORING_COUNTERS
:
566 uint64_t readOnlyMask
= (1 << 12) | (1 << 14);
567 newVal
= (val
& ~readOnlyMask
) |
568 (regs
[reg
] & readOnlyMask
);
571 case APIC_INITIAL_COUNT
:
574 newVal
= bits(val
, 31, 0);
575 // Compute how many timer ticks we're being programmed for.
576 uint64_t newCount
= newVal
*
577 (divideFromConf(regs
[APIC_DIVIDE_CONFIGURATION
]));
578 // Schedule on the edge of the next tick plus the new count.
579 Tick offset
= curTick() % clock
;
581 reschedule(apicTimerEvent
,
582 curTick() + (newCount
+ 1) * clock
- offset
, true);
584 reschedule(apicTimerEvent
,
585 curTick() + newCount
* clock
, true);
589 case APIC_CURRENT_COUNT
:
590 //Local APIC Current Count register is read only.
592 case APIC_DIVIDE_CONFIGURATION
:
603 X86ISA::Interrupts::Interrupts(Params
* p
) :
604 BasicPioDevice(p
), IntDev(this, p
->int_latency
), latency(p
->pio_latency
),
606 apicTimerEvent(this),
607 pendingSmi(false), smiVector(0),
608 pendingNmi(false), nmiVector(0),
609 pendingExtInt(false), extIntVector(0),
610 pendingInit(false), initVector(0),
611 pendingStartup(false), startupVector(0),
612 startedUp(false), pendingUnmaskableInt(false),
613 pendingIPIs(0), cpu(NULL
)
616 memset(regs
, 0, sizeof(regs
));
617 //Set the local apic DFR to the flat model.
618 regs
[APIC_DESTINATION_FORMAT
] = (uint32_t)(-1);
625 X86ISA::Interrupts::checkInterrupts(ThreadContext
*tc
) const
627 RFLAGS rflags
= tc
->readMiscRegNoEffect(MISCREG_RFLAGS
);
628 if (pendingUnmaskableInt
) {
629 DPRINTF(LocalApic
, "Reported pending unmaskable interrupt.\n");
634 DPRINTF(LocalApic
, "Reported pending external interrupt.\n");
637 if (IRRV
> ISRV
&& bits(IRRV
, 7, 4) >
638 bits(regs
[APIC_TASK_PRIORITY
], 7, 4)) {
639 DPRINTF(LocalApic
, "Reported pending regular interrupt.\n");
647 X86ISA::Interrupts::getInterrupt(ThreadContext
*tc
)
649 assert(checkInterrupts(tc
));
650 // These are all probably fairly uncommon, so we'll make them easier to
652 if (pendingUnmaskableInt
) {
654 DPRINTF(LocalApic
, "Generated SMI fault object.\n");
655 return new SystemManagementInterrupt();
656 } else if (pendingNmi
) {
657 DPRINTF(LocalApic
, "Generated NMI fault object.\n");
658 return new NonMaskableInterrupt(nmiVector
);
659 } else if (pendingInit
) {
660 DPRINTF(LocalApic
, "Generated INIT fault object.\n");
661 return new InitInterrupt(initVector
);
662 } else if (pendingStartup
) {
663 DPRINTF(LocalApic
, "Generating SIPI fault object.\n");
664 return new StartupInterrupt(startupVector
);
666 panic("pendingUnmaskableInt set, but no unmaskable "
667 "ints were pending.\n");
670 } else if (pendingExtInt
) {
671 DPRINTF(LocalApic
, "Generated external interrupt fault object.\n");
672 return new ExternalInterrupt(extIntVector
);
674 DPRINTF(LocalApic
, "Generated regular interrupt fault object.\n");
675 // The only thing left are fixed and lowest priority interrupts.
676 return new ExternalInterrupt(IRRV
);
681 X86ISA::Interrupts::updateIntrInfo(ThreadContext
*tc
)
683 assert(checkInterrupts(tc
));
684 if (pendingUnmaskableInt
) {
686 DPRINTF(LocalApic
, "SMI sent to core.\n");
688 } else if (pendingNmi
) {
689 DPRINTF(LocalApic
, "NMI sent to core.\n");
691 } else if (pendingInit
) {
692 DPRINTF(LocalApic
, "Init sent to core.\n");
695 } else if (pendingStartup
) {
696 DPRINTF(LocalApic
, "SIPI sent to core.\n");
697 pendingStartup
= false;
700 if (!(pendingSmi
|| pendingNmi
|| pendingInit
|| pendingStartup
))
701 pendingUnmaskableInt
= false;
702 } else if (pendingExtInt
) {
703 pendingExtInt
= false;
705 DPRINTF(LocalApic
, "Interrupt %d sent to core.\n", IRRV
);
706 // Mark the interrupt as "in service".
708 setRegArrayBit(APIC_IN_SERVICE_BASE
, ISRV
);
709 // Clear it out of the IRR.
710 clearRegArrayBit(APIC_INTERRUPT_REQUEST_BASE
, IRRV
);
716 X86ISA::Interrupts::serialize(std::ostream
&os
)
718 SERIALIZE_ARRAY(regs
, NUM_APIC_REGS
);
719 SERIALIZE_SCALAR(clock
);
720 SERIALIZE_SCALAR(pendingSmi
);
721 SERIALIZE_SCALAR(smiVector
);
722 SERIALIZE_SCALAR(pendingNmi
);
723 SERIALIZE_SCALAR(nmiVector
);
724 SERIALIZE_SCALAR(pendingExtInt
);
725 SERIALIZE_SCALAR(extIntVector
);
726 SERIALIZE_SCALAR(pendingInit
);
727 SERIALIZE_SCALAR(initVector
);
728 SERIALIZE_SCALAR(pendingStartup
);
729 SERIALIZE_SCALAR(startupVector
);
730 SERIALIZE_SCALAR(startedUp
);
731 SERIALIZE_SCALAR(pendingUnmaskableInt
);
732 SERIALIZE_SCALAR(pendingIPIs
);
733 SERIALIZE_SCALAR(IRRV
);
734 SERIALIZE_SCALAR(ISRV
);
735 bool apicTimerEventScheduled
= apicTimerEvent
.scheduled();
736 SERIALIZE_SCALAR(apicTimerEventScheduled
);
737 Tick apicTimerEventTick
= apicTimerEvent
.when();
738 SERIALIZE_SCALAR(apicTimerEventTick
);
742 X86ISA::Interrupts::unserialize(Checkpoint
*cp
, const std::string
§ion
)
744 UNSERIALIZE_ARRAY(regs
, NUM_APIC_REGS
);
745 UNSERIALIZE_SCALAR(clock
);
746 UNSERIALIZE_SCALAR(pendingSmi
);
747 UNSERIALIZE_SCALAR(smiVector
);
748 UNSERIALIZE_SCALAR(pendingNmi
);
749 UNSERIALIZE_SCALAR(nmiVector
);
750 UNSERIALIZE_SCALAR(pendingExtInt
);
751 UNSERIALIZE_SCALAR(extIntVector
);
752 UNSERIALIZE_SCALAR(pendingInit
);
753 UNSERIALIZE_SCALAR(initVector
);
754 UNSERIALIZE_SCALAR(pendingStartup
);
755 UNSERIALIZE_SCALAR(startupVector
);
756 UNSERIALIZE_SCALAR(startedUp
);
757 UNSERIALIZE_SCALAR(pendingUnmaskableInt
);
758 UNSERIALIZE_SCALAR(pendingIPIs
);
759 UNSERIALIZE_SCALAR(IRRV
);
760 UNSERIALIZE_SCALAR(ISRV
);
761 bool apicTimerEventScheduled
;
762 UNSERIALIZE_SCALAR(apicTimerEventScheduled
);
763 if (apicTimerEventScheduled
) {
764 Tick apicTimerEventTick
;
765 UNSERIALIZE_SCALAR(apicTimerEventTick
);
766 if (apicTimerEvent
.scheduled()) {
767 reschedule(apicTimerEvent
, apicTimerEventTick
, true);
769 schedule(apicTimerEvent
, apicTimerEventTick
);
775 X86LocalApicParams::create()
777 return new X86ISA::Interrupts(this);