2 * Copyright (c) 2008 The Hewlett-Packard Development Company
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
9 * The software must be used only for Non-Commercial Use which means any
10 * use which is NOT directed to receiving any direct monetary
11 * compensation for, or commercial advantage from such use. Illustrative
12 * examples of non-commercial use are academic research, personal study,
13 * teaching, education and corporate research & development.
14 * Illustrative examples of commercial use are distributing products for
15 * commercial advantage and providing services using the software for
16 * commercial advantage.
18 * If you wish to use this software or functionality therein that may be
19 * covered by patents for commercial use, please contact:
20 * Director of Intellectual Property Licensing
21 * Office of Strategy and Technology
22 * Hewlett-Packard Company
24 * Palo Alto, California 94304
26 * Redistributions of source code must retain the above copyright notice,
27 * this list of conditions and the following disclaimer. Redistributions
28 * in binary form must reproduce the above copyright notice, this list of
29 * conditions and the following disclaimer in the documentation and/or
30 * other materials provided with the distribution. Neither the name of
31 * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
32 * contributors may be used to endorse or promote products derived from
33 * this software without specific prior written permission. No right of
34 * sublicense is granted herewith. Derivatives of the software and
35 * output created using the software may be prepared, but only for
36 * Non-Commercial Uses. Derivatives of the software may be shared with
37 * others provided: (i) the others agree to abide by the list of
38 * conditions herein which includes the Non-Commercial Use restrictions;
39 * and (ii) such Derivatives of the software include the above copyright
40 * notice to acknowledge the contribution from this software where
41 * applicable, this list of conditions and the disclaimer below.
43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
58 #include "arch/x86/apicregs.hh"
59 #include "arch/x86/interrupts.hh"
60 #include "arch/x86/intmessage.hh"
61 #include "cpu/base.hh"
62 #include "mem/packet_access.hh"
65 divideFromConf(uint32_t conf
)
67 // This figures out what division we want from the division configuration
68 // register in the local APIC. The encoding is a little odd but it can
69 // be deciphered fairly easily.
70 int shift
= ((conf
& 0x8) >> 1) | (conf
& 0x3);
71 shift
= (shift
+ 1) % 8;
79 decodeAddr(Addr paddr
)
89 regNum
= APIC_VERSION
;
92 regNum
= APIC_TASK_PRIORITY
;
95 regNum
= APIC_ARBITRATION_PRIORITY
;
98 regNum
= APIC_PROCESSOR_PRIORITY
;
104 regNum
= APIC_LOGICAL_DESTINATION
;
107 regNum
= APIC_DESTINATION_FORMAT
;
110 regNum
= APIC_SPURIOUS_INTERRUPT_VECTOR
;
128 regNum
= APIC_IN_SERVICE((paddr
- 0x100) / 0x8);
146 regNum
= APIC_TRIGGER_MODE((paddr
- 0x180) / 0x8);
164 regNum
= APIC_INTERRUPT_REQUEST((paddr
- 0x200) / 0x8);
167 regNum
= APIC_ERROR_STATUS
;
170 regNum
= APIC_INTERRUPT_COMMAND_LOW
;
173 regNum
= APIC_INTERRUPT_COMMAND_HIGH
;
176 regNum
= APIC_LVT_TIMER
;
179 regNum
= APIC_LVT_THERMAL_SENSOR
;
182 regNum
= APIC_LVT_PERFORMANCE_MONITORING_COUNTERS
;
185 regNum
= APIC_LVT_LINT0
;
188 regNum
= APIC_LVT_LINT1
;
191 regNum
= APIC_LVT_ERROR
;
194 regNum
= APIC_INITIAL_COUNT
;
197 regNum
= APIC_CURRENT_COUNT
;
200 regNum
= APIC_DIVIDE_CONFIGURATION
;
203 // A reserved register field.
204 panic("Accessed reserved register field %#x.\n", paddr
);
212 X86ISA::Interrupts::read(PacketPtr pkt
)
214 Addr offset
= pkt
->getAddr() - pioAddr
;
215 //Make sure we're at least only accessing one register.
216 if ((offset
& ~mask(3)) != ((offset
+ pkt
->getSize()) & ~mask(3)))
217 panic("Accessed more than one register at a time in the APIC!\n");
218 ApicRegIndex reg
= decodeAddr(offset
);
219 uint32_t val
= htog(readReg(reg
));
221 "Reading Local APIC register %d at offset %#x as %#x.\n",
223 pkt
->setData(((uint8_t *)&val
) + (offset
& mask(3)));
224 pkt
->makeAtomicResponse();
229 X86ISA::Interrupts::write(PacketPtr pkt
)
231 Addr offset
= pkt
->getAddr() - pioAddr
;
232 //Make sure we're at least only accessing one register.
233 if ((offset
& ~mask(3)) != ((offset
+ pkt
->getSize()) & ~mask(3)))
234 panic("Accessed more than one register at a time in the APIC!\n");
235 ApicRegIndex reg
= decodeAddr(offset
);
236 uint32_t val
= regs
[reg
];
237 pkt
->writeData(((uint8_t *)&val
) + (offset
& mask(3)));
239 "Writing Local APIC register %d at offset %#x as %#x.\n",
240 reg
, offset
, gtoh(val
));
241 setReg(reg
, gtoh(val
));
242 pkt
->makeAtomicResponse();
246 X86ISA::Interrupts::requestInterrupt(uint8_t vector
,
247 uint8_t deliveryMode
, bool level
)
250 * Fixed and lowest-priority delivery mode interrupts are handled
251 * using the IRR/ISR registers, checking against the TPR, etc.
252 * The SMI, NMI, ExtInt, INIT, etc interrupts go straight through.
254 if (deliveryMode
== DeliveryMode::Fixed
||
255 deliveryMode
== DeliveryMode::LowestPriority
) {
256 DPRINTF(LocalApic
, "Interrupt is an %s.\n",
257 DeliveryMode::names
[deliveryMode
]);
258 // Queue up the interrupt in the IRR.
261 if (!getRegArrayBit(APIC_INTERRUPT_REQUEST_BASE
, vector
)) {
262 setRegArrayBit(APIC_INTERRUPT_REQUEST_BASE
, vector
);
264 setRegArrayBit(APIC_TRIGGER_MODE_BASE
, vector
);
266 clearRegArrayBit(APIC_TRIGGER_MODE_BASE
, vector
);
269 } else if (!DeliveryMode::isReserved(deliveryMode
)) {
270 DPRINTF(LocalApic
, "Interrupt is an %s.\n",
271 DeliveryMode::names
[deliveryMode
]);
272 if (deliveryMode
== DeliveryMode::SMI
&& !pendingSmi
) {
273 pendingUnmaskableInt
= pendingSmi
= true;
275 } else if (deliveryMode
== DeliveryMode::NMI
&& !pendingNmi
) {
276 pendingUnmaskableInt
= pendingNmi
= true;
278 } else if (deliveryMode
== DeliveryMode::ExtInt
&& !pendingExtInt
) {
279 pendingExtInt
= true;
280 extIntVector
= vector
;
281 } else if (deliveryMode
== DeliveryMode::INIT
&& !pendingInit
) {
282 pendingUnmaskableInt
= pendingInit
= true;
290 X86ISA::Interrupts::recvMessage(PacketPtr pkt
)
293 Addr offset
= pkt
->getAddr() - x86InterruptAddress(id
, 0);
294 assert(pkt
->cmd
== MemCmd::MessageReq
);
299 TriggerIntMessage message
= pkt
->get
<TriggerIntMessage
>();
301 "Got Trigger Interrupt message with vector %#x.\n",
303 // Make sure we're really supposed to get this.
304 assert((message
.destMode
== 0 && message
.destination
== id
) ||
305 (bits((int)message
.destination
, id
)));
307 requestInterrupt(message
.vector
,
308 message
.deliveryMode
, message
.trigger
);
312 panic("Local apic got unknown interrupt message at offset %#x.\n",
323 X86ISA::Interrupts::readReg(ApicRegIndex reg
)
325 if (reg
>= APIC_TRIGGER_MODE(0) &&
326 reg
<= APIC_TRIGGER_MODE(15)) {
327 panic("Local APIC Trigger Mode registers are unimplemented.\n");
330 case APIC_ARBITRATION_PRIORITY
:
331 panic("Local APIC Arbitration Priority register unimplemented.\n");
333 case APIC_PROCESSOR_PRIORITY
:
334 panic("Local APIC Processor Priority register unimplemented.\n");
336 case APIC_ERROR_STATUS
:
337 regs
[APIC_INTERNAL_STATE
] &= ~ULL(0x1);
339 case APIC_INTERRUPT_COMMAND_LOW
:
340 panic("Local APIC Interrupt Command low"
341 " register unimplemented.\n");
343 case APIC_INTERRUPT_COMMAND_HIGH
:
344 panic("Local APIC Interrupt Command high"
345 " register unimplemented.\n");
347 case APIC_CURRENT_COUNT
:
349 if (apicTimerEvent
.scheduled()) {
351 // Compute how many m5 ticks happen per count.
352 uint64_t ticksPerCount
= clock
*
353 divideFromConf(regs
[APIC_DIVIDE_CONFIGURATION
]);
354 // Compute how many m5 ticks are left.
355 uint64_t val
= apicTimerEvent
.when() - curTick
;
356 // Turn that into a count.
357 val
= (val
+ ticksPerCount
- 1) / ticksPerCount
;
370 X86ISA::Interrupts::setReg(ApicRegIndex reg
, uint32_t val
)
372 uint32_t newVal
= val
;
373 if (reg
>= APIC_IN_SERVICE(0) &&
374 reg
<= APIC_IN_SERVICE(15)) {
375 panic("Local APIC In-Service registers are unimplemented.\n");
377 if (reg
>= APIC_TRIGGER_MODE(0) &&
378 reg
<= APIC_TRIGGER_MODE(15)) {
379 panic("Local APIC Trigger Mode registers are unimplemented.\n");
381 if (reg
>= APIC_INTERRUPT_REQUEST(0) &&
382 reg
<= APIC_INTERRUPT_REQUEST(15)) {
383 panic("Local APIC Interrupt Request registers "
384 "are unimplemented.\n");
391 // The Local APIC Version register is read only.
393 case APIC_TASK_PRIORITY
:
396 case APIC_ARBITRATION_PRIORITY
:
397 panic("Local APIC Arbitration Priority register unimplemented.\n");
399 case APIC_PROCESSOR_PRIORITY
:
400 panic("Local APIC Processor Priority register unimplemented.\n");
403 // Remove the interrupt that just completed from the local apic state.
404 clearRegArrayBit(APIC_IN_SERVICE_BASE
, ISRV
);
407 case APIC_LOGICAL_DESTINATION
:
408 newVal
= val
& 0xFF000000;
410 case APIC_DESTINATION_FORMAT
:
411 newVal
= val
| 0x0FFFFFFF;
413 case APIC_SPURIOUS_INTERRUPT_VECTOR
:
414 regs
[APIC_INTERNAL_STATE
] &= ~ULL(1 << 1);
415 regs
[APIC_INTERNAL_STATE
] |= val
& (1 << 8);
417 warn("Focus processor checking not implemented.\n");
419 case APIC_ERROR_STATUS
:
421 if (regs
[APIC_INTERNAL_STATE
] & 0x1) {
422 regs
[APIC_INTERNAL_STATE
] &= ~ULL(0x1);
425 regs
[APIC_INTERNAL_STATE
] |= ULL(0x1);
431 case APIC_INTERRUPT_COMMAND_LOW
:
432 panic("Local APIC Interrupt Command low"
433 " register unimplemented.\n");
435 case APIC_INTERRUPT_COMMAND_HIGH
:
436 panic("Local APIC Interrupt Command high"
437 " register unimplemented.\n");
440 case APIC_LVT_THERMAL_SENSOR
:
441 case APIC_LVT_PERFORMANCE_MONITORING_COUNTERS
:
446 uint64_t readOnlyMask
= (1 << 12) | (1 << 14);
447 newVal
= (val
& ~readOnlyMask
) |
448 (regs
[reg
] & readOnlyMask
);
451 case APIC_INITIAL_COUNT
:
454 newVal
= bits(val
, 31, 0);
455 // Compute how many timer ticks we're being programmed for.
456 uint64_t newCount
= newVal
*
457 (divideFromConf(regs
[APIC_DIVIDE_CONFIGURATION
]));
458 // Schedule on the edge of the next tick plus the new count.
459 Tick offset
= curTick
% clock
;
461 reschedule(apicTimerEvent
,
462 curTick
+ (newCount
+ 1) * clock
- offset
, true);
464 reschedule(apicTimerEvent
,
465 curTick
+ newCount
* clock
, true);
469 case APIC_CURRENT_COUNT
:
470 //Local APIC Current Count register is read only.
472 case APIC_DIVIDE_CONFIGURATION
:
483 X86ISA::Interrupts::checkInterrupts(ThreadContext
*tc
) const
485 RFLAGS rflags
= tc
->readMiscRegNoEffect(MISCREG_RFLAGS
);
486 if (pendingUnmaskableInt
) {
487 DPRINTF(LocalApic
, "Reported pending unmaskable interrupt.\n");
492 DPRINTF(LocalApic
, "Reported pending external interrupt.\n");
495 if (IRRV
> ISRV
&& bits(IRRV
, 7, 4) >
496 bits(regs
[APIC_TASK_PRIORITY
], 7, 4)) {
497 DPRINTF(LocalApic
, "Reported pending regular interrupt.\n");
505 X86ISA::Interrupts::getInterrupt(ThreadContext
*tc
)
507 assert(checkInterrupts(tc
));
508 // These are all probably fairly uncommon, so we'll make them easier to
510 if (pendingUnmaskableInt
) {
512 DPRINTF(LocalApic
, "Generated SMI fault object.\n");
513 return new SystemManagementInterrupt();
514 } else if (pendingNmi
) {
515 DPRINTF(LocalApic
, "Generated NMI fault object.\n");
516 return new NonMaskableInterrupt(nmiVector
);
517 } else if (pendingInit
) {
518 DPRINTF(LocalApic
, "Generated INIT fault object.\n");
519 return new InitInterrupt(initVector
);
521 panic("pendingUnmaskableInt set, but no unmaskable "
522 "ints were pending.\n");
525 } else if (pendingExtInt
) {
526 DPRINTF(LocalApic
, "Generated external interrupt fault object.\n");
527 return new ExternalInterrupt(extIntVector
);
529 DPRINTF(LocalApic
, "Generated regular interrupt fault object.\n");
530 // The only thing left are fixed and lowest priority interrupts.
531 return new ExternalInterrupt(IRRV
);
536 X86ISA::Interrupts::updateIntrInfo(ThreadContext
*tc
)
538 assert(checkInterrupts(tc
));
539 if (pendingUnmaskableInt
) {
541 DPRINTF(LocalApic
, "SMI sent to core.\n");
543 } else if (pendingNmi
) {
544 DPRINTF(LocalApic
, "NMI sent to core.\n");
546 } else if (pendingInit
) {
547 DPRINTF(LocalApic
, "Init sent to core.\n");
550 if (!(pendingSmi
|| pendingNmi
|| pendingInit
))
551 pendingUnmaskableInt
= false;
552 } else if (pendingExtInt
) {
553 pendingExtInt
= false;
555 DPRINTF(LocalApic
, "Interrupt %d sent to core.\n", IRRV
);
556 // Mark the interrupt as "in service".
558 setRegArrayBit(APIC_IN_SERVICE_BASE
, ISRV
);
559 // Clear it out of the IRR.
560 clearRegArrayBit(APIC_INTERRUPT_REQUEST_BASE
, IRRV
);
566 X86LocalApicParams::create()
568 return new X86ISA::Interrupts(this);