2 * Copyright (c) 2008 The Hewlett-Packard Development Company
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 #include "arch/x86/regs/apic.hh"
41 #include "arch/x86/interrupts.hh"
42 #include "arch/x86/intmessage.hh"
43 #include "cpu/base.hh"
44 #include "debug/LocalApic.hh"
45 #include "dev/x86/i82094aa.hh"
46 #include "dev/x86/pc.hh"
47 #include "dev/x86/south_bridge.hh"
48 #include "mem/packet_access.hh"
49 #include "sim/system.hh"
52 divideFromConf(uint32_t conf
)
54 // This figures out what division we want from the division configuration
55 // register in the local APIC. The encoding is a little odd but it can
56 // be deciphered fairly easily.
57 int shift
= ((conf
& 0x8) >> 1) | (conf
& 0x3);
58 shift
= (shift
+ 1) % 8;
66 decodeAddr(Addr paddr
)
76 regNum
= APIC_VERSION
;
79 regNum
= APIC_TASK_PRIORITY
;
82 regNum
= APIC_ARBITRATION_PRIORITY
;
85 regNum
= APIC_PROCESSOR_PRIORITY
;
91 regNum
= APIC_LOGICAL_DESTINATION
;
94 regNum
= APIC_DESTINATION_FORMAT
;
97 regNum
= APIC_SPURIOUS_INTERRUPT_VECTOR
;
115 regNum
= APIC_IN_SERVICE((paddr
- 0x100) / 0x8);
133 regNum
= APIC_TRIGGER_MODE((paddr
- 0x180) / 0x8);
151 regNum
= APIC_INTERRUPT_REQUEST((paddr
- 0x200) / 0x8);
154 regNum
= APIC_ERROR_STATUS
;
157 regNum
= APIC_INTERRUPT_COMMAND_LOW
;
160 regNum
= APIC_INTERRUPT_COMMAND_HIGH
;
163 regNum
= APIC_LVT_TIMER
;
166 regNum
= APIC_LVT_THERMAL_SENSOR
;
169 regNum
= APIC_LVT_PERFORMANCE_MONITORING_COUNTERS
;
172 regNum
= APIC_LVT_LINT0
;
175 regNum
= APIC_LVT_LINT1
;
178 regNum
= APIC_LVT_ERROR
;
181 regNum
= APIC_INITIAL_COUNT
;
184 regNum
= APIC_CURRENT_COUNT
;
187 regNum
= APIC_DIVIDE_CONFIGURATION
;
190 // A reserved register field.
191 panic("Accessed reserved register field %#x.\n", paddr
);
199 X86ISA::Interrupts::read(PacketPtr pkt
)
201 Addr offset
= pkt
->getAddr() - pioAddr
;
202 //Make sure we're at least only accessing one register.
203 if ((offset
& ~mask(3)) != ((offset
+ pkt
->getSize()) & ~mask(3)))
204 panic("Accessed more than one register at a time in the APIC!\n");
205 ApicRegIndex reg
= decodeAddr(offset
);
206 uint32_t val
= htog(readReg(reg
));
208 "Reading Local APIC register %d at offset %#x as %#x.\n",
210 pkt
->setData(((uint8_t *)&val
) + (offset
& mask(3)));
211 pkt
->makeAtomicResponse();
216 X86ISA::Interrupts::write(PacketPtr pkt
)
218 Addr offset
= pkt
->getAddr() - pioAddr
;
219 //Make sure we're at least only accessing one register.
220 if ((offset
& ~mask(3)) != ((offset
+ pkt
->getSize()) & ~mask(3)))
221 panic("Accessed more than one register at a time in the APIC!\n");
222 ApicRegIndex reg
= decodeAddr(offset
);
223 uint32_t val
= regs
[reg
];
224 pkt
->writeData(((uint8_t *)&val
) + (offset
& mask(3)));
226 "Writing Local APIC register %d at offset %#x as %#x.\n",
227 reg
, offset
, gtoh(val
));
228 setReg(reg
, gtoh(val
));
229 pkt
->makeAtomicResponse();
233 X86ISA::Interrupts::requestInterrupt(uint8_t vector
,
234 uint8_t deliveryMode
, bool level
)
237 * Fixed and lowest-priority delivery mode interrupts are handled
238 * using the IRR/ISR registers, checking against the TPR, etc.
239 * The SMI, NMI, ExtInt, INIT, etc interrupts go straight through.
241 if (deliveryMode
== DeliveryMode::Fixed
||
242 deliveryMode
== DeliveryMode::LowestPriority
) {
243 DPRINTF(LocalApic
, "Interrupt is an %s.\n",
244 DeliveryMode::names
[deliveryMode
]);
245 // Queue up the interrupt in the IRR.
248 if (!getRegArrayBit(APIC_INTERRUPT_REQUEST_BASE
, vector
)) {
249 setRegArrayBit(APIC_INTERRUPT_REQUEST_BASE
, vector
);
251 setRegArrayBit(APIC_TRIGGER_MODE_BASE
, vector
);
253 clearRegArrayBit(APIC_TRIGGER_MODE_BASE
, vector
);
256 } else if (!DeliveryMode::isReserved(deliveryMode
)) {
257 DPRINTF(LocalApic
, "Interrupt is an %s.\n",
258 DeliveryMode::names
[deliveryMode
]);
259 if (deliveryMode
== DeliveryMode::SMI
&& !pendingSmi
) {
260 pendingUnmaskableInt
= pendingSmi
= true;
262 } else if (deliveryMode
== DeliveryMode::NMI
&& !pendingNmi
) {
263 pendingUnmaskableInt
= pendingNmi
= true;
265 } else if (deliveryMode
== DeliveryMode::ExtInt
&& !pendingExtInt
) {
266 pendingExtInt
= true;
267 extIntVector
= vector
;
268 } else if (deliveryMode
== DeliveryMode::INIT
&& !pendingInit
) {
269 pendingUnmaskableInt
= pendingInit
= true;
271 } else if (deliveryMode
== DeliveryMode::SIPI
&&
272 !pendingStartup
&& !startedUp
) {
273 pendingUnmaskableInt
= pendingStartup
= true;
274 startupVector
= vector
;
277 #if FULL_SYSTEM //XXX CPU has no wakeup method in SE mode.
284 X86ISA::Interrupts::setCPU(BaseCPU
* newCPU
)
287 if (cpu
!= NULL
&& cpu
->cpuId() != newCPU
->cpuId()) {
288 panic("Local APICs can't be moved between CPUs"
289 " with different IDs.\n");
292 initialApicId
= cpu
->cpuId();
293 regs
[APIC_ID
] = (initialApicId
<< 24);
298 X86ISA::Interrupts::init()
301 // The local apic must register its address ranges on both its pio port
302 // via the basicpiodevice(piodevice) init() function and its int port
303 // that it inherited from IntDev. Note IntDev is not a SimObject itself.
305 BasicPioDevice::init();
308 Pc
* pc
= dynamic_cast<Pc
*>(platform
);
310 pc
->southBridge
->ioApic
->registerLocalApic(initialApicId
, this);
316 X86ISA::Interrupts::recvMessage(PacketPtr pkt
)
318 Addr offset
= pkt
->getAddr() - x86InterruptAddress(initialApicId
, 0);
319 assert(pkt
->cmd
== MemCmd::MessageReq
);
324 TriggerIntMessage message
= pkt
->get
<TriggerIntMessage
>();
326 "Got Trigger Interrupt message with vector %#x.\n",
329 requestInterrupt(message
.vector
,
330 message
.deliveryMode
, message
.trigger
);
334 panic("Local apic got unknown interrupt message at offset %#x.\n",
338 pkt
->makeAtomicResponse();
344 X86ISA::Interrupts::recvResponse(PacketPtr pkt
)
346 assert(!pkt
->isError());
347 assert(pkt
->cmd
== MemCmd::MessageResp
);
348 if (--pendingIPIs
== 0) {
349 InterruptCommandRegLow low
= regs
[APIC_INTERRUPT_COMMAND_LOW
];
350 // Record that the ICR is now idle.
351 low
.deliveryStatus
= 0;
352 regs
[APIC_INTERRUPT_COMMAND_LOW
] = low
;
354 DPRINTF(LocalApic
, "ICR is now idle.\n");
360 X86ISA::Interrupts::addressRanges(AddrRangeList
&range_list
)
363 Range
<Addr
> range
= RangeEx(x86LocalAPICAddress(initialApicId
, 0),
364 x86LocalAPICAddress(initialApicId
, 0) +
366 range_list
.push_back(range
);
367 pioAddr
= range
.start
;
372 X86ISA::Interrupts::getIntAddrRange(AddrRangeList
&range_list
)
375 range_list
.push_back(RangeEx(x86InterruptAddress(initialApicId
, 0),
376 x86InterruptAddress(initialApicId
, 0) +
377 PhysAddrAPICRangeSize
));
382 X86ISA::Interrupts::readReg(ApicRegIndex reg
)
384 if (reg
>= APIC_TRIGGER_MODE(0) &&
385 reg
<= APIC_TRIGGER_MODE(15)) {
386 panic("Local APIC Trigger Mode registers are unimplemented.\n");
389 case APIC_ARBITRATION_PRIORITY
:
390 panic("Local APIC Arbitration Priority register unimplemented.\n");
392 case APIC_PROCESSOR_PRIORITY
:
393 panic("Local APIC Processor Priority register unimplemented.\n");
395 case APIC_ERROR_STATUS
:
396 regs
[APIC_INTERNAL_STATE
] &= ~ULL(0x1);
398 case APIC_CURRENT_COUNT
:
400 if (apicTimerEvent
.scheduled()) {
402 // Compute how many m5 ticks happen per count.
403 uint64_t ticksPerCount
= clock
*
404 divideFromConf(regs
[APIC_DIVIDE_CONFIGURATION
]);
405 // Compute how many m5 ticks are left.
406 uint64_t val
= apicTimerEvent
.when() - curTick();
407 // Turn that into a count.
408 val
= (val
+ ticksPerCount
- 1) / ticksPerCount
;
421 X86ISA::Interrupts::setReg(ApicRegIndex reg
, uint32_t val
)
423 uint32_t newVal
= val
;
424 if (reg
>= APIC_IN_SERVICE(0) &&
425 reg
<= APIC_IN_SERVICE(15)) {
426 panic("Local APIC In-Service registers are unimplemented.\n");
428 if (reg
>= APIC_TRIGGER_MODE(0) &&
429 reg
<= APIC_TRIGGER_MODE(15)) {
430 panic("Local APIC Trigger Mode registers are unimplemented.\n");
432 if (reg
>= APIC_INTERRUPT_REQUEST(0) &&
433 reg
<= APIC_INTERRUPT_REQUEST(15)) {
434 panic("Local APIC Interrupt Request registers "
435 "are unimplemented.\n");
442 // The Local APIC Version register is read only.
444 case APIC_TASK_PRIORITY
:
447 case APIC_ARBITRATION_PRIORITY
:
448 panic("Local APIC Arbitration Priority register unimplemented.\n");
450 case APIC_PROCESSOR_PRIORITY
:
451 panic("Local APIC Processor Priority register unimplemented.\n");
454 // Remove the interrupt that just completed from the local apic state.
455 clearRegArrayBit(APIC_IN_SERVICE_BASE
, ISRV
);
458 case APIC_LOGICAL_DESTINATION
:
459 newVal
= val
& 0xFF000000;
461 case APIC_DESTINATION_FORMAT
:
462 newVal
= val
| 0x0FFFFFFF;
464 case APIC_SPURIOUS_INTERRUPT_VECTOR
:
465 regs
[APIC_INTERNAL_STATE
] &= ~ULL(1 << 1);
466 regs
[APIC_INTERNAL_STATE
] |= val
& (1 << 8);
468 warn("Focus processor checking not implemented.\n");
470 case APIC_ERROR_STATUS
:
472 if (regs
[APIC_INTERNAL_STATE
] & 0x1) {
473 regs
[APIC_INTERNAL_STATE
] &= ~ULL(0x1);
476 regs
[APIC_INTERNAL_STATE
] |= ULL(0x1);
482 case APIC_INTERRUPT_COMMAND_LOW
:
484 InterruptCommandRegLow low
= regs
[APIC_INTERRUPT_COMMAND_LOW
];
485 // Check if we're already sending an IPI.
486 if (low
.deliveryStatus
) {
491 InterruptCommandRegHigh high
= regs
[APIC_INTERRUPT_COMMAND_HIGH
];
492 // Record that an IPI is being sent.
493 low
.deliveryStatus
= 1;
494 TriggerIntMessage message
= 0;
495 message
.destination
= high
.destination
;
496 message
.vector
= low
.vector
;
497 message
.deliveryMode
= low
.deliveryMode
;
498 message
.destMode
= low
.destMode
;
499 message
.level
= low
.level
;
500 message
.trigger
= low
.trigger
;
501 bool timing
= sys
->getMemoryMode() == Enums::timing
;
502 // Be careful no updates of the delivery status bit get lost.
503 regs
[APIC_INTERRUPT_COMMAND_LOW
] = low
;
505 int numContexts
= sys
->numContexts();
506 switch (low
.destShorthand
) {
508 if (message
.deliveryMode
== DeliveryMode::LowestPriority
) {
509 panic("Lowest priority delivery mode "
510 "IPIs aren't implemented.\n");
512 if (message
.destMode
== 1) {
513 int dest
= message
.destination
;
514 hack_once("Assuming logical destinations are 1 << id.\n");
515 for (int i
= 0; i
< numContexts
; i
++) {
521 if (message
.destination
== 0xFF) {
522 for (int i
= 0; i
< numContexts
; i
++) {
523 if (i
== initialApicId
) {
524 requestInterrupt(message
.vector
,
525 message
.deliveryMode
, message
.trigger
);
531 if (message
.destination
== initialApicId
) {
532 requestInterrupt(message
.vector
,
533 message
.deliveryMode
, message
.trigger
);
535 apics
.push_back(message
.destination
);
542 requestInterrupt(message
.vector
,
543 message
.deliveryMode
, message
.trigger
);
546 requestInterrupt(message
.vector
,
547 message
.deliveryMode
, message
.trigger
);
551 for (int i
= 0; i
< numContexts
; i
++) {
552 if (i
!= initialApicId
) {
559 pendingIPIs
+= apics
.size();
560 intPort
->sendMessage(apics
, message
, timing
);
561 newVal
= regs
[APIC_INTERRUPT_COMMAND_LOW
];
565 case APIC_LVT_THERMAL_SENSOR
:
566 case APIC_LVT_PERFORMANCE_MONITORING_COUNTERS
:
571 uint64_t readOnlyMask
= (1 << 12) | (1 << 14);
572 newVal
= (val
& ~readOnlyMask
) |
573 (regs
[reg
] & readOnlyMask
);
576 case APIC_INITIAL_COUNT
:
579 newVal
= bits(val
, 31, 0);
580 // Compute how many timer ticks we're being programmed for.
581 uint64_t newCount
= newVal
*
582 (divideFromConf(regs
[APIC_DIVIDE_CONFIGURATION
]));
583 // Schedule on the edge of the next tick plus the new count.
584 Tick offset
= curTick() % clock
;
586 reschedule(apicTimerEvent
,
587 curTick() + (newCount
+ 1) * clock
- offset
, true);
589 reschedule(apicTimerEvent
,
590 curTick() + newCount
* clock
, true);
594 case APIC_CURRENT_COUNT
:
595 //Local APIC Current Count register is read only.
597 case APIC_DIVIDE_CONFIGURATION
:
608 X86ISA::Interrupts::Interrupts(Params
* p
) :
609 BasicPioDevice(p
), IntDev(this, p
->int_latency
), latency(p
->pio_latency
),
611 apicTimerEvent(this),
612 pendingSmi(false), smiVector(0),
613 pendingNmi(false), nmiVector(0),
614 pendingExtInt(false), extIntVector(0),
615 pendingInit(false), initVector(0),
616 pendingStartup(false), startupVector(0),
617 startedUp(false), pendingUnmaskableInt(false),
618 pendingIPIs(0), cpu(NULL
)
620 , platform(p
->platform
)
624 memset(regs
, 0, sizeof(regs
));
625 //Set the local apic DFR to the flat model.
626 regs
[APIC_DESTINATION_FORMAT
] = (uint32_t)(-1);
633 X86ISA::Interrupts::checkInterrupts(ThreadContext
*tc
) const
635 RFLAGS rflags
= tc
->readMiscRegNoEffect(MISCREG_RFLAGS
);
636 if (pendingUnmaskableInt
) {
637 DPRINTF(LocalApic
, "Reported pending unmaskable interrupt.\n");
642 DPRINTF(LocalApic
, "Reported pending external interrupt.\n");
645 if (IRRV
> ISRV
&& bits(IRRV
, 7, 4) >
646 bits(regs
[APIC_TASK_PRIORITY
], 7, 4)) {
647 DPRINTF(LocalApic
, "Reported pending regular interrupt.\n");
655 X86ISA::Interrupts::getInterrupt(ThreadContext
*tc
)
657 assert(checkInterrupts(tc
));
658 // These are all probably fairly uncommon, so we'll make them easier to
660 if (pendingUnmaskableInt
) {
662 DPRINTF(LocalApic
, "Generated SMI fault object.\n");
663 return new SystemManagementInterrupt();
664 } else if (pendingNmi
) {
665 DPRINTF(LocalApic
, "Generated NMI fault object.\n");
666 return new NonMaskableInterrupt(nmiVector
);
667 } else if (pendingInit
) {
668 DPRINTF(LocalApic
, "Generated INIT fault object.\n");
669 return new InitInterrupt(initVector
);
670 } else if (pendingStartup
) {
671 DPRINTF(LocalApic
, "Generating SIPI fault object.\n");
672 return new StartupInterrupt(startupVector
);
674 panic("pendingUnmaskableInt set, but no unmaskable "
675 "ints were pending.\n");
678 } else if (pendingExtInt
) {
679 DPRINTF(LocalApic
, "Generated external interrupt fault object.\n");
680 return new ExternalInterrupt(extIntVector
);
682 DPRINTF(LocalApic
, "Generated regular interrupt fault object.\n");
683 // The only thing left are fixed and lowest priority interrupts.
684 return new ExternalInterrupt(IRRV
);
689 X86ISA::Interrupts::updateIntrInfo(ThreadContext
*tc
)
691 assert(checkInterrupts(tc
));
692 if (pendingUnmaskableInt
) {
694 DPRINTF(LocalApic
, "SMI sent to core.\n");
696 } else if (pendingNmi
) {
697 DPRINTF(LocalApic
, "NMI sent to core.\n");
699 } else if (pendingInit
) {
700 DPRINTF(LocalApic
, "Init sent to core.\n");
703 } else if (pendingStartup
) {
704 DPRINTF(LocalApic
, "SIPI sent to core.\n");
705 pendingStartup
= false;
708 if (!(pendingSmi
|| pendingNmi
|| pendingInit
|| pendingStartup
))
709 pendingUnmaskableInt
= false;
710 } else if (pendingExtInt
) {
711 pendingExtInt
= false;
713 DPRINTF(LocalApic
, "Interrupt %d sent to core.\n", IRRV
);
714 // Mark the interrupt as "in service".
716 setRegArrayBit(APIC_IN_SERVICE_BASE
, ISRV
);
717 // Clear it out of the IRR.
718 clearRegArrayBit(APIC_INTERRUPT_REQUEST_BASE
, IRRV
);
724 X86ISA::Interrupts::serialize(std::ostream
&os
)
726 SERIALIZE_ARRAY(regs
, NUM_APIC_REGS
);
727 SERIALIZE_SCALAR(clock
);
728 SERIALIZE_SCALAR(pendingSmi
);
729 SERIALIZE_SCALAR(smiVector
);
730 SERIALIZE_SCALAR(pendingNmi
);
731 SERIALIZE_SCALAR(nmiVector
);
732 SERIALIZE_SCALAR(pendingExtInt
);
733 SERIALIZE_SCALAR(extIntVector
);
734 SERIALIZE_SCALAR(pendingInit
);
735 SERIALIZE_SCALAR(initVector
);
736 SERIALIZE_SCALAR(pendingStartup
);
737 SERIALIZE_SCALAR(startupVector
);
738 SERIALIZE_SCALAR(startedUp
);
739 SERIALIZE_SCALAR(pendingUnmaskableInt
);
740 SERIALIZE_SCALAR(pendingIPIs
);
741 SERIALIZE_SCALAR(IRRV
);
742 SERIALIZE_SCALAR(ISRV
);
743 bool apicTimerEventScheduled
= apicTimerEvent
.scheduled();
744 SERIALIZE_SCALAR(apicTimerEventScheduled
);
745 Tick apicTimerEventTick
= apicTimerEvent
.when();
746 SERIALIZE_SCALAR(apicTimerEventTick
);
750 X86ISA::Interrupts::unserialize(Checkpoint
*cp
, const std::string
§ion
)
752 UNSERIALIZE_ARRAY(regs
, NUM_APIC_REGS
);
753 UNSERIALIZE_SCALAR(clock
);
754 UNSERIALIZE_SCALAR(pendingSmi
);
755 UNSERIALIZE_SCALAR(smiVector
);
756 UNSERIALIZE_SCALAR(pendingNmi
);
757 UNSERIALIZE_SCALAR(nmiVector
);
758 UNSERIALIZE_SCALAR(pendingExtInt
);
759 UNSERIALIZE_SCALAR(extIntVector
);
760 UNSERIALIZE_SCALAR(pendingInit
);
761 UNSERIALIZE_SCALAR(initVector
);
762 UNSERIALIZE_SCALAR(pendingStartup
);
763 UNSERIALIZE_SCALAR(startupVector
);
764 UNSERIALIZE_SCALAR(startedUp
);
765 UNSERIALIZE_SCALAR(pendingUnmaskableInt
);
766 UNSERIALIZE_SCALAR(pendingIPIs
);
767 UNSERIALIZE_SCALAR(IRRV
);
768 UNSERIALIZE_SCALAR(ISRV
);
769 bool apicTimerEventScheduled
;
770 UNSERIALIZE_SCALAR(apicTimerEventScheduled
);
771 if (apicTimerEventScheduled
) {
772 Tick apicTimerEventTick
;
773 UNSERIALIZE_SCALAR(apicTimerEventTick
);
774 if (apicTimerEvent
.scheduled()) {
775 reschedule(apicTimerEvent
, apicTimerEventTick
, true);
777 schedule(apicTimerEvent
, apicTimerEventTick
);
783 X86LocalApicParams::create()
785 return new X86ISA::Interrupts(this);