2 * Copyright (c) 2008 The Hewlett-Packard Development Company
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
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12 * modified or unmodified, in source code or in binary form.
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18 * redistributions in binary form must reproduce the above copyright
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23 * this software without specific prior written permission.
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40 #include "arch/x86/apicregs.hh"
41 #include "arch/x86/interrupts.hh"
42 #include "arch/x86/intmessage.hh"
43 #include "cpu/base.hh"
44 #include "dev/x86/i82094aa.hh"
45 #include "dev/x86/pc.hh"
46 #include "dev/x86/south_bridge.hh"
47 #include "mem/packet_access.hh"
48 #include "sim/system.hh"
51 divideFromConf(uint32_t conf
)
53 // This figures out what division we want from the division configuration
54 // register in the local APIC. The encoding is a little odd but it can
55 // be deciphered fairly easily.
56 int shift
= ((conf
& 0x8) >> 1) | (conf
& 0x3);
57 shift
= (shift
+ 1) % 8;
65 decodeAddr(Addr paddr
)
75 regNum
= APIC_VERSION
;
78 regNum
= APIC_TASK_PRIORITY
;
81 regNum
= APIC_ARBITRATION_PRIORITY
;
84 regNum
= APIC_PROCESSOR_PRIORITY
;
90 regNum
= APIC_LOGICAL_DESTINATION
;
93 regNum
= APIC_DESTINATION_FORMAT
;
96 regNum
= APIC_SPURIOUS_INTERRUPT_VECTOR
;
114 regNum
= APIC_IN_SERVICE((paddr
- 0x100) / 0x8);
132 regNum
= APIC_TRIGGER_MODE((paddr
- 0x180) / 0x8);
150 regNum
= APIC_INTERRUPT_REQUEST((paddr
- 0x200) / 0x8);
153 regNum
= APIC_ERROR_STATUS
;
156 regNum
= APIC_INTERRUPT_COMMAND_LOW
;
159 regNum
= APIC_INTERRUPT_COMMAND_HIGH
;
162 regNum
= APIC_LVT_TIMER
;
165 regNum
= APIC_LVT_THERMAL_SENSOR
;
168 regNum
= APIC_LVT_PERFORMANCE_MONITORING_COUNTERS
;
171 regNum
= APIC_LVT_LINT0
;
174 regNum
= APIC_LVT_LINT1
;
177 regNum
= APIC_LVT_ERROR
;
180 regNum
= APIC_INITIAL_COUNT
;
183 regNum
= APIC_CURRENT_COUNT
;
186 regNum
= APIC_DIVIDE_CONFIGURATION
;
189 // A reserved register field.
190 panic("Accessed reserved register field %#x.\n", paddr
);
198 X86ISA::Interrupts::read(PacketPtr pkt
)
200 Addr offset
= pkt
->getAddr() - pioAddr
;
201 //Make sure we're at least only accessing one register.
202 if ((offset
& ~mask(3)) != ((offset
+ pkt
->getSize()) & ~mask(3)))
203 panic("Accessed more than one register at a time in the APIC!\n");
204 ApicRegIndex reg
= decodeAddr(offset
);
205 uint32_t val
= htog(readReg(reg
));
207 "Reading Local APIC register %d at offset %#x as %#x.\n",
209 pkt
->setData(((uint8_t *)&val
) + (offset
& mask(3)));
210 pkt
->makeAtomicResponse();
215 X86ISA::Interrupts::write(PacketPtr pkt
)
217 Addr offset
= pkt
->getAddr() - pioAddr
;
218 //Make sure we're at least only accessing one register.
219 if ((offset
& ~mask(3)) != ((offset
+ pkt
->getSize()) & ~mask(3)))
220 panic("Accessed more than one register at a time in the APIC!\n");
221 ApicRegIndex reg
= decodeAddr(offset
);
222 uint32_t val
= regs
[reg
];
223 pkt
->writeData(((uint8_t *)&val
) + (offset
& mask(3)));
225 "Writing Local APIC register %d at offset %#x as %#x.\n",
226 reg
, offset
, gtoh(val
));
227 setReg(reg
, gtoh(val
));
228 pkt
->makeAtomicResponse();
232 X86ISA::Interrupts::requestInterrupt(uint8_t vector
,
233 uint8_t deliveryMode
, bool level
)
236 * Fixed and lowest-priority delivery mode interrupts are handled
237 * using the IRR/ISR registers, checking against the TPR, etc.
238 * The SMI, NMI, ExtInt, INIT, etc interrupts go straight through.
240 if (deliveryMode
== DeliveryMode::Fixed
||
241 deliveryMode
== DeliveryMode::LowestPriority
) {
242 DPRINTF(LocalApic
, "Interrupt is an %s.\n",
243 DeliveryMode::names
[deliveryMode
]);
244 // Queue up the interrupt in the IRR.
247 if (!getRegArrayBit(APIC_INTERRUPT_REQUEST_BASE
, vector
)) {
248 setRegArrayBit(APIC_INTERRUPT_REQUEST_BASE
, vector
);
250 setRegArrayBit(APIC_TRIGGER_MODE_BASE
, vector
);
252 clearRegArrayBit(APIC_TRIGGER_MODE_BASE
, vector
);
255 } else if (!DeliveryMode::isReserved(deliveryMode
)) {
256 DPRINTF(LocalApic
, "Interrupt is an %s.\n",
257 DeliveryMode::names
[deliveryMode
]);
258 if (deliveryMode
== DeliveryMode::SMI
&& !pendingSmi
) {
259 pendingUnmaskableInt
= pendingSmi
= true;
261 } else if (deliveryMode
== DeliveryMode::NMI
&& !pendingNmi
) {
262 pendingUnmaskableInt
= pendingNmi
= true;
264 } else if (deliveryMode
== DeliveryMode::ExtInt
&& !pendingExtInt
) {
265 pendingExtInt
= true;
266 extIntVector
= vector
;
267 } else if (deliveryMode
== DeliveryMode::INIT
&& !pendingInit
) {
268 pendingUnmaskableInt
= pendingInit
= true;
270 } else if (deliveryMode
== DeliveryMode::SIPI
&&
271 !pendingStartup
&& !startedUp
) {
272 pendingUnmaskableInt
= pendingStartup
= true;
273 startupVector
= vector
;
281 X86ISA::Interrupts::setCPU(BaseCPU
* newCPU
)
284 if (cpu
!= NULL
&& cpu
->cpuId() != newCPU
->cpuId()) {
285 panic("Local APICs can't be moved between CPUs"
286 " with different IDs.\n");
289 initialApicId
= cpu
->cpuId();
290 regs
[APIC_ID
] = (initialApicId
<< 24);
295 X86ISA::Interrupts::init()
297 BasicPioDevice::init();
298 Pc
* pc
= dynamic_cast<Pc
*>(platform
);
300 pc
->southBridge
->ioApic
->registerLocalApic(initialApicId
, this);
305 X86ISA::Interrupts::recvMessage(PacketPtr pkt
)
307 Addr offset
= pkt
->getAddr() - x86InterruptAddress(initialApicId
, 0);
308 assert(pkt
->cmd
== MemCmd::MessageReq
);
313 TriggerIntMessage message
= pkt
->get
<TriggerIntMessage
>();
315 "Got Trigger Interrupt message with vector %#x.\n",
318 requestInterrupt(message
.vector
,
319 message
.deliveryMode
, message
.trigger
);
323 panic("Local apic got unknown interrupt message at offset %#x.\n",
327 pkt
->makeAtomicResponse();
333 X86ISA::Interrupts::recvResponse(PacketPtr pkt
)
335 assert(!pkt
->isError());
336 assert(pkt
->cmd
== MemCmd::MessageResp
);
337 if (--pendingIPIs
== 0) {
338 InterruptCommandRegLow low
= regs
[APIC_INTERRUPT_COMMAND_LOW
];
339 // Record that the ICR is now idle.
340 low
.deliveryStatus
= 0;
341 regs
[APIC_INTERRUPT_COMMAND_LOW
] = low
;
345 DPRINTF(LocalApic
, "ICR is now idle.\n");
351 X86ISA::Interrupts::addressRanges(AddrRangeList
&range_list
)
354 Range
<Addr
> range
= RangeEx(x86LocalAPICAddress(initialApicId
, 0),
355 x86LocalAPICAddress(initialApicId
, 0) +
357 range_list
.push_back(range
);
358 pioAddr
= range
.start
;
363 X86ISA::Interrupts::getIntAddrRange(AddrRangeList
&range_list
)
366 range_list
.push_back(RangeEx(x86InterruptAddress(initialApicId
, 0),
367 x86InterruptAddress(initialApicId
, 0) +
368 PhysAddrAPICRangeSize
));
373 X86ISA::Interrupts::readReg(ApicRegIndex reg
)
375 if (reg
>= APIC_TRIGGER_MODE(0) &&
376 reg
<= APIC_TRIGGER_MODE(15)) {
377 panic("Local APIC Trigger Mode registers are unimplemented.\n");
380 case APIC_ARBITRATION_PRIORITY
:
381 panic("Local APIC Arbitration Priority register unimplemented.\n");
383 case APIC_PROCESSOR_PRIORITY
:
384 panic("Local APIC Processor Priority register unimplemented.\n");
386 case APIC_ERROR_STATUS
:
387 regs
[APIC_INTERNAL_STATE
] &= ~ULL(0x1);
389 case APIC_CURRENT_COUNT
:
391 if (apicTimerEvent
.scheduled()) {
393 // Compute how many m5 ticks happen per count.
394 uint64_t ticksPerCount
= clock
*
395 divideFromConf(regs
[APIC_DIVIDE_CONFIGURATION
]);
396 // Compute how many m5 ticks are left.
397 uint64_t val
= apicTimerEvent
.when() - curTick
;
398 // Turn that into a count.
399 val
= (val
+ ticksPerCount
- 1) / ticksPerCount
;
412 X86ISA::Interrupts::setReg(ApicRegIndex reg
, uint32_t val
)
414 uint32_t newVal
= val
;
415 if (reg
>= APIC_IN_SERVICE(0) &&
416 reg
<= APIC_IN_SERVICE(15)) {
417 panic("Local APIC In-Service registers are unimplemented.\n");
419 if (reg
>= APIC_TRIGGER_MODE(0) &&
420 reg
<= APIC_TRIGGER_MODE(15)) {
421 panic("Local APIC Trigger Mode registers are unimplemented.\n");
423 if (reg
>= APIC_INTERRUPT_REQUEST(0) &&
424 reg
<= APIC_INTERRUPT_REQUEST(15)) {
425 panic("Local APIC Interrupt Request registers "
426 "are unimplemented.\n");
433 // The Local APIC Version register is read only.
435 case APIC_TASK_PRIORITY
:
438 case APIC_ARBITRATION_PRIORITY
:
439 panic("Local APIC Arbitration Priority register unimplemented.\n");
441 case APIC_PROCESSOR_PRIORITY
:
442 panic("Local APIC Processor Priority register unimplemented.\n");
445 // Remove the interrupt that just completed from the local apic state.
446 clearRegArrayBit(APIC_IN_SERVICE_BASE
, ISRV
);
449 case APIC_LOGICAL_DESTINATION
:
450 newVal
= val
& 0xFF000000;
452 case APIC_DESTINATION_FORMAT
:
453 newVal
= val
| 0x0FFFFFFF;
455 case APIC_SPURIOUS_INTERRUPT_VECTOR
:
456 regs
[APIC_INTERNAL_STATE
] &= ~ULL(1 << 1);
457 regs
[APIC_INTERNAL_STATE
] |= val
& (1 << 8);
459 warn("Focus processor checking not implemented.\n");
461 case APIC_ERROR_STATUS
:
463 if (regs
[APIC_INTERNAL_STATE
] & 0x1) {
464 regs
[APIC_INTERNAL_STATE
] &= ~ULL(0x1);
467 regs
[APIC_INTERNAL_STATE
] |= ULL(0x1);
473 case APIC_INTERRUPT_COMMAND_LOW
:
475 InterruptCommandRegLow low
= regs
[APIC_INTERRUPT_COMMAND_LOW
];
476 // Check if we're already sending an IPI.
477 if (low
.deliveryStatus
) {
482 InterruptCommandRegHigh high
= regs
[APIC_INTERRUPT_COMMAND_HIGH
];
483 // Record that an IPI is being sent.
484 low
.deliveryStatus
= 1;
485 TriggerIntMessage message
= 0;
486 message
.destination
= high
.destination
;
487 message
.vector
= low
.vector
;
488 message
.deliveryMode
= low
.deliveryMode
;
489 message
.destMode
= low
.destMode
;
490 message
.level
= low
.level
;
491 message
.trigger
= low
.trigger
;
492 bool timing
= sys
->getMemoryMode() == Enums::timing
;
493 // Be careful no updates of the delivery status bit get lost.
494 regs
[APIC_INTERRUPT_COMMAND_LOW
] = low
;
496 int numContexts
= sys
->numContexts();
497 switch (low
.destShorthand
) {
499 if (message
.deliveryMode
== DeliveryMode::LowestPriority
) {
500 panic("Lowest priority delivery mode "
501 "IPIs aren't implemented.\n");
503 if (message
.destMode
== 1) {
504 int dest
= message
.destination
;
505 hack_once("Assuming logical destinations are 1 << id.\n");
506 for (int i
= 0; i
< numContexts
; i
++) {
512 if (message
.destination
== 0xFF) {
513 for (int i
= 0; i
< numContexts
; i
++) {
514 if (i
== initialApicId
) {
515 requestInterrupt(message
.vector
,
516 message
.deliveryMode
, message
.trigger
);
522 if (message
.destination
== initialApicId
) {
523 requestInterrupt(message
.vector
,
524 message
.deliveryMode
, message
.trigger
);
526 apics
.push_back(message
.destination
);
533 requestInterrupt(message
.vector
,
534 message
.deliveryMode
, message
.trigger
);
537 requestInterrupt(message
.vector
,
538 message
.deliveryMode
, message
.trigger
);
542 for (int i
= 0; i
< numContexts
; i
++) {
543 if (i
!= initialApicId
) {
550 pendingIPIs
+= apics
.size();
551 intPort
->sendMessage(apics
, message
, timing
);
552 newVal
= regs
[APIC_INTERRUPT_COMMAND_LOW
];
556 case APIC_LVT_THERMAL_SENSOR
:
557 case APIC_LVT_PERFORMANCE_MONITORING_COUNTERS
:
562 uint64_t readOnlyMask
= (1 << 12) | (1 << 14);
563 newVal
= (val
& ~readOnlyMask
) |
564 (regs
[reg
] & readOnlyMask
);
567 case APIC_INITIAL_COUNT
:
570 newVal
= bits(val
, 31, 0);
571 // Compute how many timer ticks we're being programmed for.
572 uint64_t newCount
= newVal
*
573 (divideFromConf(regs
[APIC_DIVIDE_CONFIGURATION
]));
574 // Schedule on the edge of the next tick plus the new count.
575 Tick offset
= curTick
% clock
;
577 reschedule(apicTimerEvent
,
578 curTick
+ (newCount
+ 1) * clock
- offset
, true);
580 reschedule(apicTimerEvent
,
581 curTick
+ newCount
* clock
, true);
585 case APIC_CURRENT_COUNT
:
586 //Local APIC Current Count register is read only.
588 case APIC_DIVIDE_CONFIGURATION
:
599 X86ISA::Interrupts::Interrupts(Params
* p
) :
600 BasicPioDevice(p
), IntDev(this), latency(p
->pio_latency
), clock(0),
601 apicTimerEvent(this),
602 pendingSmi(false), smiVector(0),
603 pendingNmi(false), nmiVector(0),
604 pendingExtInt(false), extIntVector(0),
605 pendingInit(false), initVector(0),
606 pendingStartup(false), startupVector(0),
607 startedUp(false), pendingUnmaskableInt(false),
608 pendingIPIs(0), cpu(NULL
)
611 memset(regs
, 0, sizeof(regs
));
612 //Set the local apic DFR to the flat model.
613 regs
[APIC_DESTINATION_FORMAT
] = (uint32_t)(-1);
620 X86ISA::Interrupts::checkInterrupts(ThreadContext
*tc
) const
622 RFLAGS rflags
= tc
->readMiscRegNoEffect(MISCREG_RFLAGS
);
623 if (pendingUnmaskableInt
) {
624 DPRINTF(LocalApic
, "Reported pending unmaskable interrupt.\n");
629 DPRINTF(LocalApic
, "Reported pending external interrupt.\n");
632 if (IRRV
> ISRV
&& bits(IRRV
, 7, 4) >
633 bits(regs
[APIC_TASK_PRIORITY
], 7, 4)) {
634 DPRINTF(LocalApic
, "Reported pending regular interrupt.\n");
642 X86ISA::Interrupts::getInterrupt(ThreadContext
*tc
)
644 assert(checkInterrupts(tc
));
645 // These are all probably fairly uncommon, so we'll make them easier to
647 if (pendingUnmaskableInt
) {
649 DPRINTF(LocalApic
, "Generated SMI fault object.\n");
650 return new SystemManagementInterrupt();
651 } else if (pendingNmi
) {
652 DPRINTF(LocalApic
, "Generated NMI fault object.\n");
653 return new NonMaskableInterrupt(nmiVector
);
654 } else if (pendingInit
) {
655 DPRINTF(LocalApic
, "Generated INIT fault object.\n");
656 return new InitInterrupt(initVector
);
657 } else if (pendingStartup
) {
658 DPRINTF(LocalApic
, "Generating SIPI fault object.\n");
659 return new StartupInterrupt(startupVector
);
661 panic("pendingUnmaskableInt set, but no unmaskable "
662 "ints were pending.\n");
665 } else if (pendingExtInt
) {
666 DPRINTF(LocalApic
, "Generated external interrupt fault object.\n");
667 return new ExternalInterrupt(extIntVector
);
669 DPRINTF(LocalApic
, "Generated regular interrupt fault object.\n");
670 // The only thing left are fixed and lowest priority interrupts.
671 return new ExternalInterrupt(IRRV
);
676 X86ISA::Interrupts::updateIntrInfo(ThreadContext
*tc
)
678 assert(checkInterrupts(tc
));
679 if (pendingUnmaskableInt
) {
681 DPRINTF(LocalApic
, "SMI sent to core.\n");
683 } else if (pendingNmi
) {
684 DPRINTF(LocalApic
, "NMI sent to core.\n");
686 } else if (pendingInit
) {
687 DPRINTF(LocalApic
, "Init sent to core.\n");
690 } else if (pendingStartup
) {
691 DPRINTF(LocalApic
, "SIPI sent to core.\n");
692 pendingStartup
= false;
695 if (!(pendingSmi
|| pendingNmi
|| pendingInit
|| pendingStartup
))
696 pendingUnmaskableInt
= false;
697 } else if (pendingExtInt
) {
698 pendingExtInt
= false;
700 DPRINTF(LocalApic
, "Interrupt %d sent to core.\n", IRRV
);
701 // Mark the interrupt as "in service".
703 setRegArrayBit(APIC_IN_SERVICE_BASE
, ISRV
);
704 // Clear it out of the IRR.
705 clearRegArrayBit(APIC_INTERRUPT_REQUEST_BASE
, IRRV
);
711 X86LocalApicParams::create()
713 return new X86ISA::Interrupts(this);